L99PM60JTR - STMicroelectronics

L99PM60J
Power management IC with LIN transceiver
Features
■
One 5 V low-drop voltage regulators (100 mA,
continuous mode)
■
No electrolytic capacitor required on regulator
output (only 220 nF ceramic typ.)
■
Ultra-low quiescent current in VBAT-standby
(7 µA) and V1-standby (45 µA)
■
Window watchdog and advanced fail-safe
functionality
■
Configurable fail-safe output
■
Programmable reset threshold (4.6 V; 3.5 V)
■
VS monitoring / temperature measurement
■
LIN 2.1 compliant (SAE J2602 compatible)
transceiver
■
High-speed LIN Flash mode up to 100 Kbit/s
■
ST SPI interface for mode control and
diagnostics
■
2 high-side drivers, e.g. LED or HALL
(RDSon,typ = 7 Ω)
■
2 low-side drivers (RDSon,typ = 2 Ω)
■
Outputs are short-circuit protected
■
Direct drive feature for high sides
■
Temperature warning and thermal shutdown
*$3*&)7
PowerSSO-16
Description
The L99PM60J is a power management system
IC that features one low-drop regulator, a direct
drive for high-side drivers, and a LIN 2.1
compliant SAE J2602 transceiver.
The integrated standard serial peripheral
interface (SPI) controls all L99PM60J operation
modes and provides driver diagnostic functions.
Applications
■
Automotive ECUs requiring LIN and power
management features such as door zone, and
body control modules
Table 1.
Device summary
Order codes
Package
PowerSSO-16
September 2013
Doc ID 18309 Rev 6
Tube
Tape and reel
L99PM60J
L99PM60JTR
1/75
www.st.com
1
Contents
L99PM60J
Contents
1
Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.1.1
Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2
Voltage regulator behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2
Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3
V1-standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4
VBAT-standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Wake up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Window – watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7
Fail Safe mode
2.7.1
Temporary failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7.2
Nonrecoverable failures – entering forced VBAT-standby mode . . . . . . . . 19
2.7.3
Fail Safe Output (OUT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset output (NRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.9
LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.9.1
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.9.2
Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial Peripheral Interface (ST SPI Standard) . . . . . . . . . . . . . . . . . . . . . 23
Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1
High side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1
4
OUT1 reprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2
Low side driver outputs REL1, REL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3
SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1
2/75
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8
2.10
3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VS overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Doc ID 18309 Rev 6
L99PM60J
Contents
4.2
VS undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 28
5
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7
6.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.1
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.3
Power-on reset (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4.4
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4.5
Reset output (V1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.6
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.7
High-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.8
Low-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.9
Direct drive / voltage supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.10
LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.11
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ST SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1
SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1.2
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1.3
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1.4
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.1.5
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1.6
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.1.7
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.1.8
Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . 52
7.1.9
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.1.10
Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . 53
7.1.11
Read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.1.12
Format of data shifted out at SDO during ‘Read and Clear Status’
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Doc ID 18309 Rev 6
3/75
Contents
L99PM60J
7.1.13
7.2
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.2.1
8
10
4/75
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.1
9
Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Package and Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.2
PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.3
PowerSSO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Doc ID 18309 Rev 6
L99PM60J
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin descriptions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Wake up sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Failures management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-on reset (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset output (V1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Input: DRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Output: VSOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LIN transmit data input: pin TXD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
LIN receive data output: pin RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LIN Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Input CSN for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Inputs: CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Output DO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
RXDL/NINT timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Detailed global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Addressing mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Write command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Format of data shifted out at SDO during write cycle: global status register . . . . . . . . . . . 52
Format of data shifted out at SDO during write cycle: data byte . . . . . . . . . . . . . . . . . . . . 52
Read command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Format of data shifted out at SDO during read cycle: global status register. . . . . . . . . . . . 53
Format of data shifted out at SDO during read cycle: data byte . . . . . . . . . . . . . . . . . . . . . 53
Read and clear status’ command format‘ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Format of data shifted out at SDO during ‘Read and Clear Status’ operation: global status
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Doc ID 18309 Rev 6
5/75
List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
6/75
L99PM60J
Format of data shifted out at SDO during read cycle: data byte . . . . . . . . . . . . . . . . . . . . . 55
Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ID-Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Family identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Silicon version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Silicon version code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SPI-frame-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SPI register: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SPI register: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI register: CTRL register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI register: STAT register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Overview of control register data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Control register 1, 1st data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Control register 1, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Control register 2, 1st data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Control register 2, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Overview of status register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Status register 1, command and data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Status register 1, data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Status register 2, command and data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Status register 2, data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Status register 3, command and data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Status register 3, data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Status register 4, command and data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Status register 4, data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Status register 4, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PowerSSO-16 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Doc ID 18309 Rev 6
L99PM60J
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connection PowerSSO-16 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating modes – main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog in FLASH Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Recovery after forced VBAT due to multiple watchdog failure . . . . . . . . . . . . . . . . . . . . . . 20
Recovery after forced VBAT due to multiple TSD2 failure . . . . . . . . . . . . . . . . . . . . . . . . . 20
Recovery after forced VBAT due to short at V1 failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Watchdog timing (missing watchdog trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SPI – input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPI – output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPI transition parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SPI global status register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Read configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Write configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Format of data shifted out at SDO during ‘Read and Clear Status’ operation . . . . . . . . . . 55
Thermal data of PowerSSO-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . . 68
V1 thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Thermal fitting model of V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PowerSSO-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PowerSSO-16 tape and reel shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Doc ID 18309 Rev 6
7/75
Block diagram and pin descriptions
1
L99PM60J
Block diagram and pin descriptions
Figure 1.
block diagram
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Table 2.
Pin
Symbol
1
GND
2
NRESET
3
DO
SPI: serial data output
4
DI
SPI: serial data input
5
V1
Voltage regulator 1 output: 5 V supply e.g. micro controller
6
CLK
7
RxD/NINT
8
9
8/75
Pin descriptions and functions
Function
Ground
NReset output to micro controller; Internal pull-up of typ. 100 KΩ (reset
state = LOW)
SPI: serial clock input
Receiver output of the LIN 2.1 transceiver or interrupt:
DRV/VSM/TMP Direct drive for high-side drivers OUT1/2; VS and temperature monitoring
CSN
SPI: chip select not input
Doc ID 18309 Rev 6
L99PM60J
Block diagram and pin descriptions
Table 2.
Pin descriptions and functions (continued)
Pin
Symbol
Function
10
OUT2
High side drivers (7 Ω, typ.): to supply e.g. LED's, HALL sensors, external
contacts
11
OUT1/FSO
High side driver (7 Ω, typ.): to supply e.g. LED's, HALL sensors, external
contacts
12
TxD
13
VS
14
REL1
Low side driver (2 Ω typ.): e.g. relay
15
REL2
Low side driver (2 Ω typ.): e.g. relay
16
LIN
Figure 2.
Transmitter input of the LIN 2.1 transceiver
Power supply voltage
LIN bus line
Pin connection PowerSSO-16 (top view)
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Note:
It is recommended to connect pin GND directly to the Heat Slug.
Doc ID 18309 Rev 6
9/75
Detailed description
L99PM60J
2
Detailed description
2.1
Voltage regulator
The L99PM60J contains a fully protected low drop voltage regulator, which is designed for
very fast transient response. The output voltage is stable with loads capacitors > 220 nF
The V1 voltage regulator provides 5 V supply voltage and up to 100 mA continuous load
current and is mainly intended for supply of the system microcontroller. The V1 regulator is
embedded in the power management and failsafe functionality of the device and operates
according to the selected operating mode.
In addition the regulator V1 drives the L99PM60J internal 5 V loads. The voltage regulator is
protected against overload and overtemperature. An external reverse current protection has
to be provided by the application circuitry to prevent the input capacitor from being
discharged by negative transients or low input voltage. Current limitation of the regulator
ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic
load capacitors > 220 nF.
If device temperature exceeds TSD1 threshold, all outputs (OUTx, RELx, LIN) are
deactivated except V1. Hence the micro controller has the possibility for interaction or error
logging. In case of exceeding TSD2 threshold (TSD2 > TSD1), also V1 is deactivated (see
state chart Figure 11). A timer is started and the voltage regulator is deactivated for tTSD.
During this time, all other walk-up sources (LIN) are disabled. After 1 sec., the voltage
regulator tries to restart automatically. If the restart fails 7 times without clearing and thermal
shutdown condition still exists, the L99PM60J enters the VBAT-standby mode.
In case of short to GND at “V1” after initial turn on (V1 < V1fail for t > tv1short) the L99PM60J
enters the VBAT-standby mode. Reactivation (wake-up) of the device can be achieved with
signals from LIN.
2.1.1
Voltage regulator failure
The V1, regulator output voltage is monitored.
In case of a drop below the V1 – fail thresholds (V1 < V1fail for t > tV1fail), the V1 -fail bit is
latched. The fail bits can be cleared by a dedicated SPI command.
Short to ground detection
At power-on, in case of short detection on V1, the regulator output switches off after tV1short
and the L99PM60J turns to forced VBAT-standby mode. The forced VBAT TSD2/SHTV1 and
V1fail lists are set.
During Normal mode, once the regulator exceeded the V1fail threshold, in case of short
detection on V1, the device turns to force VBAT-standby mode only after thermal shutdown
TSD2 detection. In this case the forced VBAT TSD2/SHTV1 bit is set.
V1 undervoltage warning
For the L99PM60J 2 different V1 reset thresholds can be selected. The higher threshold
VRT2 is set by default. If the lower threshold is selected the V1 undervoltage warning flag is
set, if the voltage on V1 output drops below the higher threshold. This Bit is latched and can
be read and optionally cleared.
10/75
Doc ID 18309 Rev 6
L99PM60J
Detailed description
V1 failure failsafe activation
If the voltage on V1 output drops below the selected V1 reset threshold the RESET output is
pulled to ground. If the V1 output voltage remains below the V1 reset threshold for longer
than tFSO, fail safe mode is activated additionally. For more details about failsafe please
refer to chapter Fail safe mode
2.1.2
Voltage regulator behaviour
Figure 3.
Supply voltage operation summary
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Power control in operating modes
The L99PM60J can be operated in 4 different operating modes:
2.2.1
●
Active
●
Flash
●
V1-standby
●
VBAT-standby
Active mode
All functions are available and the device is controlled by the ST SPI Interface.
Doc ID 18309 Rev 6
11/75
Detailed description
2.2.2
L99PM60J
Flash mode
To program the system microcontroller, the L99PM60J can be operated in Flash Mode
where the internal watchdog is disabled. In addition the SPI-Interface and low power modes
are not available in Flash Mode.
The mode can be entered if the following condition is applied
VCSN > VFlash
At exit from Flash Mode (VCSN < Vflash) no NReset pulse is generated and the watchdog
starts with a Long Open Window.
Note:
“High” level for flash mode selection is VCSN > Vflash. For all other operation modes,
standard 5V logic signals are required.
2.2.3
V1-standby mode
The transition from Active Mode to V1-standby mode is controlled by SPI.
To supply the micro controller in a low power mode, the voltage regulator 1 (V1) remains
active. In order to reduce the current consumption, the regulator goes in low current mode
as soon as the supply current of the microcontroller goes below the ICMP current threshold.
At this transition, the L99PM60J also deactivates the internal watchdog.
Relay outputs and LIN Transmitter are switched off in V1-standby Mode. High side Outputs
remain in the configuration programmed prior to the standby command.
A cyclic contact supply (for cyclic monitoring of external contacts) can be activated by SPI
and using the Direct Drive Input (DRV).
Each wake up event sets the device into the active mode and forces the RxD/NINT pin to
the low level.
Note:
Input TxD must be at recessive (high) level and CSN must be at high level in order to
achieve minimum standby current in V1-standby Mode.
Interrupt
The interrupt signal (linked to RxDL/NINT internally) indicates a wake-up event from
V1-standby mode. In case of activity on LIN or SPI access the NINT pin is pulled low for
tInterupt
In case of V1-standby mode and (IV1 > ICMP), the device remains in standby mode, the V1
regulator switches to high current mode and the watchdog starts. No Interrupt signal is
generated.
2.2.4
VBAT-standby mode
The transition from Active Mode to VBAT-standby mode is initiated by an SPI command.
In VBAT-standby Mode, the voltage regulator, relay outputs and LIN transmitter are switched
off. High side outputs remain in the configuration programmed prior to the standby
command.
In VBAT-standby mode the current consumption of the L99PM60J is reduced to a minimum
level.
12/75
Doc ID 18309 Rev 6
L99PM60J
Note:
Detailed description
Inputs TXDL and CSN must be terminated to GND in VBAT-standby to achieve minimum
standby current.
This can be achieved with the internal ESD protection diodes of the microcontroller
(microcontroller is not supplied in this mode; V1 is pulled to GND).
2.3
Wake up from standby modes
A wake-up from standby mode switches the device to active mode. This can be initiated by
one or more of the following sources:
Table 3.
Wake up sources
Wake up source
LIN bus activity
IV1 > ICMP
SPI Access
Description
Always active
Device remains in V1-standby mode with watchdog enabled (If
ICMP = 0) and V1 goes into High Current Mode (Increased Current
Consumption). No interrupt is generated.
Always active (except in VBAT-standby mode)
Wake up event: CSN is low and first rising edge on CLK
All wake-up events from V1-standby mode (except IV1 > ICMP) are indicated to the
microcontroller by a low-pulse at RxDL/NINT (duration: tInterupt)
Wake-up from V1-standby by SPI Access might be used to check the interrupt service
handler.
2.4
Cyclic contact supply
In V1-standby mode, any high side driver output (OUT1..2) can be used to supply external
contacts. Direct drive feature for high side drivers must be enabled by SPI to control the high
side driver outputs by DRV/VSM/TMP pin.
Doc ID 18309 Rev 6
13/75
Detailed description
L99PM60J
2.5
Functional overview (truth table)
Table 4.
Functional overview (truth table)
Operating Modes
Function
Comments
V1-standby
static mode
(cyclic sense)
Active mode
VBAT-standby
static mode
(cyclic sense)
On
On(1)
Off
On
On
Off
On
Off
(on: I_V1 > ICMP-threshold Off
and ICMP = 0)
Direct drive
On / Off(2)
On / Off(2)
Off
Relay driver
On
Off
Off
Off(3)
Off(3)
Voltage-regulator, V1
VOUT = 5 V
Reset-generator
Window watchdog
V1 monitor
LIN
LIN 2.1
On
FSO (if configured by
SPI), active by default
Fail safe output
OUT1/FSO OFF(4) OUT1/FSO OFF(4)
OUT1/FSO OFF(4)
Oscillator
On
(5)
Off
VS-monitor
On
(6)
Off
1. Supply the processor in low current mode.
2. Selectable from SPI
3. The bus state is internally stored when going to standby mode. A change of bus state leads to a wake-up after exceeding of
internal filter time
4. ON in Failsafe Condition: If Standby mode is entered with active Fail Safe mode, the output remains ON in Standby mode.
5. Activated when direct drive feature is enabled from SPI and DRV/VSM/TMP pin is high.
6. ON when OUT1/2 are activated during direct drive
14/75
Doc ID 18309 Rev 6
L99PM60J
Figure 4.
Detailed description
Operating modes – main states
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2.6
Window – watchdog
During normal operation, the watchdog monitors the micro controller within a tSW trigger
cycle
In VBAT-standby and Flash program modes, the watchdog circuit is automatically disabled.
After wake-up, the watchdog starts with a long open window. After serving the watchdog, the
microcontroller may send the device back to V1-standby mode
After power-on or standby mode, the watchdog is started with a long open window tLW. The
long open window allows the micro controller to run its own setup and then to trigger the
Doc ID 18309 Rev 6
15/75
Detailed description
L99PM60J
watchdog via the SPI. The trigger is finally accepted when the CSN input becomes HIGH
after the transmission of the SPI word.
Writing ‘1’ to the watchdog trigger bit terminates the long open window and start the window
watchdog Subsequently, the micro controller has to serve the watchdog by alternating the
watchdog trigger bit within the safe trigger area (refer to watchdog chapter). A correct
watchdog trigger signal immediately starts the next cycle.
After 8 watchdog failures in sequence, the V1 regulator is switched off for tV1Off If
subsequently, 7 additional watchdog failures occur, the V1 regulator is completely turned off
and the device goes into VBAT-standby mode until a walk-up occurs.
In case of a Watchdog failure, the outputs (RELx, OUTx) are switched off and the device
enters fail safe mode (i. e. all control registers are set to default values, except OUT1
when not used as FSO.)
The following diagrams illustrate the Watchdog behavior of the L99PM60J. The diagrams
are split into 3 parts. First diagram shows the functional behavior of the watchdog without
any error. The second diagram covers the behavior covering all the error conditions, which
can affect the watchdog behavior. Third diagram shows the transition in and out of FLASH
mode. All three diagrams can be overlapped to get all the possible state transitions under all
circumstances. For a better readability, those transitions have been split in normal
operating, operating with errors and flash mode.
Figure 5.
Watchdog in normal operating mode (no errors)
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16/75
Doc ID 18309 Rev 6
L99PM60J
Detailed description
Figure 6.
Watchdog with error conditions
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Doc ID 18309 Rev 6
17/75
Detailed description
L99PM60J
2.7
Fail Safe mode
2.7.1
Temporary failures
L99PM60J enters Fail Safe mode in case of:
●
●
Watchdog failure
V1 turn on failure
–
●
V1 short (V1 < V1fail for t > tv1short)
V1 undervoltage (V1 < Vrth for t > tUV1)
–
Fail Safe Mode only entered if VS > VSUV
●
Thermal Shutdown TSD2
●
SPI failure
–
DI stuck to GND or VCC (SPI frame = ’00 00’ or ‘FF FF’)
The Fail Safe functionality is also available in V1-standby Mode. During V1-standby Mode the
Fails Safe Mode is entered in the following cases:
●
V1 undervoltage (V1 < VRTH for t > tV1FS)
–
Fail Safe Mode only entered if VS > VSUV
●
Watchdog failure (if watchdog still running due to IV1 > ICMP)
●
Thermal Shutdown TSD2
In Fail Safe Mode the L99PM60J returns to a default state with all outputs turned off. The
Fail Safe condition is indicated to the remaining system. The conditions during Fails Safe
Mode are:
●
All outputs are turned off
●
All Control Registers are set to default values (except OUT1/FSO configuration).
Write operations to Control Registers are blocked until the Fail Safe condition is
cleared
●
LIN Transmitter and SPI remains on
●
Corresponding Failure Bits in Status Registers are set.
●
FSO Bit (Bit 0 Global Status Register) is set
●
OUT1/FSO is activated if configured as Fail Safe Output
OUT1 is configured as Fail Safe Output unless it is disabled by SPI.
If the Fail Safe Mode was entered it keeps active until the Fail safe condition is removed and
the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe, the actions to
quit Fail safe Mode can be different.
18/75
Doc ID 18309 Rev 6
L99PM60J
Detailed description
Table 5.
Fail safe conditions and exit modes
Failure source
µC (oscillator)
Failure condition
Diagnosis
Exit from Fail Safe Mode
Watchdog, early write
failure or expired window
Failsafe = 1;
WDfail = n + 1
Propper trigger in Window
mode and read fail safe bit
Short at turn-on
Failsafe = 1; forced sleep
TSD2/SHTV1 = 1
Read&Clear SR3 after
wake
V1
V1 < Vrth for t > tFSO
Failsafe = 1; V1fail = 1(1)
(Failsafe mode only
entered when VS > VSUV)
Temperature
Tj > TSD2
Failsafe = 1; TW = 1;
TSD1 = 1; TSD2 = 1
Tj < TSD2
Read&Clear SR4
SPI
DI short to GND or VCC
Failsafe = 1
Valid SPI command
V1 > Vrth
Read Failsafe bit
1. if V1 < V1fail (for t >tv1fail)
The failsafe bit is located in the Global Status Register (Bit 0)
2.7.2
Nonrecoverable failures – entering forced VBAT-standby mode
If the failsafe condition persists and all attempts to return to normal system operation fail, the
L99PM60J enters the Forced Vbatstby Mode in order to prevent damage to the system. The
Forced Vbatstby Mode can be terminated by any regular wake-up event. The root cause of
the Forced Vbatstby is indicated in the SPI Status Registers
The Forced Vbatstby Mode is entered in case of:
Table 6.
●
Multiple Watchdog Failures: Forced Sleep WD = 1 (15x watchdog failure)
●
Multiple Thermal Shutdown 2: Forced Sleep TSD2/SHTV1 = 1 (7x TSD2)
●
V1 short at turn-on: Forced Sleep TSD2/SHTV1 = 1 (V1 < V1fail for t > tv1short)
Failures management
Failure Source
Failure Condition
Diagnosis
Exit from Failsafe Mode
µC (Oscillator)
15 consecutive
Watchdog Failures
Failsafe=1
ForcedSleepWD =1
Wake-up
TRIG=1 during LOWi
Read & Clear SR3
V1
short at turn-on
Failsafe=1
ForcedSleepTSD2/SHTV1=1
Read&Clear SR3 after wake-up
7 times TSD2
Failsafe=1
TW=1
TSD1=1
TSD2=1
ForcedSleepTSD2/SHTV1=1
Read&Clear SR4 after wake-up
Read&Clear SR3 after wake-up
Temperature
Doc ID 18309 Rev 6
19/75
Detailed description
Figure 8.
L99PM60J
Recovery after forced VBAT due to multiple watchdog failure
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Doc ID 18309 Rev 6
L99PM60J
Detailed description
Figure 10. Recovery after forced VBAT due to short at V1 failure
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2.7.3
Fail Safe Output (OUT1)
The device provides a high side output (OUT1) which can be used as Failsafe output. The
default configuration after power on for OUT1 is Failsafe output.
The Failsafe output is protected against
●
Overvoltage and undervoltage (undervoltage can be masked by SPI for OUT1).
See Control Register 2.
●
Overcurrent
In case of overcurrent condition, FSO switches off. The according status bit is latched and
can be read and optionally cleared by SPI. The drivers remain off until the status is cleared.
In case overvoltage or undervoltage condition, FSO is switched off. The according status bit
is latched and can be read and optionally cleared by SPI. The drivers remain off until the
status is cleared.
With the OUT UV shutdown enable bit (Control Register 2) the FSO can be excluded from a
switch off in case of Vs Undervoltage. If the bit is set to ‘1’ the driver switches off, otherwise
the drivers remain on.
In case of open-load condition, the according status register is latched. The status can be
read and optionally cleared by SPI. The FSO is not switch off.
Note:
The maximum voltage and current applied to the High Side Outputs is specified in chapter 4
‘Absolute Maximum Ratings’. Appropriate external protection may be required in order to
respect these limits under application conditions.
Doc ID 18309 Rev 6
21/75
Detailed description
2.8
L99PM60J
Reset output (NRESET)
If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output
“NRESET” is pulled up by internal pull up resistor to V1 voltage after a reset delay time
tReset. This is necessary for a defined start of the micro controller when the application is
switched on. Since the NRESET output is realized as an open drain output it is also possible
to connect an external NRESET open drain NRESET source to the output. It must be
considered that as soon the NRESET is released from the L99PM60J the watchdog timing
starts.
A reset pulse tReset is generated in case of:
2.9
●
V1 drops below Vrth (configurable by SPI) for more than V1UFT
●
Watchdog failure
LIN bus interface
General features:
●
Speed communication up to 20kbit/s.
●
LIN 2.1 compliant (SAE J2602 compatible) transceiver.
●
Function range from +40V to -18V DC at LIN Pin.
●
GND disconnection fail safe at module level.
●
Off mode: does not disturb network.
●
GND shift operation at system level.
●
Micro controller Interface with CMOS compatible I/O pins.
●
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
●
Matched output slopes and propagation delay
In order to further reduce the current consumption in standby mode, the integrated LIN bus
interface offers an ultra low current consumption.
2.9.1
Error handling
The L99PM60J provides the following 3 error handling features which are not described in
the LIN Spec. Revision 2.1, but are realized in different stand alone LIN transceivers / micro
controllers to switch the application back to normal operation mode.
At Vs > Vpor (i.e. Vs power-on reset threshold), the LIN transceiver is enabled.
The LIN transmitter is disabled in case of the following errors:
●
Dominant TxDL time out
●
LIN permanent recessive
●
Thermal shutdown 1
●
VS overvoltage / VS undervoltage
The LIN receiver is not disabled in case of any failure condition.
Dominant TxD time out
If TXD is in dominant state (low) for more than tdom(TXDL)(typ) the transmitter is disabled. The
status bit is latched and can be read and optionally cleared by SPI. The transmitter remains
disabled until the status register is cleared. This feature can be disabled via SPI.
22/75
Doc ID 18309 Rev 6
L99PM60J
Detailed description
Permanent recessive
If TXD changes to dominant (low) state but RXD signal does not follow within tLIN, the
transmitter is disabled. The Status bit is latched and can be read and optionally cleared by
SPI. The transmitter remains disabled until the status register is cleared.
Permanent dominant
If the bus state is dominant (low) for more than tdom(TXDL) (typ.) a permanent dominant status
is detected. The Status bit is latched and can be read and optionally cleared by SPI. The
transmitter is not switched off
2.9.2
Wake up (from LIN)
In standby mode the L99PM60J can receive a wake up from LIN bus. For the wake up
feature the L99PM60J logic differentiates two different conditions.
Normal wake up
Normal wake up can occur when the LIN transceiver was set in standby mode while LIN
was in recessive (high) state. A dominant level at LIN for t > tlinbus, switches the L99PM60J
to active mode. A interrupt is generated at the RXD/NINT pin.
Wake up from short to GND condition
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for tlinbus, switches the L99PM60J to active mode. An interrupt is
generated at the RXD/NINT pin.
Note:
A wake up caused by a message on the bus starts the voltage regulator and the
microcontroller to switch the application back to normal operation mode.
2.10
Serial Peripheral Interface (ST SPI Standard)
A 16 bit SPI is used for bi-directional communication with the micro controller.
During active mode, the SPI
●
triggers the watchdog
●
controls the modes and status of all L99PM60J modules (incl. input and output drivers)
●
provides driver output diagnostic
●
provide L99PM60J diagnostic (incl. overtemperature warning, L99PM60J operation
status)
The SPI can be driven by a micro controller with its SPI peripheral running in following
mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to micro controller with a built-in SPI. Only three CMOS-compatible
output pins and one input pin are needed to communicate with the device. A fault condition
can be detected by setting CSN to low. If CSN = 0, the DO-pin reflects the global error flag
(fault condition) of the device.
Doc ID 18309 Rev 6
23/75
Detailed description
L99PM60J
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) is in high impedance state. A low signal activates the output driver and a
serial communication can be started. The state during CSN = 0 is called a communication
frame.
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI is
sampled at the rising edge of the CLK signal and shifted into an internal 16 bit shift register.
At the rising edge of the CSN signal the contents of the shift register is transferred to Data
Input Register. The writing to the selected Data Input Register is only enabled if exactly 16
bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame is ignored. This safety function is
implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and goes from high
impedance to a low or high level depending on the global error flag (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin transfers the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK shifts the next bit out.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the
falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to fCLK.
24/75
Doc ID 18309 Rev 6
L99PM60J
Protection and diagnosis
3
Protection and diagnosis
3.1
High side driver outputs
The device provides a total of 2 high side outputs Out1,2, (7 Ω typ. at @ 25C) to drive e.g.
LED's or hall sensors
The high side outputs are protected against
●
Overvoltage and undervoltage (undervoltage can be masked by SPI for OUT1).
See Section : Control Register 2
●
Overcurrent
●
Overtemperature(a)
In case of overcurrent or overtemperature (TSD1) condition, the drivers switches off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
In case overvoltage/undervoltage condition, the drivers is switched off. The according status
bit is latched and can be read and optionally cleared by SPI. The drivers remain off until the
status is cleared. The driver can be excluded from undervoltage shutdown.
With the OUT UV shutdown enable bit (Control Register 2) the drivers can be excluded from
a switch off in case of Vs undervoltage. If the bit is set to ‘1’ the driver switches off, otherwise
the drivers remain on.
In case of open-load condition, the according status register is latched. The status can be
read and optionally cleared by SPI. The High sides is not switch off.
In case of a fail safe condition, the high side drivers are switched off. The control bits are set
to default values. (Except OUT1/FSO if it is used as a High-side Output)
Note:
The maximum voltage and current applied to the High Side Outputs is specified in chapter 4
‘Absolute Maximum Ratings’. Appropriate external protection may be required in order to
respect these limits under application conditions.
3.1.1
OUT1 reprogramming
To change the setting for OUT1 from FSO (default) to normal output configuration (ON/OFF
or Direct Drive) a SPI safety sequence is required. First write command with a specific
pattern to CONF Register needs to be provided in order to enable the write access for
configuration bits of OUT1. With an SPI write command to Control Register 1 the bits for
OUT1 can be modified.
The write command to Control Register 1 must follow the write command to the CONF
Register (no other SPI command in between these 2 commands)
Safety Sequence:
1.
Write to Conf Register (0x0011 1111; 1010 101x)
x: don’t care for unlocking sequence but according to description of watchdog timing
2.
Write to Ctrl Register 1 (0x0000 0001; xxxx xxxx)
x: values according to description of Ctrl Reg1
a. Except OUT1 when configured as FSO
Doc ID 18309 Rev 6
25/75
Protection and diagnosis
3.2
L99PM60J
Low side driver outputs REL1, REL2
The outputs REL1, REL2 (RDSon = 2 Ω typ. at 25 °C) are specially designed to drive relay
loads.
Typical relays used have the following characteristics:
Relay type 1: ON-state: R = 160 Ω typical +10%, L = 300 mH: Off-state: 240 mH
Relay type 2: ON-state: R = 220 Ω typical +10 %, L = 420 mH: Off-state: 330 mH
The outputs provide an active output Zener clamping (44 V typ) feature for the
demagnetisation of the relay coil, even though a load dump condition exists.
The low side drivers switch off in case of:
●
VS overvoltage and undervoltage (can be masked by SPI) Control Register 2, Bit0
●
Overcurrent
●
Overtemperature
In case of overload or overtemperature (TSD1) condition, the drivers switches off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
In case VS overvoltage and undervoltage condition, the drivers is switched off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
With the LS OVUV shutdown enable bit (Control Register 2) the drivers can be excluded
from a switch off in case of overvoltage and undervoltage. If the bit is set to ‘1’ the driver
switches off, otherwise the drivers remain on.
3.3
SPI diagnosis
Digital diagnosis features are provided by SPI (for details please refer to Section 7.2: SPI
registers)
26/75
●
V1 reset threshold programmable
●
Overtemperature including pre warning
●
Open-load separately for each OUT1,2
●
Overload status separately for each output stage
●
VS-supply overvoltage/undervoltage
●
V1-fail bit
●
V1 undervoltage
●
Chip Reset bit (start from power-on reset)
●
Number of unsuccessful V1 restarts after thermal shutdown
●
Number of sequential watchdog failures
●
LIN diagnosis (permanent recessive/dominant, dominant TxD)
●
Device state (wake-up from V1stby or Vbatstby)
●
Forced Vbatstby after WD-fail, forced Vbatstby after overtemperature
●
Watchdog timer state (diagnosis of watchdog)
●
Failsafe status
●
SPI communication error
Doc ID 18309 Rev 6
L99PM60J
4
Power supply fail
Power supply fail
Overvoltage and undervoltage detection on VS
4.1
VS overvoltage
If the supply voltage Vs reaches the overvoltage threshold (VSOV)
4.2
●
The outputs OUT1,2, REL1,2 and LIN are switched to high impedance state (load
protection).
●
The overvoltage bit is set and can be cleared with a ‘Read and Clear’ command.
●
Outputs REL1,2 can be excluded from a shutdown in case of overvoltage by SPI
VS undervoltage
If the supply voltage Vs drops below the undervoltage threshold voltage (VSUV)
●
The outputs OUT1,2, REL1,2, LIN are switched to high impedance state.
●
The undervoltage bit is set and can be cleared with the ‘Read and Clear’ command.
●
Outputs REL1,2 can be excluded from a shutdown in case of undervoltage by SPI
●
Output OUT1,2 can be excluded from a shutdown in case of undervoltage by SPI
Doc ID 18309 Rev 6
27/75
Power supply fail
4.3
L99PM60J
Temperature warning and thermal shutdown
Figure 11.
Thermal shutdown protection and diagnosis
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28/75
With the first transition into the TSD2 state failsafe mode is entered. The Thermal State
machine recovers the same state were it was before entering Standby Mode. In case of a
TSD2 it enters TSD1 state.
Doc ID 18309 Rev 6
L99PM60J
5
Typical application
Typical application
Figure 12. Typical application diagram
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Doc ID 18309 Rev 6
29/75
Electrical specifications
L99PM60J
6
Electrical specifications
6.1
Absolute maximum ratings
Table 7.
Absolute maximum rating
Symbol
Parameter / test condition
Value [DC voltage]
Unit
DC supply voltage / “jump start”
-0.3 to +28
V
Load dump
-0.3 to +40
V
-0.3 to +5.25
V
Logic input / output voltage range
-0.3 to V1 + 0.3
V
VCSN
Multi Level Input
-0.3 to Vs + 0.3
V
VREL1
VREL2,
Low-side output voltage range
-0.3 to +40
V
VOUT1..2,
High-side output voltage range
-0.3 to VS + 0.3
V
Current injection into VS related input pins
10
mA
Current injection into VS related outputs
10
mA
-20 to +40
V
VS
V1
Stabilized supply voltage, logic supply
VDI
VCLK
VTXD
VDO
VRXD
VNRESET
VDRV
IIn_put
Iout_inj
LIN bus I/O voltage range
VLIN
Note:
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit!
Loss of ground or ground shift with externally grounded loads: ESD structures are
configured for nominal currents only. If external loads are connected to different grounds,
the current load must be limited to this nominal current.
6.2
ESD protection
Table 8.
ESD protection
Parameter
Value
Unit
+/-2
kV
+/-4
kV
LIN
+/-8(2)
+/-10(3)
+/-7(4)
kV
All pins(5)
+/-500
V
All pins
(1)
All output pins
30/75
(2)
Doc ID 18309 Rev 6
L99PM60J
Electrical specifications
Table 8.
ESD protection (continued)
Parameter
Value
Unit
Corner pins
+/-750
V
pins(6)
+/-200
V
(5)
All
1. HBM (human body model, 100pF, 1.5 kΩ) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A
2. HBM with all none zapped pins grounded.
3. Indirect ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω) and ‘Hardware Requirements for LIN and
Flexray Interfaces in Automotive Applications’ (version 1.1, 2009-12-02)
4. Direct ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω) and ‘Hardware Requirements for LIN and
Flexray Interfaces in Automotive Applications’ (version 1.1, 2009-12-02); Cbus,LIN = 220 pF
5. Charged device model
6. Machine model: C = 200 pF; R = 0 Ω
6.3
Thermal data
Table 9.
Operating junction temperature
Symbol
Tj
RthjA
Table 10.
Parameter
TSD1 OFF
Thermal resistance junction / ambient
-40 to 150
°C
See Figure 26
°K/W
Temperature warning and thermal shutdown
Parameter
Min.
Typ.
Max.
Unit
Thermal overtemperature warning
threshold
Tj(1)
120
130
140
°C
Thermal shutdown junction
temperature 1
Tj(1)
130
140
150
°C
Tj(1)
150
160
170
°C
TSD2OFF
TSD2 ON
Unit
Operating junction temperature
Symbol
TW ON
Value
Thermal shutdown junction
temperature 2
Hysteresis
5
°C
TSD12hys
1. Non-overlapping
Doc ID 18309 Rev 6
31/75
Electrical specifications
L99PM60J
6.4
Electrical characteristics
6.4.1
Supply and supply monitoring
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18V; 4.8 V < V1 < 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 11.
Supply and supply monitoring
Symbol
Parameter
Test condition
VS absolute minimum value
VSAbsmin(1) for controlling V1 and NReset VS increasing / decreasing
outputs
VS
Supply voltage range
Min.
Typ.
Max.
Unit
—
2.5
—
V
6
13.5
18
V
5.81
V
0.15
V
22
V
1
1.5
V
6
12
mA
1
7
16
µA
10
48
70
µA
50
55
60
µA
VSUV
VS UV-threshold voltage
Vhyst_UV
Undervoltage hysteresis
VSOV
VS OV-threshold voltage
VS increasing / decreasing
18
Vhyst_OV
Overvoltage hysteresis
Hysteresis
0.5
IV(act)
Current consumption in
active mode
VS = 12 V; TxD LIN high;
V1 = 5 V;
HS/LS drivers OFF;
VLIN > (VS - 1.5 V)
IV(BAT)
Current consumption in VBAT- VS = 12 V; V1 = OFF;
VLIN > (VS - 1.5 V)
standby mode
IV(V1)
Current consumption in
V1-standby mode
IV(V1)CS
Current consumption in
V1-standby during direct drive
VS increasing / decreasing
5.11
0.04
VS = 12 V; V1 = 5 V;
HS/LS drivers OFF;
VLIN > (VS - 1.5 V);
Iv1 < ICMP_Fail
0.1
VS = 12 V; V1 = 5 V;
LS drivers OFF;
VLIN > (VS - 1.5 V);
Iv1 < ICMP_Fail
t on
45μA + ------------------- ⋅ 1750μA
t period
at ton = 200 µs;
tperiod = 50 ms
1. For VS > VSabsmin the V1 and NRESET output are actively driven.
VS < VSabsmin the V1 output is connected to ground by passive pull down resistor of 1MΩ.
6.4.2
Oscillator
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
32/75
Doc ID 18309 Rev 6
L99PM60J
Electrical specifications
Table 12.
Symbol
FCLK
6.4.3
Oscillator
Parameter
Test condition
Oscillation frequency
Min.
Typ.
Max.
Unit
0.808
1.0
1.35
MHz
Typ.
Max.
Unit
3.45
4.5
V
2.6
3.5
V
Power-on reset (VS)
All outputs open; Tj = -40 °C to 130 °C, unless otherwise specified.
Table 13.
Symbol
VPOR
VPOR
Power-on reset (VS)
Parameter
Test condition
VPOR threshold
Min.
(VS increasing)
VPOR threshold
(VS
decreasing)(1)
2.2
1. This threshold is valid if Vs had already reached 7V previously
6.4.4
Voltage regulator V1
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28 V; Tj = -40 °C to 130 °C, unless otherwise specified.
Table 14.
Symbol
Voltage regulator V1
Parameter
Test condition
V1
Output voltage
V1
Output voltage tolerance
Active mode
ILOAD = 6 mA... 50 mA,
VS = 13.5 V
Vhc1
Output voltage tolerance
active mode, high current
ILOAD = 50 mA... 100 mA,
VS = 13.5 V
VSTB1
Output voltage tolerance
V1-standby mode
ILOAD = 0uA...5mA
VS = 13.5V
VDP1
ICC1
tTSD
Typ.
Max.
5.0
-2
Unit
V
+/-2
%
+/-2.5
%
+4.5
%
ILOAD = 50 mA; VS = 4.5 V
0.2
0.4
V
ILOAD = 100 mA; V = 4.5 V
0.3
0.5
V
100
mA
950
mA
Drop-out voltage
Output current in active mode
ICCmax1 Short circuit output current
Cload1
Min.
Load capacitor1
Max. continuous load
current
Current limitation
400
Ceramic
0.22
V1 deactivation time after
thermal shutdown
600
µF
1
s
ICMP_rise
Current comp. rising
threshold
Rising current
2.1
4.6
6.8
mA
ICMP_fail
Current comp. falling
threshold
Falling current
1.5
3.6
6.0
mA
Doc ID 18309 Rev 6
33/75
Electrical specifications
Table 14.
Voltage regulator V1 (continued)
Symbol
ICMP_hys
L99PM60J
Parameter
V1 fail threshold
tV1fail
V1 fail Filter time
tV1FS
Min.
Typ.
Current comp. hysteresis
V1fail
tV1short
Test condition
Unit
0.5
mA
2
V
2
us
4
ms
2
ms
V1 forced
V1 short to ground detection
filter time
Max.
V1 short to ground
V1 Fail safe filter time
Note:
Nominal capacitor value required for stability of the regulator. Tested with 220nF ceramic
(+/- 20%). Capacitor must be located close to the regulator output pin.
6.4.5
Reset output (V1 supervision)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 4.0 V < VS = 28 V; Tj = -40 to 130 °C, unless otherwise specified.
Table 15.
Reset output (V1 supervision)
Symbol
Test condition
Min.
Typ.
Max.
Unit
VRT1
Reset threshold voltage1
VV1 decreasing
3.35
3.5
3.65
V
VRT1
Reset threshold voltage1
VV1 increasing
4.4
4.6
4.85
V
VRT2
Reset threshold voltage2
(default)
VV1 increasing /
decreasing
4.4
4.6
4.85
V
VRESET
Reset pin low output voltage
V1 > 1 V;
IRESET = 1 mA
0,2
0,4
V
RRESET
Reset pull up int. resistor
110
204
kΩ
40
µs
tRR
V1UVFT
tReset
6.4.6
Parameter
Reset reaction time
60
@ILOAD = 1 mA
6
V1 undervoltage filter time
16
µs
Reset delay time
2
ms
Watchdog
4.5 V < VS < 28 V; 4.8 V < V1 < 5.2 V; Tj = -40 to 130 °C, unless otherwise specified, see
Figure 13 and Figure 14)
Table 16.
Symbol
tLW
Parameter
Test condition
Long open window
Min.
Typ.
Max.
Unit
48.75
65
81.25
ms
4.5
ms
TEFW1
Early failure window 1
TLFW1
Late failure window 1
20
Safe window 1
7.5
TSW
34/75
Watchdog
Doc ID 18309 Rev 6
ms
10
12
ms
L99PM60J
Electrical specifications
Table 16.
Watchdog (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tWDR
Watchdog reset pulse time
1.5
2
2.5
ms
tV1Off
V1 deactivation duration after
8 consecutive WD failures
150
200
250
ms
Figure 13. Watchdog timing (missing watchdog trigger)
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Figure 14. Watchdog early, late and safe windows
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6.4.7
High-side outputs
Outputs (OUT1…2);
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless otherwise specified.
Doc ID 18309 Rev 6
35/75
Electrical specifications
Table 17.
L99PM60J
Output
Symbol
Parameter
RDSON
DC output resistance
IOUT
Min.
Typ.
Max.
Unit
ILOAD = 60 mA at
Tj = 25 °C
0
7
12
Ω
Short circuit shutdown current
8 V < VS < 16 V
140
235
330
mA
tSCF
Short circuit filter time
Tested by scan chain
IOLD
Open-load detection current 1
4.2
mA
tOLDT
Open-load filter time
SR
Test condition
64 * TOSC
0.5
Tested by scan chain
Slew rate
2
64 * TOSC
0.2
0.5
0.8
V/µs
tdONHS
Switch ON delay time
0.2 VS
5
35
60
µs
tdOFFHS
Switch OFF delay time
0.8 VS
20
95
150
µs
tSCF
Short circuit filter time
Tested by scan chain
IFW(1)
Loss of GND current (ESD
structure)
64 * TOSC
100
mA
1. Parameter guaranteed by design
6.4.8
Low-side drivers
Outputs (REL1…2);
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6 V ≤ VS ≤ 18 V; 4.8 V ≤ V1 ≤ 5.2 V; Tj = -40 to 130 °C, unless otherwise specified.
Table 18.
Relay drivers
Symbol
RDSON
IOUT
VZ
Parameter
Test condition
Min.
Typ.
Max.
Unit
0
2
3
Ω
DC output resistance
ILOAD = 100 mA @ Tj = 25 °C
Short circuit shut down current
8 V < VS < 16 V
250
375
500
mA
ILOAD = 100 mA
40
44
48
V
Output clamp
voltage(1)
tONHL
Turn on delay time to 10% VOUT
2.5
50
100
µs
tOFFLH
Turn off delay time to 90% VOUT
5
50
100
µs
4
V/µs
tSCF
Short circuit filter time
SR
Slew rate
64 *
TOSC
Tested by scan chain
0.2
2
1. The output is capable to switch off relay coils with the impedance of RL = 160 Ω; L = 300 mH (RL = 220 Ω; L = 420 mH); at
VS = 40 V (Load dump condition).
6.4.9
Direct drive / voltage supply monitoring
Input: DRV
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
36/75
Doc ID 18309 Rev 6
L99PM60J
Electrical specifications
6 V ≤ VS ≤ 18 V; 4.8 V ≤ V1 ≤ 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 19.
Input: DRV
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VDRVLOW Input voltage low level
Normal mode, V1 = 5 V
1.0
2.3
2.9
V
VDRVHIGH Input voltage high level
Normal mode, V1 = 5 V
1.5
2.8
3.8
V
Normal mode, V1 = 5 V
0.4
0.75
1.5
V
5
30
60
µA
25
35
pF
VDRVHYS
IDRVPD
Cin(1)
1.
VCSNHIGH –
VCSNLOW
Pull down current at input Normal mode, Vin = 1.5 V
Input capacitance
0 V < V1 < 5.2 V
Value of input capacity is not measured in production test. Parameter guaranteed by design.
Output: VSOUT
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V ≤ VS ≤ 18 V; 4.8 V ≤ V1 ≤ 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 20.
Symbol
Output: VSOUT
Parameter
Test condition
Typ.
Max.
Unit
0.195
VS
0.2 VS
0.205
VS
V
Output voltage
VS = 6 V; VS = 10 V;
VS = 18 V
VSOUTUV
VS output voltage in
case of undervoltage
VS = 4.5 V; VSM selected
0.0
V
VSOUTOV
VS output voltage in
case of overvoltage
VS = 24 V; VSM selected
5.0
V
VTROOM
TSENSE output voltage
at 25 °C
VS = 12 V; T = 25 °C
1.38
V
T = 25 °C; T= 130 °C;
T = -40 °C
3.5
mV/K
2
mA
VSOUT
VTSENSE TSENSE output voltage
IVSOUT
6.4.10
Min.
Pull-up pull-down
current ability
LIN
LIN 2.1 compliant for Baud rates up to 20 kBit/s (SAE J2602 compatible) baud rate of the
LIN bus can be upgraded up to 100 kBits by SPI bit configuration (LIN Flash bit 3 CR2).
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tjunction = -40 °C to 130 °C unless otherwise specified.
Doc ID 18309 Rev 6
37/75
Electrical specifications
Table 21.
Symbol
L99PM60J
LIN transmit data input: pin TXD
Parameter
Test condition
Min.
Typ.
0.8
1.9
Max. Unit
VTXDOW
Input voltage dominant level
Normal mode; V1 = 5 V
VTXDHIGH
Input voltage recessive level
Normal mode; V1 = 5 V
VTXDHYS
VTXDHIGH – VTXDOW
Normal mode; V1 = 5 V
ITXDPU
TXD pull up resistor
Normal mode; V1 = 5 V
20
kΩ
ITXDPD
TXD pull-down current
Test mode; VIN = 10 V
480
µA
Table 22.
Symbol
VRXDOW
VRXDHIGH
Table 23.
0.5
Parameter
Test condition
Min.
Output voltage dominant level Normal mode; V1 = 5 V; 2 mA
Output voltage recessive
level
VThdom
Receiver threshold voltage
recessive to dominant
state
VBusdom
Receiver dominant state
Normal mode; V1 = 5 V; 2 mA
1.0
1.5
V
Typ.
Max. Unit
0.5
4.5
Test condition
V
V
Min.
Typ.
Max.
Unit
0.4 VS
0.45 VS
0.5 VS
V
0.4 VS
V
0.6 VS
V
Receiver threshold voltage
dominant to recessive
state
0.5 VS
VBusrec
Receiver recessive state
0.6 VS
VThhys
Receiver threshold
hysteresis
VThrec – VThdom
VTHcnt
Receiver tolerance center
value
(VThrec + VThdom) / 2
VThwkup
Receiver walk-up
threshold voltage
VTHwkdwn
Receiver walk-up
threshold voltage
Transmitter input current
limit in dominant state
0.175
VS
V
0.475
VS
0.5 VS
0.525
VS
V
1.0
1.5
2
V
VS - 3.5 VS - 2.5 VS - 1.5
V
64 *
TOSC
µs
40
VTxD = VTxDhigh; VLIN = 0 V;
VBAT = 12 V(1)
-1
Doc ID 18309 Rev 6
V
0.1 VS
VTxD = VTxDlow;
VLIN = Vbatmax = 18 V
Transmitter input current in VTxD = VTxDhigh; 8 V < VLIN < 18 V;
8 V < VBAT < 18 V; VLIN > VBAT
recessive state
0.55 VS
0.07 VS
Dominant time for walk-up Sleep mode edge: recessivevia bus
dominant
Input leakage current at
Ibus_PAS_dom the receiver incl. pull-up
resistor
38/75
V
0.2
VThrec
Ibus_PAS_rec
3.5
LIN transmitter and receiver: pin LIN
Parameter
ILINDomSC
2.9
LIN receive data output: pin RXD
Symbol
tlinbus
V
100
180
mA
mA
20
µA
L99PM60J
Table 23.
Symbol
Electrical specifications
LIN transmitter and receiver: pin LIN (continued)
Max.
Unit
1
mA
Input current if loss of Vbat
GND = VS; 0 V < VLIN < 18 V
at device
100
µA
VLINdom
LIN voltage level in
dominant state
VTxD = VTxDlow; ILIN = 40 mA
1.2
V
VLINrec
LIN voltage level in
recessive state
VTxD = VTxDhigh; ILIN = 10 µA
RLINup
LIN output pull up resistor
VLIN = 0 V
Ibus_NO_GND
Ibus
Parameter
Input current if loss of
GND at device
Test condition
GND = VS; 0 V < VLIN < 18 V;
VBAT = 12 V
Min.
Typ.
-1
0.8 Vs
V
20
40
60
kΩ
Min.
Typ.
Max.
Unit
6
µs
2
µs
1. Slave Mode
Table 24.
Symbol
tRXpd
tRXpd_sym
D1
D2
D3
LIN transceiver timing
Parameter
Test condition
Receiver propagation
delay time
tRXpd = max(tRXpdr, tRXpdf);
tRXpdf = t(0.5 RXD) - t(0.45 VLIN);
tRXpdr = t(0.5 RXD) - t(0.55 VLIN);
CRXD = 20 pF; VS = 12 V;
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 kΩ, Cbus = 6.8 nF;
Rbus = 500 kΩ, Cbus = 10 nF
Symmetry of receiver
propagation delay time
(rising vs. falling edge)
tRXpd_sym = tRXpdr – tRXpdf
Duty cycle 1
THRec(max) = 0.744 * VS;
THDom(max) = 0.581 * VS;
VS = 7…18 V; tbit = 50 µs;
D1 = tbus_rec(min)/(2 x tbit)
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 kΩ, Cbus = 6.8 nF;
Rbus = 500 kΩ, Cbus = 10 nF
Duty Cycle 2
THRec(min) = 0.422 * VS;
THDom(min) = 0.284 * VS;
VS = 7.6 …18 V; tbit = 50 µs;
D1 = tbus_rec(max)/(2 x tbit)
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 kΩ, Cbus = 6.8 nF;
Rbus = 500 kΩ, Cbus = 10 nF
Duty Cycle 3
THRec(max) = 0.778 * VS;
THDom(max) = 0.616 * VS;
VS = 7…18 V; tbit = 96 µs;
D3 = tbus_rec(min)/(2 x tbit)
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 kΩ, Cbus = 6.8 nF;
Rbus = 500 kΩ, Cbus = 10 nF
Doc ID 18309 Rev 6
-2
0.396
0.581
0.417
39/75
Electrical specifications
Table 24.
L99PM60J
LIN transceiver timing (continued)
Symbol
Parameter
D4
Test condition
Min.
Typ.
Max.
THRec(min) = 0.389 * VS;
THDom(min) = 0.251 * VS;
VS = 7.6…18 V; tbit = 96 µs;
D1 = tbus_rec(max)/(2 x tbit)
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 kΩ, Cbus = 6.8 nF;
Rbus = 500 kΩ, Cbus = 10 nF
Duty Cycle 4
Unit
0.590
tdom(TXDL)
TXDL dominant time-out
12
ms
tLIN
LIN permanent recessive
time-out
40
µs
RDSon
Table 25.
ON resistance
16
Ω
LIN Flash mode
Symbol
SRf
10.5
Parameter
LIN slew rate falling edge
Test condition
Min.
Typ.
Max.
Unit
From 20% to 80% of VLIN; VS = 12 V;
Rbus = 150 Ω; Cbus = 1 nF
—
13
—
V/µs
Figure 15. LIN transmit, receive timing
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6.4.11
SPI
Input: CSN
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V ≤ VS ≤ 18 V; 4.8 V ≤ V1 ≤ 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
40/75
Doc ID 18309 Rev 6
L99PM60J
Electrical specifications
Table 26.
Input: CSN
Symbol
Min.
Typ.
Max.
Unit
Normal mode; V1 = 5 V
0.8
1.9
2.5
V
Normal mode; V1 = 5 V
1.5
2.9
3.5
V
VCSNHIGH – VCSNLOW Normal mode; V1 = 5 V
0.5
1.0
1.5
V
ICSNPU
CSN pull up resistor
Normal mode; V1 = 5 V
10
20
35
kΩ
ICSNPD
CSN pull-down current
Test mode, VIN = 10 V
VCSNLOW
Parameter
Input voltage low level
VCSNHIGH Input voltage high level
VCSNHYS
Test condition
480
µA
Input CSN for Flash mode
6 V ≤ VS ≤ 18 V, 4.5 V ≤ V1 ≤ 5.3 V; Tj = -40 °C to 130 °C; voltages are referred to GND, all
outputs open
Table 27.
Input CSN for Flash mode
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VflashL
Input level VCSN exit Flash
mode)
V1 = 5 V
6.1
7.25
8.4
V
VflashH
Input level VCSN entering
Flash mode
V1 = 5 V
7.4
8.4
9.4
V
VflashHYS
Input voltage hysteresis
V1 = 5 V
0.6
0.8
1.0
V
Inputs: CLK, DI
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 28.
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
160
300
us
tset
Switching from standby to
Delay time from standby to active mode. Time until output
active mode
drivers are enabled after CSN
going to high.
Vin L
Input low level
V1 = 5 V
1.0
2.3
2.9
V
Vin H
Input high level
V1 = 5 V
1.5
2.8
3.8
V
Vin Hyst
Input hysteresis
V1 = 5 V
0.4
0.75
1.5
V
Pull down current at input
VIN = 1.5 V
5
30
60
µA
10
15
pF
1
MHz
I in
1.
Inputs: CLK, DI
Cin(1)
Input capacitance at input
0 V < V1 < 5.2 V
CSN, CLK, DI and PWM1,2
fCLK
SPI input frequency at CLK
Value of input capacity is not measured in production test. Parameter guaranteed by design.
Doc ID 18309 Rev 6
41/75
Electrical specifications
L99PM60J
DI timing(b)
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 29.
DI timing
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
tCLK
Clock period
V1 = 5 V
1000
—
ns
tCLKH
Clock high time
V1 = 5 V
400
—
ns
tCLKL
Clock low time
V1 = 5 V
400
—
ns
tset CSN
CSN setup time, CSN low
before rising edge of CLK
V1 = 5 V
400
—
ns
tset CLK
CLK setup time, CLK high
before rising edge of CSN
V1 = 5 V
400
—
ns
tset DI
DI setup time
V1 = 5 V
200
—
ns
thold DI
DI hold time
V1 = 5 V
200
—
ns
tr in
Rise time of input signal DI,
CLK, CSN
V1 = 5 V
—
100
ns
tf in
Fall time of input signal DI,
CLK, CSN
V1 = 5 V
—
100
ns
Output DO
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 30.
Symbol
Output DO
Parameter
Test condition
Min.
VDOL
Output low level
V1 = 5 V; ID = -4 mA
VDOH
Output high level
V = 5 V; ID = 4 mA
4.5
IDOLK
3-state leakage current
VCSN = V1; 0 V < VDO < V1
-10
CDO(1)
3-state input capacitance
VCSN = V1,
0 V < V1 < 5.3 V
Typ.
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Doc ID 18309 Rev 6
Unit
0.5
V
V
10
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
b. See Figure 16: SPI – input timing.
Max.
10
µA
15
pF
L99PM60J
Electrical specifications
DO timing(c)
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 31.
DO timing
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tr DO
DO rise time
CL = 100 pF; ILOAD = -1 mA
—
50
100
ns
tf DO
DO fall time
CL = 100 pF; ILOAD = 1 mA
—
50
100
ns
ten DO tri L
DO enable time from
3-state to low level
CL = 100 pF; ILOAD = 1 mA;
pull-up load to V1
—
50
250
ns
tdis DO L tri
DO disable time from
low level to 3-state
CL = 100 pF; ILOAD = 4 mA;
pull-up load to V1
—
50
250
ns
ten DO tri H
DO enable time from
3-state to high level
CL = 100 pF; ILOAD = -1 mA;
pull-down load to GND
—
50
250
ns
tdis DO H tri
DO disable time from
high level to 3-state
CL = 100 pF; ILOAD = -4 mA;
pull-down load to GND
—
50
250
ns
DO delay time
VDO < 0.3 V1; VDO > 0.7 V1;
CL = 100 pF
—
50
250
ns
td DO
CSN timing(d)
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 32.
Symbol
tCSN_HI(min)
CSN timing
Parameter
Test condition
Minimum CSN HI
time, active mode
Transfer of SPI-command to
Input register
Min.
Typ.
6
—
Max. Unit
—
µs
RXDL/NINT timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
c. See Figure 17: SPI – output timing
d. See Figure 18: SPI transition parameters
Doc ID 18309 Rev 6
43/75
Electrical specifications
Table 33.
Symbol
tInterupt
L99PM60J
RXDL/NINT timing
Parameter
Test condition
Interrupt pulse duration
Walk-up from V1stby by LIN
Min.
Typ.
—
56
Figure 16. SPI – input timing
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Doc ID 18309 Rev 6
Max. Unit
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L99PM60J
Electrical specifications
Figure 17. SPI – output timing
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Electrical specifications
L99PM60J
Figure 18. SPI transition parameters
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Doc ID 18309 Rev 6
L99PM60J
ST SPI
7
ST SPI
7.1
SPI communication flow
7.1.1
General description
The proposed SPI communication is based on a standard SPI interface structure using CSN
(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock)
signal lines.
At device start-up the master reads the <SPI-frame-ID> register (ROM address 3EH) of the
slave device. This 8-bit register indicates the SPI frame length (16bit) and the availability of
additional features.
Each communication frame consists of an instruction byte which is followed by 1 data byte.
The data returned on SDO within the same frame always starts with the <Global Status>
register. It provides general status information about the device. It is followed by 1 data byte
(i.e. ‘In-frame-response’).
For write cycles the <Global Status> register is followed by the previous content of the
addressed register.
For read cycles the <Global Status> register is followed by the content of the addressed
register.
7.1.2
Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (<Write>, <Read>, <Read and Clear>, <Read Device
Information>) and a 6 bit address. If less than 6 address bits are required, the remaining bits
are unused but are reserved.
Table 34.
Command byte
MSB
LSB
Op code
OC1
Address
OC0
A5
A4
A3
A2
A1
A0
OCx: operating code
Ax: address
7.1.3
Operating code definition
Table 35.
Operating code definition
OC1
OC0
Meaning
0
0
<Write mode>
0
1
<Read mode>
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ST SPI
L99PM60J
Table 35.
Operating code definition (continued)
OC1
OC0
Meaning
1
0
<Read and clear status>
1
1
<Read device information>
The <Write Mode> <Read Mode> and <Read and Clear Status> operations allow access to
the RAM of the device, i.e. to write to control registers or read status information.
A <Read and Clear Status> operation addressed to a device specific status register reads
back and subsequently clear this status register.
A <Read and Clear Status> operation with address 3FH clears all status registers (including
the Global Status Register). Configuration Register is read by this operation.
<Read Device Information> allows access to the ROM area which contains device related
information such as the product family, product name, silicon version, register width and
availability of a watchdog.
More detailed descriptions of the device information are available in ‘Read Device
Information’.
7.1.4
Global status register(e)
Table 36.
Global status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Communication
error
Not (chip reset
or comm error)
TSD2 or TSD1
TW
V1 fail
VS fail
(OV/UV)
Fail safe
Fail safe
VS fail
(OV / UV)
V1 fail
TW
TSD1 or TSD2
Detailed global status register
NOT(chip reset
or comm error)
Comm error
Global error
Table 37.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex.
0
0
1
0
0
0
0
0
20
Default value in Normal mode - after
correct WD trigger or after Read &
Clear on Error Flags
1
0
0
0
0
0
0
0
80
Power ON - strong battery
1
0
0
0
0
0
1
0
82
Power ON - weak battery
1
1
0
0
0
0
0
0
C0
Communication error
e. See Section 7.2: SPI registers for details
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L99PM60J
Doc ID 18309 Rev 6
L99PM60J
ST SPI
Fail safe
VS fail
(OV / UV)
V1 fail
TW
TSD1 or TSD2
Detailed global status register (continued)
NOT(chip reset
or comm error)
Global error
Comm error
Table 37.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex.
L99PM60J
1
0
1
0
0
0
1
0
A2
VS overvoltage or VS undervoltage
1
0
1
0
0
0
0
1
A1
WD failure
1
0
1
0
0
0
0
1
A1
SPI error (DI stuck)
1
0
1
1
1
0
0
1
B9
TSD2
1
0
1
0
0
1
0
0
A4
V1 fail
1
0
1
0
0
0
0
0
A0
Other device failure(1)
1. The Global Error Flag is raised due to a failure condition which is not reported in the Global Status
Register. The Failure is reported in the Status Registers 1 – 4.
7.1.5
Configuration register
The <Configuration> register is accessible at RAM address 3FH.
The Configuration Register is implemented for compliance purpose to ST SPI Standard.
Table 38.
Configuration register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
WD trigger
<WD Trigger>: this Bit is reserved to serve the watchdog.
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ST SPI
L99PM60J
Figure 20. Read configuration register
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Figure 21. Write configuration register
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L99PM60J
ST SPI
7.1.6
Address mapping
Table 39.
Addressing mapping
RAM
Address
Description
Access
ROM
Address
3FH
Reserved
3EH
<SPI frame ID>
Includes frame width and availability of
watchdog
3FH
<Configuration>
R/W
14H
Status register 4
R
13H
Status register 3
R
12H
Status register 2
R
11H
Status register 1
R
02H
Control register 2
R/W
01H
Control register 1
R/W
00H
Reserved
…
Description
Access
N/A
R
Unused
N/A
03H
<product code 2>
Unique product identifier
N/A
02H
<product code 1>
Unique product identifier
R
01H
<silicon version>
Indicates Design Version
R
00H
<ID Header>
Device family, max address of device
information
R
R/W
The RAM memory area consists of 8 bit registers.
For the device information (ROM memory area) the eight bits of the memory cell are used.
All unused RAM and ROM addresses are read as ‘0’.
Note:
7.1.7
1
The register definition for RAM address 00H is unused. A register value of all 0 must cause
the device to enter a failsafe state (interpreted as ‘SDI stuck to GND’ failure).
2
ROM address 3FH is unused. An attempt to access this address must be recognized as a
communication error (‘SDI stuck to VCC’ failure) and must cause the device to enter a
failsafe state.
Write operation
The write operation starts with a Command Byte followed by 1 data byte.
Table 40.
Write command format
MSB
LSB
Command byte
Op Code
0
Address
0
A5
A4
A3
A2
A1
A0
D6
D5
D4
D3
D2
D1
D0
Data byte
D7
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ST SPI
L99PM60J
OC0, OC1: operating code (00 for ‘write’ mode)
A0 to A5: address bits
An attempt to write 00H at RAM address 00H is recognized as a failure (SDI stuck to GND).
The device enters a failsafe state.
7.1.8
Format of data shifted out at SDO during write cycle
Table 41.
Format of data shifted out at SDO during write cycle: global status
register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Comm
error
Not (chip reset
or comm error)
TSD2 or
TSD1
TW
V1 fail
VS fail
(OV/UV)
Fail
safe
Table 42.
Format of data shifted out at SDO during write cycle: data byte
MSB
Previous content of addressed register
D7
D6
D5
D4
D3
D2
LSB
D1
D0
Failures are indicated by activating the corresponding bit of the <Global Status> register.
The returned data byte represents the previous content of the accessed register.
Figure 22. Format of data shifted out at SDO during write cycle
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L99PM60J
7.1.9
ST SPI
Read operation
The Read operation starts with a Command Byte followed by 1 data byte.
The content of the data byte is ‘don’t care’. The content of the addressed register is shifted
out at SDO within the same frame (‘in-frame response’).
Table 43.
Read command format
MSB
LSB
Command byte
Op code
0
Address
1
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
Data byte
0
OC0, OC1: operating code (01 for ‘read’ mode)
A0 to A5: address bits
7.1.10
Format of data shifted out at SDO during read cycle
Table 44.
Format of data shifted out at SDO during read cycle: global status
register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Comm
error
Not (chip reset
or comm error)
TSD2 or
TSD1
TW
V1 fail
VS fail
(OV/UV)
Fail
safe
Table 45.
Format of data shifted out at SDO during read cycle: data byte
MSB
D7
Previous content of addressed register
D6
D5
D4
D3
D2
LSB
D1
D0
Failures are indicated by activating the corresponding bit of the <Global Status> register.
The returned data byte represents the content of the register to be read.
Doc ID 18309 Rev 6
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ST SPI
L99PM60J
Figure 23. Format of data shifted out at SDO during read cycle
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7.1.11
Read and clear status operation
The ‘Read and Clear Status’ operation starts with a command byte followed by 1 data byte.
The content of the data byte is ‘don’t care’. The content of the addressed Status Register is
transferred to SDO within the same frame (‘in-frame response’) and is subsequently
cleared.
A ‘Read and Clear Status’ operation with address 3FH clears all Status registers (incl. the
<Global Status> register). The Configuration Register is read by this operation.
Table 46.
Read and clear status’ command format‘
MSB
LSB
Command byte
Op code
1
Address
0
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
Data byte
0
OC0, OC1: operating code (10 for ‘read and clear status’ mode)
A0 to A5: address bits
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Doc ID 18309 Rev 6
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7.1.12
ST SPI
Format of data shifted out at SDO during ‘Read and Clear Status’
operation
Table 47.
Format of data shifted out at SDO during ‘Read and Clear Status’
operation: global status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Comm
error
Not (chip reset
or comm error)
TSD2 or
TSD1
TW
V1 fail
VS fail
(OV/UV)
Fail
safe
Table 48.
Format of data shifted out at SDO during read cycle: data byte
MSB
Previous content of addressed register
D7
D6
D5
D4
D3
LSB
D2
D1
D0
Failures are indicated by activating the corresponding bit of the <Global Status> register.
The returned data byte represents the content of the register to be read.
Figure 24. Format of data shifted out at SDO during ‘Read and Clear Status’ operation
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Doc ID 18309 Rev 6
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ST SPI
7.1.13
L99PM60J
Read device information
The device information is stored at the ROM addresses defined below and is read using the
respective operating code.
Table 49.
Read device information
Op code
Address
Device information
OC1
OC0
1
1
3FH
Reserved
1
1
3EH
<SPI frame ID>
Includes frame width and availability of watchdog = 41H
1
1
04H to 3DH
1
1
03H
<product code 2>
Unique product identifier; content = 4BH
1
1
02H
<product code 1>
Unique product identifier; content = 0CH
1
1
01H
<silicon version>
Indicates design version
1
1
00H
<ID Header>
Device family, max address of device information. Content: 43H
Unused
The <ID-Header> (00H) indicates the product family and specifies the highest address
which contains product information (the standard value, i.e. no additional product
information registers are present, is 03H  content of ID-Header is: XX00 0011)
Table 50.
ID-Header
Bit 7
Bit 6
Family identifier
Table 51.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Highest address containing device information
Family identifier
Bit 7
Bit 6
Meaning
0
0
VIPower
0
1
BCD
1
0
VIPower hybrid
1
1
Tbd
The <Product Code 1> (02H) and <Product Code 2> (03H) represents a unique code to
identify the product name. The code is specified in the device datasheet.
The <Silicon Version> (01H) provides information about the silicon version according to the
table below:
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L99PM60J
ST SPI
Table 52.
Bit 7
Silicon version
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Bit 1
Bit 0
Silicon version
Definition of the silicon version code:
Table 53.
Silicon version code
Bit3
Bit 2
Bit 1
Bit 0
Silicon version
0
0
0
0
First Silicon
0
0
0
1
V2
0
0
1
0
V3
0
0
1
1
V4
0
1
0
0
V5
0
1
0
1
V6
0
1
1
0
V7
0
1
1
1
V8
1
…
…
…
…
The <SPI-frame-ID> (ROM address 3EH) provides information about the register width (1,
2, 3 bytes) and the availability of ‘Burst Mode Read’ and watchdog.
Table 54.
SPI-frame-ID
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BR
WD
X
X
X
32-bit
24-bit
16-bit
x
x
BR: Burst-Mode Read (1 = Burst-Mode Read is supported)
WD: Watchdog (1 = available, 0 = not available)
32-bit, 24-bit, 16-bit: width of SPI frame (see table below)
7.2
SPI registers
Overview command byte
Table 55.
SPI register: command byte
Read/write
x
Address
x
x
x
Doc ID 18309 Rev 6
x
x
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ST SPI
L99PM60J
Table 56.
SPI register: mode selection
Read/write
Table 57.
Mode selection
0
0
Write
0
1
Read
1
0
Read and clear
1
1
Read device info
SPI register: CTRL register selection
CTRL register 1, 2
CTRL register selection
0
0
0
0
0
1
CTRL register1
0
0
0
0
1
0
CTRL register2
Table 58.
SPI register: STAT register selection
STAT register. 1…4
STAT register selection
0
1
0
0
0
1
STAT register1
0
1
0
0
1
0
STAT register2
0
1
0
0
1
1
STAT register3
0
1
0
1
0
0
STAT register4
Overview of control register data bytes
Table 59.
Overview of control register data byte
1st data byte
Control register 1
Defaults
1
1
1
1
0
0
0
0
Funct.
OUT2_2
OUT2_1
OUT1_2
OUT1_1
ICMP
Sandby
select
Go
standby
TRIG
Group
HS control
Mode control
Control register 2
Defaults
0
0
0
1
0
Funct.
REL2
REL1
VSM EN
Reset
level
LIN Flash
Group
58/75
LS control
1
1
LIN TXD OUT UV LS OVUV
timeout shutdown shutdown
enable
enable
enable
Other control
Doc ID 18309 Rev 6
1
L99PM60J
ST SPI
Control Register 1
Table 60.
Control register 1
1st data byte
Command byte
Read/ write
x
Table 61.
Address
x
0
0
Bit
0
0
1
Data, 8bit
Control register 1, 1st data byte
Group
Table 62.
0
HS control
Mode control
Defaults
1
1
1
1
0
0
0
0
Funct.
OUT2_2
OUT2_1
OUT1_2
OUT1_1
ICMP
Standby
select
Go
standby
TRIG
Control register 1, bits
Name
7
Comment
Select mode of OUT2
OUT2_2
OUT2_1
Active mode
V1-standby VBAT-standby
0
0
Off
0
1
On
VSM enable
1
0
OUT2
6
0
Direct drive
1
Off
Direct
drive
Off
Direct
drive
Off
VSM enable
1
Note:
1
0
Direct drive
1
Off
Note: In Direct Drive, Pin DRV/VSOUT, can be used as an input to directly
switch on/off OUT2
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ST SPI
Table 62.
Bit
L99PM60J
Control register 1, bits (continued)
Name
5
Comment
Select mode of OUT1
OUT2_2
OUT2_1
Active mode
V1-standby VBAT-standby
0
0
Off
0
1
On
VSM enable
1
1
Direct drive
1
Off
FSO
Direct
drive
Off
FSO
FSO
Note:
ICMP
V1 load current supervision
– 0: enabled; watchdog is disabled in V1-standby when the V1loadcurrent < ICMPthreshold
– 1: disabled; Watchdog is automatically disabled when V1-standby is entered
2
Stby Select
1
Go Stby
0
TRIG
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1
0
OUT1
4
3
0
In Direct Drive, Pin DRV/VSOUT, can be used as an input to directly switch
on/off OUT1
To change the setting for OUT1 from FSO (default) to normal output configuration
(ON/OFF or Direct Drive) a SPI safety sequence
Needs to be followed. First write command with a specific pattern to CONF Register needs
to be provided in order to enable the write access
For configuration bits of OUT1. With an SPI write command to Control Register 1 the bits
for OUT1 can be modified.
The Write command to Control Register 1 must follow the write command to the CONF
Register (no other SPI command in between these 2 commands)
Safety Sequence:
– Write to Conf Register
(0x0011 1111; 1010 101x)
x: don’t care for unlocking sequence but according to description of watchdog timing
– Write to Ctrl Register 1 (0x0000 0001; xxxx xxxx)
x: values according to description of Ctrl Reg1
Select standby mode
– 0: VBAT-standby mode
– 1: V1-standby mode
Execute standby mode
– 0: no action
– 1: execute standby mode
Trigger bit for watchdog
Doc ID 18309 Rev 6
L99PM60J
ST SPI
Control Register 2
Table 63.
Control register 2
1st data byte
Command byte
Read/ write
x
Table 64.
Group
Table 65.
Bit
Address
x
0
0
0
0
1
0
Data, 8bit
Control register 2, 1st data byte
LS control
Other control
Defaults
0
0
0
1
0
1
Function
REL2
REL1
VSM
enable
Reset
level
LIN
Flash
1
1
LIN TXD OUT UV LS OVUV
timeout shutdown shutdown
enable
enable
enable
Control register 2, bits
Name
Comment
Select mode of REL2
REL2
7
Active mode
V1 standby
VBAT standby
REL2
0
1
REL2 off
REL2 on
REL2 off
Select mode of REL1
REL2
6
REL1
Active mode
V1 standby
0
1
VBAT standby
REL1 off
REL1 on
REL1 off
Select Pin DRV/VSOUT as input/output
VSM
enable
Active mode
DRV/VSOUT pin used as input (direct drive)(1)
0
OUT2_2 OUT2_1
5
VSM enable
1
VBAT
V1
standby standby
DRV/VSOUT used as
0
0
Output (VS/5 voltage)
0
1
Output (VS/5 voltage)
1
0
1
1
Output (TSENSE
voltage)
DRV/VSOUT pin
used as input
(direct drive)(1)
Output (VS/5 voltage)
1. Usage of Direct Drive feature is not only related to the configuration of DRV/VSOUT as
an input. Refer to truth table of OUT1/2 for the direct drive feature.
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ST SPI
Table 65.
Bit
L99PM60J
Control register 2, bits
Name
Comment
Select V1 reset level
– 0: 3.5 V
– 1: 4.6 V
4
Reset level
3
LIN Flash
Select maximum LIN communication speed
– 0: 20 kbit/s
– 1: 100 kbit/s
2
LIN TXD
timeout
enable
Enable / disable monitoring of TxD
– 0: no TxD monitoring
– 1: TxD monitoring; LIN transmitter is switched off if TXDL is dominant for t > 12 ms
1
OUT UV
shutdown
enable
Select undervoltage shutdown for HS driver
– 0: no undervoltage shutdown
– 1: undervoltage shutdown
0
LS OVUV
shutdown
enable
Shutdown of LS drivers in case of overvoltage / undervoltage
0: no shutdown of low sides in case of overvoltage / undervoltage
1: shutdown low sides in case of overvoltage / undervoltage
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Doc ID 18309 Rev 6
L99PM60J
ST SPI
7.2.1
Status register
Table 66.
Overview of status register data bytes
1st data byte
Status register 1
Funct.
OV
UV
OL OUT2
OL OUT1
Group
OC OUT2
OC OUT1
OC REL2
OC REL1
LIN Wake
Device
State
Device
State
Forced
sleep
TSD/ShtV1
WD timer
state1
WD timer
state0
TSD2
TSD1
TW
Diagnosis 1
Status register 2
Funct.
Res
LIN perm
dom
LIN TXD
dom
LIN perm
rec
Group
Res
Diagnosis 2
Status register 3
Funct.
WD Fail
WD Fail
WD Fail
Forced
sleep WD
WD Fail
Group
Diagnosis 3
Status register 4
Funct.
V1 UV
warn
V1 restart
V1 restart
V1 restart
Group
Table 67.
V1 fail
Diagnosis 4
Global status register
Bit 7
Bit 6
Bit 5
Global error
flag
Communicatio
n error(1)
Bit 4
NOT (chip reset or
comm. error i.e. cold TSD2 or TSD1(3)
start(2)
Bit 3
Bit 2
Bit 1
Bit 0
TW
V1 fail
Vs Fail
(OV/UV)
Fail safe(4)
1. Invalid CLOCK COUNT
2. Cleared with CLR command on SR3
3. Cleared with “READ and CLEAR” on SR4
4. Cleared with a valid WD trigger (WD fail) or by clearing the corresponding status register related to failure
Status Register 1
Table 68.
Status register 1, command and data byte
1st data byte
Command byte
Read/write
x
x
Address
0
1
0
0
Doc ID 18309 Rev 6
0
1
Data, 8bit
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ST SPI
L99PM60J
Table 69.
Status register 1, data byte
1st data byte
Function
OV
UV
OL OUT2 OL OUT1 OC OUT2 OC OUT1 OC REL2 OC REL1
Group
Diagnosis 1
Table 70.
Status register 1, bits
Bit
Name
7
OV
Overvoltage event occurred since last read out
Bit is latched until a “Read and clear” access
6
UV
Undervoltage event occurred since last read out
Bit is latched until a “Read and clear” access
5
Comment
4
OL OUT2 Open-load event occurred since last read out
OL OUT1 Bit is latched until a “read and clear” access
3
OC OUT2
2
1
OC OUT1 Overcurrent event occurred since last read out
OC REL2 Bit is latched until a “read and clear” access
0
OC REL1
Status Register 2
Table 71.
Status register 2, command and data byte
1st data byte
Command byte
Read/write
x
x
Table 72.
Address
0
1
0
0
1
0
Data, 8bit
Status register 2, data byte
1st data byte
Function
Res
LIN perm
dom
LIN TXD
dom
Group
Res
LIN wake
Device
state
Device
state
Diagnosis 2
Table 73.
64/75
LIN perm
rec
Status register 2, bits
Bit
Name
Comment
7
Res
6
LIN perm
dom
LIN bus is dominant for t > 12 ms
Bit is latched until a “Read and clear” access
5
LIN TXD
dom
TxDL pin is dominant for t > 12 ms; Transmitter is disabled; Bit is latched until a
“Read and clear” access
Reserved
Doc ID 18309 Rev 6
L99PM60J
ST SPI
Table 73.
Status register 2, bits (continued)
Bit
Name
4
LIN perm
rec
3
Res
2
LIN wake
1
Device
state
0
Comment
LIN bus does not follow TxDL within 40 µs; Transmitter is disabled; Bit is
latched until a “Read and clear” access
Reserved
Wake up from LIN; Bit is latched until a “Read and clear” access
State from which the device woke up
Device
state
Device
state
0
0
Active
0
1
V1-standby
1
0
VBAT-standby
Device
State
State from which the device woke up
Bit is latched until a “read and clear access”.
After a “read and clear access”, the device state is updated.
After a wake up, device state is
– 01: V1-standby
– 10: VBAT-standby
Status Register 3
Table 74.
Status register 3, command and data byte
1st data byte
Command byte
Read/write
x
Table 75.
x
Address
0
1
0
0
1
1
Data, 8bit
Status register 3, data byte
1st data byte
Function
WD
fail_3
WD
fail_2
WD
fail_1
Group
Table 76.
WD
fail_0
Forced
sleep WD
Forced
WD timer WD timer
sleep
State_1
State_0
TSD/ShtV1
Diagnosis 3
Status register 3, bits
Bit
Name
7
WD fail_3
6
WD fail_2
5
WD fail_1
4
WD fail_0
Comment
Number of missing watchdog triggers (15 missing Watchdog trigger forces the
device into VBAT-standby).
Bits are not clearable; are cleared with a proper Watchdog trigger
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ST SPI
L99PM60J
Table 76.
Status register 3, bits (continued)
Bit
Name
3
Forced
sleep WD
2
Comment
Device was forced to VBAT mode because of multiple watchdog errors
Bits are latched until a read and clear access
Device was forced to VBAT or multiple thermal shutdown events or a short on
Forced
V1 during start-up.
sleep
TSD/ShtV1 Bits are latched until a read and clear access
WD timer
state_1
1
Status of watchdog counter of selected watchdog timing
WD_timer_state_1
WD_timer_state_0
0
0
0% - 33%
0
1
33% - 66%
1
1
66% - 100%
WD timer
state_0
0
Counter
Bits are not clearable
Status Register 4
Table 77.
Status register 4, command and data byte
1st data byte
Command byte
Read/write
x
x
Table 78.
Address
0
1
0
1
0
0
Data, 8bit
Status register 4, data byte
1st data byte
Function
V1 UV
warn
V1
V1
V1
restart_2 restart_1 restart_0
Group
Name
7
V1 UV warn
6
V1 restart_2
3
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TSD1
TW
Status register 4, bits
Bit
4
TSD2
Diagnosis 4
Table 79.
5
V1 fail
Comment
V1 undervoltage pre-warning (V1 < 4.5 V)
Bit is latched until a read and clear access
Number of TSD2 events which caused a restart of V1 regulator (7 TSD2
V1 restart_1 events forces the device into VBAT-standby)
Bits are latched until a read and clear access
V1 restart_0
V1 fail
V1 fail (V1 < 2 V for t > 2 µs) event occurred since last read out
Bit is latched until a “read and clear access”
Doc ID 18309 Rev 6
L99PM60J
ST SPI
Table 79.
Status register 4, bits (continued)
Bit
Name
2
TSD2
1
TSD1
0
TW
Comment
Thermal warning / shutdown1 / shutdown2 occurred since last readout
Bits are latched until a “read and clear access”
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Package and PCB thermal data
L99PM60J
8
Package and PCB thermal data
8.1
PowerSSO-16 thermal data
Figure 25. Thermal data of PowerSSO-16
$*9
Note:
Board finish thickness 1.6 mm +/- 10%; Board double layer; Board dimension 77 x 86;
Board Material FR4; Cu thickness 0.070 mm (front and back side); Thermal vias separation
1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm;
Footprint dimension 2.5 mm x 4.2 mm
Figure 26. Rthj-amb vs PCB copper area in open box free air condition
57+MBDPEYV&XKHDWVLQNDUHD
57+MDPE
57+MBDPEƒ&:
3&%&XKHDWVLQNDUHDFPA
$*9
68/75
Doc ID 18309 Rev 6
L99PM60J
Package and PCB thermal data
Figure 27. V1 thermal impedance
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=foot print
10
1
0.0001
0.001
0.01
0.1
Time (s)
1
10
100
1000
AG00064V1
Figure 28. Thermal fitting model of V1
$*9
Equation 1: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THp ( 1 – δ )
where
δ = tp ⁄ T
Doc ID 18309 Rev 6
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Package and PCB thermal data
Table 80.
70/75
L99PM60J
PowerSSO-16 thermal parameter
Area/island (cm2)
FP
R1 (°C/W)
1.5
R2 (°C/W)
3
R3 (°C/W)
5
R4 (°C/W)
2
8
20
6
6
R5 (°C/W)
28
21
10
R6 (°C/W)
32
25
21
C1 (W·s/°C)
0.0008
C2 (W·s/°C)
0.01
C3 (W·s/°C)
0.05
C4 (W·s/°C)
0.2
0.3
0.3
C5 (W·s/°C)
0.5
1
1.5
C6 (W·s/°C)
4
6
8
Doc ID 18309 Rev 6
L99PM60J
Package and Packaging Information
9
Package and Packaging Information
9.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:
www.st.com.ECOPACK® is an ST trademark.
9.2
PowerSSO-16 package information
Figure 29. PowerSSO-16 package dimensions
AG00110V1
Doc ID 18309 Rev 6
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Package and Packaging Information
Table 81.
L99PM60J
PowerSSO-16 mechanical data
Millimeters
Symbol
Min.
Max.
A
1.25
1.72
A1
0.00
0.10
A2
1.10
1.62
B
0.18
0.36
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
0.50
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
k
0°
8°
X
1.90
2.50
Y
3.60
4.20
ddd
72/75
Typ.
0.10
Doc ID 18309 Rev 6
L99PM60J
9.3
Package and Packaging Information
PowerSSO-16 packing information
Figure 30. PowerSSO-16 tube shipment (no suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
B
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
AG00111V1
Figure 31. PowerSSO-16 tape and reel shipment (no suffix)
REEL DIMENSION
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
AG00112V1
Doc ID 18309 Rev 6
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Revision history
10
L99PM60J
Revision history
Table 82.
Document revision history
Date
Revision
26-Jan-2011
1
Initial release.
2
Updated Section 3.2: Low side driver outputs REL1, REL2
Updated Figure 8: Recovery after forced VBAT due to multiple
watchdog failure
Table 11: Supply and supply monitoring:
– IV(BAT) (V1-standby): updated test condition and minimum, typical
and maximum values
– IV(V1): updated typical value
Table 13: Power-on reset (VS)
– VPOR (VS decreasing): updated minimun and typical values
Table 14: Voltage regulator V1
– VSTB1: updated minimum and maximum values
– ICMP_rise, ICMP_fail: updated minimum, typical and maximum values
Table 15: Reset output (V1 supervision)
– VRT2 (increasing/ decreasing): updated minimux, typical and
maximum values
Table 17: Output
– IOLD: updated minimux, typical and maximum values
Table 18: Relay drivers
– VZ: added typical value
Table 20: Output: VSOUT:
– VSOUT: added minimum and maximum values
Table 26: Input: CSN:
– ICSNPU: added minimum aln maximum values
Table 39: Addressing mapping
– Updated RAM address: inserted Control Register 1
25-Mar-2011
3
Updated following tables:
– Table 13: Power-on reset (VS):
VPOR decreasing: updated minimum value
– Table 14: Voltage regulator V1:
ICMP_rise: updated minimum value
ICMP_fail: updated minimum and maximum values
– Table 15: Reset output (V1 supervision):
VRT1: added row
VRT2: updated test condition and maximum value
28-Apr-2011
4
Changed document state from preliminary data to final datasheet
03-Nov-2011
5
Updated Figure 8: Recovery after forced VBAT due to multiple
watchdog failure
Table 11: Supply and supply monitoring:
– IV(act), IV(BAT), IV(V1): updated test conditions
– IV(V1)CS: added row
19-Sep-2013
6
Updated disclaimer.
09-Mar-2011
74/75
Changes
Doc ID 18309 Rev 6
L99PM60J
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