STMICROELECTRONICS L99DZ70XP

L99DZ70XP
Door actuator driver
Features
■
One full bridge for 6 A load (Ron = 150 mΩ)
■
Two half bridges for 3 A load (Ron = 300 mΩ)
■
Two half bridges for 0.75 A load
(Ron = 1600 mΩ)
■
One highside driver for 6 A load (Ron = 90 mΩ)
■
Two configurable highside drivers for up to
1.5 A load (Ron = 500 mΩ) or 0.4 A
(Ron = 1800 mΩ)
■
Two highside drivers for 0.5 A load
(Ron = 1600 mΩ)
Applications
■
■
Programmable softstart function to drive loads
with higher inrush currents as current limitation
value
■
Very low current consumption in standby mode
(IS < 6 µA typ; Tj ≤ 85 °C; ICC < 5 µA typ;
Tj ≤ 85 °C)
■
Current monitor output for all highside drivers
■
Device contains temperature warning and
protection
■
Openload detection for all outputs
■
Over-current protection for all otputs
■
Separated half bridges for door lock motor
■
PWM control of all outputs
■
Charge pump output for reverse polarity
protection
■
STM standard serial peripheral interface (STSPI 3.0)
■
Control block for electrochromic element
Table 1.
PowerSSO-36
Door actuator driver with 6 bridges for double
door lock control, mirror fold and mirror axis
control, highside driver for mirror defroster,
bulbs and LEDs (replacement for L9950).
Control block with external MOS transistor for
charging / discharging of electrochromic glass.
Description
The L99DZ70XP is a microcontroller driven
multifunctional door actuator driver for automotive
applications. Up to five DC motors and five
grounded resistive loads can be driven with six
half bridges and five highside drivers. An
electrochromic mirror glass can be controlled
using the integrated SPI-driven module in
conjunction with an external MOS transistor. The
integrated SPI controls all operating modes
(forward, reverse, brake and high impedance).
Also all diagnostic information is available via SPI
read.
Device summary
Order codes
Package
PowerSSO-36
November 2010
Tube
Tape and reel
L99DZ70XP
L99DZ70XPTR
Doc ID 15162 Rev 3
1/47
www.st.com
1
Contents
L99DZ70XP
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1
2.5
3
4
SPI - Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1
Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2
Wake up and active mode / standby mode . . . . . . . . . . . . . . . . . . . . . . . 24
3.3
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4
Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5
Overvoltage and undervoltage detection at VS . . . . . . . . . . . . . . . . . . . . 25
3.6
Overvoltage and undervoltage detection at VCC . . . . . . . . . . . . . . . . . . . 25
3.7
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25
3.8
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9
Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10
Over-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12
PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14
Programmable soft-start function to drive loads with higher inrush current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15
Controller for electrochromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1
2/47
Outputs OUT1 - OUT11, ECV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.1
Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.2
Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 15162 Rev 3
L99DZ70XP
Contents
4.2
4.1.3
Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.4
Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.5
SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.1
5
Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1
Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2
Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3
Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4
Control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5
Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.6
Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.7
Status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.8
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8
7.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2
PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3
PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Doc ID 15162 Rev 3
3/47
List of tables
L99DZ70XP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
4/47
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current monitor output CM / PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Charge pump output CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
On-resistance and switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrochrome control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SDI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Control register 0 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Control register 1 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Control register 2 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Control register 3 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status register 0 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Status register 1 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Status register 2 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Doc ID 15162 Rev 3
L99DZ70XP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrochrome control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI - Transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI - Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI - driver turn on/off timing, minimum CSN HI time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Example of programmable soft-start function for inductive loads . . . . . . . . . . . . . . . . . . . . 27
Write and read SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Global error flag definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 15162 Rev 3
5/47
Block diagram and pin description
1
L99DZ70XP
Block diagram and pin description
Figure 1.
Block diagram
VBAT
STD18NF03L
100k
10k
VS
L99PM62GXP
CP
100µF
300mΩ
100nF
1600mΩ
Charge
Pump
1600mΩ
VCC
VCC
150mΩ
1k
1k
1k
SPI
Interface
DI
DO
CLK
CSN
1k
PWM1
1k
Standby
SPC560D
Driver Interface & Diagnostic
ST SPI
M
OUT1
M
OUT2
M
OUT3
150mΩ
OUT4
OUT5
300mΩ
OUT6
M
M
500 / 1800mΩ
10 Watt
OUT7
500 / 1800mΩ
90mΩ
10 Watt
OUT8
progr. Bulb or LED Mode
OUT11
OUT9
1600mΩ
OUT10
1600mΩ
STD18NF03L
ECDR (VS)
EC Glass
Control Block
CM/PWM2
1k
CM
MUX
All components to be
placed together as close
as possible
6BIT SPI controlled
5 nF
1600mΩ
100 nF
ECV (VS)
GND
Table 2.
Pin
Symbol
Function
1, 18, 19, 36
GND
Ground: reference potential.
Important: For the capability of driving the full current at the outputs all pins
of GND must be externally connected!
2, 35
6/47
Pin definition and functions
Highside driver output 11.
The output is built by a highside switch and is intended for resistive loads,
therefore the internal reverse diode from GND to the output is missing. For
ESD reason a diode to GND is present, but the energy which can be
OUT11 dissipated is limited. The highside driver is a power DMOS transistor with an
internal parasitic reverse diode from the output to VS (bulk-drain-diode). The
output is over-current protected.
Important: for the capability of driving the full current at the outputs both pins
of OUT11 must be externally connected!
Doc ID 15162 Rev 3
L99DZ70XP
Block diagram and pin description
Table 2.
Pin
3
4
5
6, 7, 14, 15,
23, 24, 28,
29
8
9
10
Pin definition and functions (continued)
Symbol
Function
OUT1,
OUT2,
OUT3
Halfbridge outputs 1,2,3.
The output is built by a highside and a lowside switch, which are internally
connected. The output stage of both switches is a power DMOS transistor.
Each driver has an internal parasitic reverse diode (bulk-drain-diode:
highside driver from output to VS, lowside driver from GND to output). This
output is over-current protected.
VS
Power supply voltage (external reverse protection required).
For this input a ceramic capacitor as close as possible to GND is
recommended.
Important: For the capability of driving the full current at the outputs all pins
of VS must be externally connected!
DI
Serial data input.
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is a 24 bit control word and the most significant bit
(MSB, bit 23) is transferred first.
CM/
PWM2
Current monitor output/PWM2 input.
Depending on the selected multiplexer bits of the control register this output
sources an image of the instant current through the corresponding highside
driver with a ratio of 1/10.000 or 1/2000. This pin is bidirectional. The
microcontroller can overdrive the current monitor signal to provide a second
PWM input for the outputs OUT5, OUT8 and OUT10.
CSN
Chip Select Not input / Testmode.
This input is low active and requires CMOS logic levels. The serial data
transfer between L99DZ70 and the microcontroller is enabled by pulling the
input CSN to low level.
Serial data output.
The diagnosis data is available via the SPI and this tristate-output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high)
11
DO
12
VCC
Supply voltage.
For this input a ceramic capacitor as close as possible to GND is
recommended.
13
CLK
Serial clock input.
This input controls the internal shift register of the SPI and requires CMOS
logic levels.
16,17
20,21
22
OUT4,
OUT5,
OUT6
Halfbridge outputs 4,5,6: see OUT1 (pin 3).
Important: For the capability of driving the full current at the outputs both
pins of OUT4 (OUT5, respectively) must be externally connected!
25
ECDR
Electrocromic driver output.
If the electrochrome mode is selected this pin is used to control the gate of
an external MOSFET, otherwise it remains in high-impedance state.
Note: It is possible to connect the pin to VS as in L9950/53/54 applications,
as long as the electrochome mode is not enabled via SPI.
26
CP
Charge pump output.
This output is provided to drive the gate of an external n-channel power
MOS used for reverse polarity protection (see Figure 1.).
Doc ID 15162 Rev 3
7/47
Block diagram and pin description
Table 2.
Pin definition and functions (continued)
Pin
Symbol
Function
27
PWM1
PWM1 input.
This input signal can be used to control the drivers OUT1-4, OUT6-7, OUT9
and OUT11 and ECV by an external PWM signal.
30
31
OUT7,
OUT8,
Highside driver outputs 7,8: see OUT9.
By selection of one of the 2 power DMOS at same output is it possible to
supply a bulb with low on-resistance or a LED with higher on-resistance in a
different application.
ECV
Electrochrome voltage input and lowside driver output.
This input senses voltage in electrocrome mode for charge monitoring.
The lowside switch provides a fast discharge of electrocromic mirror and can
be used 'stand alone' as lowside switch beside electrocromic mode.
33
OUT9
Highside driver output 9.
The output is built by a highside switch and is intended for resistive loads,
hence the internal reverse diode from GND to the output is missing. For
ESD reason a diode to GND is present but the energy which can be
dissipated is limited. The highside driver is a power DMOS transistor with an
internal parasitic reverse diode from the output to VS (bulk-drain-diode). The
output is over-current and open load protected.
34
Highside driver output 10: see OUT9.
OUT10 Important: beside the bit10 in control register 1 this output can be switched
on setting bit1 for electrocromic control mode with higher priority.
32
8/47
L99DZ70XP
Doc ID 15162 Rev 3
L99DZ70XP
Block diagram and pin description
Figure 2.
Configuration diagram (top view)
GND 1
OUT11 2
OUT1 3
OUT2 4
OUT3 5
Vs 6
Vs 7
DI 8
PowerSSO-36
CM / PWM2 9
CSN 10
DO 11
Vcc 12
CLK 13
Vs 14
Vs 15
OUT4 16
OUT4 17
GND 18
Note:
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
OUT11
OUT10
OUT9
ECV
OUT8
OUT7
Vs
Vs
PWM1
CP
ECDR
Vs
Vs
OUT6
OUT5
OUT5
GND
All pins with the same name must be externally connected.
Doc ID 15162 Rev 3
9/47
Electrical specifications
L99DZ70XP
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
-0.3...28
V
40
V
-0.3 to 5.5
V
Digital input / output voltage
-0.3 to VCC + 0.3
V
VCM
Current monitor output
-0.3 to VCC + 0.3
V
VCP
Charge pump output
-25 .. VS + 11
V
-0.3 to VS + 0.3
V
DC supply voltage
Vs
Single pulse tmax < 400 ms
Vcc
Stabilized supply voltage, logic supply
VDI, VDO, VCLK,
VCSN, VPWM
VOUTn, ECDR, ECV
IOUT,2,3,9,10,
Static output voltage (n= 1 to 11)
Output current
±1.25
A
IOUT1,6,7,8,
Output current
±5
A
IOUT4,5,11
Output current
±10
A
ECV
2.2
ESD protection
Table 4.
ESD protection
Parameter
All pins
Output pins: OUT1 - OUT6, ECV
Unit
± 2 (1)
kV
(2)
kV
±4
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
2. HBM with all unzapped pins grounded.
10/47
Value
Doc ID 15162 Rev 3
L99DZ70XP
2.3
Electrical specifications
Thermal data
Table 5.
Operating junction temperature
Symbol
Tj
Table 6.
Parameter
Operating junction temperature
Value
Unit
-40 to 150
°C
Temperature warning and thermal shutdown
Symbol
Parameter
Min.
TjTW ON
Temperature warning threshold junction
temperature
TjSD ON
Thermal shutdown threshold junction
temperature
Tj
increasing
TjSD OFF
Thermal shutdown threshold junction
temperature
Tj
decreasing
Tj
130
Max.
Unit
150
°C
170
°C
150
TjSD HYS Thermal shutdown hysteresis
2.4
Typ.
°C
5
°K
Electrical characteristics
VS = 8 to 16V, VCC= 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 7.
Supply
Item
Symbol
Parameter
7.1
VS
Operating voltage range
VS DC supply current
7.2
IS
7.3
7.4(1)
VS quiescent supply
current
Test condition
Min.
Typ. Max. Unit
7
28
V
mA
VS = 16 V, VCC = 5.3 V
active mode
OUT1 - OUT11, ECV,
ECDR floating
7
20
VS = 16 V, VCC = 0 V
standby mode
OUT1 - OUT11, ECV,
ECDR floating
Ttest = -40°C, 25°C
4
12
Ttest = 85°C
6
Doc ID 15162 Rev 3
µA
25
11/47
Electrical specifications
Table 7.
Item
L99DZ70XP
Supply (continued)
Symbol
7.5
Parameter
Test condition
VCC DC supply current
ICC
7.6(2)
VCC quiescent supply
current
7.7(1)
Min.
Typ. Max. Unit
VS = 16 V, VCC = 5.3 V
CSN = VCC, active mode
OUT1 - OUT11, ECV,
ECDR floating
1
3
VS = 16 V,
VCC = 5.3 VCSN = VCC
standby mode
OUT1 - OUT11, ECV,
ECDR floating
Ttest = -40°C, 25°C
3
6
Ttest = 85°C
5
10
Typ.
Max.
Unit
mA
µA
1. This parameter is guaranteed by design.
2. CM/ PWM 2 = VCC or 0 V.
Table 8.
Overvoltage and under voltage detection
Item
Symbol
8.1
VSUV on
8.2
Test condition
Min.
VS UV-threshold voltage
VS increasing
5.6
7.2
V
VSUV off
VS UV-threshold voltage
VS decreasing
5.2
6.1
V
8.3
VSUV hyst
VS UV-hysteresis
8.4
VSOV off
VS OV-threshold voltage
VS increasing
18
24.5
V
8.5
VSOV on
VS OV-threshold voltage
VS decreasing
17.5
23.5
V
8.6
VSOV hyst
VS OV-hysteresis
8.7
VPOR off
Power-on-reset threshold
VCC increasing
8.8
VPOR on
Power-on-reset threshold
VCC decreasing
8.9
VPOR hyst
Power-on-reset hysteresis VPOR OFF - VPOR ON
Table 9.
VCM
Parameter
ICM,r
Functional voltage
range
and 7,8
(low on-resistance)
ICM / IOUT2,3,9,10
9.3
V
1
V
2.9
2.0
V
V
0.11
Min.
Typ.
0
0V <= VCM <= 4V
1 ----------------10.000
VCC=5V
1 -----------,
2000
and 7,8
(high on-resistance)
12/47
0.5
VSOV OFF - VSOV ON
Test condition
Current monitor
output ratio:
ICM / IOUT1,4,5,6,11
9.2
VSUV ON - VSUV OFF
V
Current monitor output CM / PWM 2
Item Symbol
9.1
Parameter
Doc ID 15162 Rev 3
Max
Unit
VCC-1V
V
L99DZ70XP
Electrical specifications
Table 9.
Current monitor output CM / PWM 2 (continued)
Item Symbol
Parameter
Test condition
Current monitor
accuracy
accICMOUT1,4,5,6,
9.4
11and 7, 8
ICM acc
(low on-res.)
accICMOUT2,3,9,10,
9.5
VCM <=
3.8V,
VCC = 5V
and 7, 8
(high on-res.)
Min.
IOut,min= 500mA
IOut4,5,11max= 5.9A
IOut1,6 max= 2.9A
IOut7,8 max= 1.3A
Typ.
Max
Unit
4% +
8% +
1%FS(1) 2%FS(1)
IOut,min= 100 mA
IOut2,3 max= 0.6 A
IOut9,10max= 0.4 A
IOut8 max= 0.3 A
1. FS (full scale)= IOUTmax * ICM,r .
Table 10.
Item
Charge pump output CP
Symbol
Parameter
Max
Unit
VCP
Charge pump output
voltage
VS+6
VS+13
V
VS+8
VS+13
V
VS >=12V, ICP = -100µA VS+10
VS+13
V
300
µA
Typ.
Max.
Unit
VS = 13.5 V,
Tj = 25 °C,
IOUT1,6 = ± 1.5 A
300
400
mΩ
11.2
VS = 13.5 V,
Tj = 125 °C,
IOUT1,6 = ± 1.5 A
450
600
mΩ
11.3
VS = 13.5 V,
Tj = 25 °C,
IOUT2,3 = ± 0.4A
1600
2200
mΩ
VS = 13.5 V,
Tj = 125 °C,
IOUT2,3 = ± 0.4 A
2500
3400
mΩ
10.1
10.2
10.3
10.4
2.4.1
ICP
Charge pump output
current
Test condition
Min.
VS = 8V, ICP = -60µA
VS = 10V, ICP = -80µA
VCP = VS+10V,
VS =13.5V
95
Typ.
150
Outputs OUT1 - OUT11, ECV
Table 11.
Item
On-resistance and switching times
Symbol
Parameter
11.1
rON OUT1,
rON OUT6
rON OUT2,
rON OUT3
11.4
On-resistance to
supply or GND
On-resistance to
supply or GND
Test condition
Doc ID 15162 Rev 3
Min.
13/47
Electrical specifications
Table 11.
Item
L99DZ70XP
On-resistance and switching times (continued)
Symbol
Parameter
Typ.
Max.
Unit
VS = 13.5 V,
Tj = 25 °C,
IOUT4,5 = ± 3.0 A
150
200
mΩ
11.6
VS = 13.5 V,
Tj = 125 °C,
IOUT4,5 = ± 3.0 A
225
300
mΩ
11.7
VS = 13.5 V,
Tj = 25 °C,
IOUT9,10 = -0.4 A
1600
2200
mΩ
11.8
VS = 13.5 V,
Tj = 125 °C,
IOUT9,10 = -0.4 A
2500
3400
mΩ
11.9
VS = 13.5 V,
Tj = 25 °C,
IOUT11 = -3.0 A
90
130
mΩ
11.10
VS = 13.5 V,
Tj = 125 °C,
IOUT11 = -3.0 A
130
180
mΩ
11.11
VS = 13.5 V,
Tj = 25 °C,
IOUT7,8 = - 0.8 A
500
700
mΩ
VS = 13.5 V,
Tj = 125 °C,
IOUT7,8 = - 0.8 A
700
950
mΩ
VS = 13.5 V,
Tj = 25 °C,
IOUT7,8 = - 0.2 A
1800
2400
mΩ
VS = 13.5 V,
Tj = 125 °C,
IOUT7,8 = - 0.2 A
2500
3400
mΩ
VS = 13.5 V,
Tj = 25 °C,
IOUTECV = + 0.4 A
1600
2200
mΩ
VS = 13.5 V,
Tj = 125 °C,
IOUTECV = + 0.4 A
2500
3400
mΩ
11.5
rON OUT4,
rON OUT5
rON OUT9,
rON OUT10
rON OUT11
On-resistance to
supply or GND
On-resistance
to supply
On-resistance
to supply
On-resistance to
supply in low mode
(control register 1
bits 12 to15: 0101)
11.12
rON OUT7
rON OUT8
11.13
On-resistance to
supply in high mode
(control register 1
bits 12 to15: 1010)
11.14
11.15
rON ECV
On-resistance to
GND
11.16
11.17
IQLH
11.18
14/47
Switched-off output
current highside
drivers of OUT1-6,
8-11
Test condition
Min.
VOUT= 0V,
standby mode
-5
-2
µA
VOUT= 0V,
active mode
-10
-7
µA
Doc ID 15162 Rev 3
L99DZ70XP
Electrical specifications
Table 11.
Item
On-resistance and switching times (continued)
Symbol
Parameter
IQLH7,8
Switched-off output
current highside
drivers of OUT7-8
11.19
11.20
11.21
Switched-off output
current lowside
drivers of OUT1-6
11.22
IQLL
11.23
Switched-off output
current lowside
drivers of ECV
11.24
11.25
Output delay time,
highside driver on
(OUTX except
OUT7,8)
11.26
Output delay time,
highside driver on
(OUT7,8 in high
RDSon mode)
Test condition
Min.
Typ.
VOUT= 0V,
standby mode
-5
-2
µA
VOUT= 0V,
active mode
-15
-10
µA
VOUT= VS,
standby mode
80
Max.
120
Unit
µA
VOUT= 0V,
active mode
-10
VOUT= VS,
standby mode
-15
15
µA
VOUT= VS,
active mode
-10
10
µA
-7
µA
20
40
80
µs
15
35
60
µs
11.27
Output delay time,
highside driver on
(OUT7,8 in low
RDSon mode)
10
35
80
µs
11.28
Output delay time,
highside driver off
(OUT1, 4, 5, 6, 11)
60
150
200
µs
40
70
100
µs
15
30
70
µs
40
150
300
µs
15
45
80
µs
td ON H
td OFF H
11.29
Output delay time,
highside driver off
(OUT2,3,7, high/low
RDSon , 8 high/low
RDSon , 9, 10)
11.30
td ON L
Output delay time,
lowside driver On
11.31
td OFF L 1-6
Output delay time,
lowside driver OUT
1-6 off
td OFF L ECV
Output delay time,
lowside driver ECV
off
11.32
VS = 13.5 V,
VCC = 5 V (1)(2)(3)
VS = 13.5 V,
VCC = 5 V(1)(2)(3)
VS = 13.5 V,
VCC = 5 V,
corresponding
highside driver is not
active(1)(2)(3)
VS=13.5V,
VCC=5V(1)(2)(3)
Doc ID 15162 Rev 3
15/47
Electrical specifications
Table 11.
L99DZ70XP
On-resistance and switching times (continued)
Item
Symbol
11.33
tD HL
11.34
Parameter
Cross current
protection time
tD LH
11.35
dVOUT/dton/off Slew rate of OUTx
Test condition
tcc ONLS_OFFHS td OFFH(4)
Min.
Typ.
Max.
Unit
50
200
400
µs
0.1
0.2
0.6
V/µs
Min.
Typ.
Max.
Unit
3
5
A
0.75
1.25
A
6
10
A
0.5
1.0
A
6
10
A
tcc ONHS_OFFLS td OFFL(4)
VS = 13.5V,
VCC = 5 V(1)(2)(3))
1. Rload = 16Ω at OUT1, 6 and 7,8 in low on-resistance mode.
2. Rload = 4Ω at OUT4, 5 and 11.
3. Rload = 64Ω at OUT2, 3, 9, 10, ECV and 7, 8 in high On-resistance mode.
4. tcc is the switch-on delay time if complement in half bridge has to switch-off.
Table 12.
Current monitoring
Item
Symbol
12.1
|IOC1|,
|IOC6|
12.2
|IOC2|,
|IOC3|
12.3
|IOC4|,
|IOC5|
12.4
|IOC9|,
|IOC10|
12.5
|IOC11|
12.6
|IOC7|,
|IOC8|
12.7
16/47
Parameter
Over-current threshold
to supply or GND
Over-current threshold
to supply
Test condition
VS = 13.5V,
VCC = 5V,
sink and source
VS = 13.5V,
VCC = 5 V, source
Over-current threshold
to supply in low
on-resistance mode
VS = 13.5V, VCC = 5V,
source, control register
1 bits 12 to 15: 0101
1.5
2.5
A
Over-current threshold
to supply in high
on-resistance mode
VS = 13.5V, VCC = 5V,
source, control register
1 bits 12 to 15: 1010
0.35
0.65
A
1.25
A
100
µs
12.8
|IOCECV|
Output current
limitation to GND
VS = 13.5V,
VCC = 5 V, source
0.75
12.9
tFOC
Filter time of
over-current signal
Duration of over-current
condition to set the
status bit
10
12.10
frec0
Recovery frequency for OC
recovery duty cycle bit= 0
1
4
kHz
12.11
frec1
Recovery frequency for OC
recovery duty cycle bit= 1
2
6
kHz
Doc ID 15162 Rev 3
55
L99DZ70XP
Electrical specifications
Table 12.
Current monitoring (continued)
Item
Symbol
12.12
IIOLD1I,
IIOLD6I
12.13
IIOLD2I,
IIOLD3I
12.14
IIOLD4I,
IIOLD5I
12.15
IIOLD9I,
IIOLD10I
12.16
IIOLD11 I
Parameter
Under-current threshold
to supply or GND
Under-current threshold
to supply in low
on-resistance mode
IIOLD7I,
IIOLD8I
Item
13.1
13.2
13.3
13.4
13.5
Typ.
Max.
Unit
10
30
80
mA
10
20
30
mA
60
150
300
mA
5
10
15
mA
30
150
300
mA
15
40
60
mA
5
10
15
mA
20
30
mA
3
ms
VS = 13.5V,
VCC = 5V, sink
10
Filter time of under-current
Duration of undercurrent condition to set
the status bit
0.5
Electrochrome control
Symbol
Parameter
VCTRLmax
Maximum EC-control
voltage
DNL
Differential non linearity
IdVECVI
Voltage deviation
between target and
ECV
dVECVnr
13.6
dVECVhi
13.7
VECDRmin_high
13.8
Min.
Under-current
threshold to GND
12.19 IIOLDECVI
Table 13.
VS = 13.5 V,
VCC = 5 V, source
Under-current threshold
to supply in high
on-resistance mode
12.18
tFOL
VS = 13.5V,
VCC = 5V,
sink and source
Under-current
threshold to supply
12.17
12.20
Test condition
Difference
voltage
between target
and ECV sets
flag if VECV is:
Test condition
Min. Typ. Max.
Unit
bit 0= 1 control reg. 2(1)
1.4
1.6
V
2(1)
1.12
1.28
V
-1
1
LSB(2)
+5%
+1
LSB
(3)
mV
bit 0= 0 control reg.
-5%
dVECV =Vtarget(3)-VECV -1
LSB
IIECDRI < 1µA
(3)
Below
it
dVECV =
Vtarget - VECV
Above
it
Output voltage range
VECDRmax_low
Doc ID 15162 Rev 3
Toggle
bit 1=1
status
reg. 2
120
mV
Toggle
bit 0= 1
status
reg. 3
-120
mV
IECDR = -10 µA
4.5
5.5
V
IECDR = 10 µA
0
0.7
V
17/47
Electrical specifications
Table 13.
Item
L99DZ70XP
Electrochrome control (continued)
Symbol
Parameter
Test condition
13.9
IECDR
Current into ECDR
13.10
Min. Typ. Max.
Unit
Vtarget >VECV + 500mV,
VECDR = 3.5V
-100
-10
µA
Vtarget < VECV - 500mV,
VECDR = 1.0V;
Vtarget=1 LSB;
VECV=0.5V
10
100
µA
13.11
Recdrdis
Pulldown resistance at
ECDR in fast
discharge mode
VECDR = 0.7V ;
Cntrl Reg 1: bit 8 and bit
1 = 1, all other bits = 0
5
kΩ
13.12
IQECDR
Quiescent current
VECDR = VS;
Cntrl. reg 1 bit 1 = 0
1
µA
1. Bit 7 to 2 = ‘1’ control register 1: ECV voltage, where IIECDR can change sign.
2. 1 LSB (Least Significant Bit)= 23.8 mV.
3.
Vtarget is set by bit 7 to 2 of control register 1 and bit 0 of control register 2; tested for each individual bit.
Figure 3.
Electrochrome control block diagram
Ω
D
A
C
Ω
2.5
SPI - Electrical characteristics
VS = 8 to 16V, VCC = 4.5 to 5.5V, Tj = - 40 to 150°C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin.
18/47
Doc ID 15162 Rev 3
L99DZ70XP
Electrical specifications
Table 14.
Item
Delay time from standby to active mode
Symbol
14.1
Table 15.
tset
Parameter
Test condition
Delay time
Switching from standby to active
mode. Time until output drivers are
enabled after CSN going to high and
set bit 0=1 of control register 0.
Min.
Typ.
Max.
Unit
256
300
µs
Typ.
Max.
Unit
0.3*
Vcc
V
Inputs: CSN, CLK, PWM1/2 and DI
Item
Symbol
15.1
VinL
Input low level
VCC = 5V
15.2
VinH
Input high level
VCC = 5V
0.7*
Vcc
V
15.3
Vin Hyst
Input hysteresis
VCC = 5V
500
mV
15.4
RCSN in
CSN pull up resistor
VCC = 5V
0V<VCSN<0.7VCC
30
120
250
kΩ
15.5
RCLK in
CLK pull down resistor
VCC = 5V
VCLK = 1.5V
30
60
150
kΩ
15.6
RDI in
VCC = 5V
VDI = 1.5V
30
60
150
kΩ
VCC = 5V
VPWM1= 1.5V
30
60
150
kΩ
10
pF
Max.
Unit
15.7
15.8
Parameter
Test condition
DI pull down resistor
RPWM1 in PWM1 pull down resistor
Cin(1)
Input capacitance at input
CSN, CLK, DI and PWM1/2
Min.
0 V < VCC < 5.3V
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16.
SDI timing (1)
Item
Symbol
Parameter
Test condition
16.1
tCLK
Clock period
VCC = 5V
16.2
tCLKH
Clock high time
VCC = 5V
115
ns
16.3
tCLKL
Clock low time
VCC = 5V
115
ns
16.4
tset CSN
CSN setup time, CSN low
before rising edge of CLK
VCC = 5V
400
ns
16.5
tset CLK
CLK setup time, CLK high
before rising edge of CSN
VCC = 5V
400
ns
16.6
tset DI
DI setup time
VCC = 5V
200
ns
16.7
thold DI
DI hold time
VCC = 5V
200
ns
Doc ID 15162 Rev 3
Min.
Typ.
1000
ns
19/47
Electrical specifications
Table 16.
L99DZ70XP
SDI timing (continued)(1)
Item
Symbol
Parameter
Test condition
16.8
tr in
Rise time of input signal DI,
CLK, CSN
16.9
tf in
Fall time of input signal DI,
CLK, CSN
Min.
Typ.
Max.
Unit
VCC = 5V
100
ns
VCC = 5V
100
ns
1. DI timing parameters tested in production by a passed / failed test:
Tj= -40°C / +25°C:
SPI communication @ 2MHz.
Tj= +125°C
SPI communication @ 1.25 MHz.
Table 17.
DO
Item
Symbol
Parameter
Test condition
17.1
VDOL
Output low level
IDO = -5 mA
17.2
VDOH
Output high level
IDO = 5 mA
17.3
IDOLK
Tristate leakage
current
VCSN = VCC,
0V < VDO < VCC
17.4
CDO (1)
Tristate input
capacitance
VCSN = VCC,
0V < VCC < 5.3V
Min.
Typ.
Max.
Unit
0.2VCC
V
0.8 VCC
V
-10
10
µA
10
pF
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 18.
Item
Symbol
18.1
tr DO
DO rise time
18.2
tf DO
DO fall time
Parameter
Test condition
Min. Typ. Max.
Unit
CDO = 100 pF
80
140
ns
CDO = 100 pF
50
100
ns
18.3
DO enable time
ten DO tri L from tristate to low
level
CDO = 100 pF, Iload = 1mA
pull-up load to VCC
100
250
ns
18.4
DO disable time
tdis DO L tri from low level to
tristate
CDO = 100 pF, Iload = 4 mA
pull-up load to VCC
380
450
ns
18.5
DO enable time
ten DO tri H from tristate to high
level
CDO =100 pF, Iload = -1mA
pull-down load to GND
100
250
ns
18.6
DO disable time
tdis DO H tri from high level to
tristate
CDO = 100 pF, Iload = -4mA
pull-down load to GND
380
450
ns
VDO < 0.3 VCC,
VDO > 0.7 VCC,
CDO = 100 pF
50
250
ns
18.7
20/47
DO timing
td DO
DO delay time
Doc ID 15162 Rev 3
L99DZ70XP
Electrical specifications
Table 19.
Item
CSN timing
Symbol
19.1
Parameter
Test condition
Min.
Typ. Max.
Unit
Mimimum CSN HI time,
tCSN_HI,stb switching from standby
mode
Transfer of SPI-command
to input register
20
50
µs
Minimum CSN HI time,
active mode
Transfer of SPI-command
to input register
2
4
µs
19.2 tCSN_HI,min
Figure 4.
SPI - Transfer timing diagram
CSN high to low: DO enabled
CSN
time
CLK
0
1
2
3
4
5
6
7
X
18 19
X
0
20 21 22 23
time
DI: data will be accepted on the rising edge of CLK signal
DI
0
1
2
4
3
5
6
7
X
X
18 19
0
20 21 22 23
DO: data will change on the falling edge of CLK signal
DO
0
1
2
3
4
5
6
7
X
18 19
20 21 22
23
Input
Data
Register
old data
1
time
0
1
time
CSN low to high: actual data is
transfered to output power switches
fault bit
Figure 5.
X
1
new data
time
SPI - Input timing
0.8 VCC
CSN
0.2 VCC
t
t
set CSN
t
CLKH
se t CLK
0.8 VCC
CLK
0.2 VCC
t
set DI
t
hold DI
t
CLKL
0.8 VCC
DI
Valid
Valid
0.2 VCC
Doc ID 15162 Rev 3
21/47
Electrical specifications
Figure 6.
L99DZ70XP
SPI - DO valid data delay time and valid time
t f in
t r in
0.8 VCC
0.5 VCC
0.2 VCC
CLK
t r DO
DO
(low to high)
0.8 VCC
0.2 VCC
t d DO
t f DO
0.8 VCC
DO
(high to low)
Figure 7.
0.2 VCC
SPI - DO enable and disable time
tf in
tr in
0.8 VCC
50%
0.2 VCC
CSN
DO
pull-up load to VCC
CL = 100 pF
50%
ten DO tri L
t dis DO L tri
50%
DO
pull-down load to GND
CL = 100 pF
ten DO tri H
22/47
Doc ID 15162 Rev 3
t dis DO H tri
L99DZ70XP
Electrical specifications
Figure 8.
SPI - driver turn on/off timing, minimum CSN HI time
CSN low to high: data from shift register
is transferred to output power switches
t
t r in
tCSN_HI,min
f in
80%
50%
20%
CSN
tdOFF
current
output voltage
output
of aa driver
driver
of
OFF state
ON state
t
t
80%
50%
20%
OFF
dON
t
output voltage
current
output
ofaa driver
driver
of
ON
OFF state
Doc ID 15162 Rev 3
80%
ON state
50%
20%
23/47
Application information
L99DZ70XP
3
Application information
3.1
Dual power supply: VS and VCC
The power supply voltage VS supplies the half bridges and the highside drivers. An internal
charge-pump is used to drive the highside switches. The logic supply voltage VCC is used
for the logic part and the SPI of the device.
Due to the independent logic supply voltage the control and status information will not be
lost, if there are temporary spikes or glitches on the power supply voltage.
3.2
Wake up and active mode / standby mode
After power up of VS and Vcc the device operates in standby-mode. Pulling the signal CSN
to low level wakes the device up and the analog part will be activated (active mode).
After at least 10µs, the first SPI communication is valid and bit 0 of the Control Register 0
can be used to set the EN-mode. If bit 0 is not set to 1, the device doesn't remain in the
active mode. After at least 256µs all latched data will be cleared and the inputs and outputs
are switched to high impedance. In standby mode the current at VS (VCC) is less than 6 µA
(5 µA) for CSN = high (DO in tristate).
3.3
Charge pump
In standby mode the chargepump is turned off. After enabling the device by SPI command
(bit0=1 Control Register 0) the oscillator starts and the voltage begins to increase. The
output drivers are enabled after at least 256 µs after CSN went to high.
3.4
Diagnostic functions
All diagnostic functions (over/under-current, power supply over-/undervoltage, temperature
warning and thermal shutdown) are internally filtered. The condition has to be valid for at
least 32 µs (open load: 1ms) before the corresponding status bit in the status registers is
set.
The filters are used to improve the noise immunity of the device. The under-current and
temperature warning functions are intended for information purpose and will not change the
state of the output drivers. On contrary, the over-current condition disables the
corresponding driver and thermal shutdown disables all drivers. Without setting the overcurrent recovery bits in the input data register, the microcontroller has to clear the overcurrent status bits to reactivate the corresponding drivers.
24/47
Doc ID 15162 Rev 3
L99DZ70XP
3.5
Application information
Overvoltage and undervoltage detection at VS
If the power supply voltage VS rises above the overvoltage threshold VSOV OFF (typical
21 V), the outputs OUT1 to OUT11, ECDR and ECV are switched to high impedance state
to protect the load. When the voltage VS drops below the undervoltage threshold VSUV OFF
(UV-switch-OFF voltage), the output stages are switched to high impedance to avoid the
operation of the power devices without sufficient gate driving voltage (increased power
dissipation). If the supply voltage VS recovers (control register 3: bit 4=0) to normal
operating voltage then the outputs stages return to the programmed state. If the
undervoltage/overvoltage recovery disable bit is set (control register 3: bit 4=1), the
automatic turn-on of the drivers is deactivated.
The microcontroller needs to clear the status bits to reactivate the drivers. It is
recommended to set bit1 control register 3 to avoid a possible high current oscillation in
case of a shorted output to GND and low battery voltage.
3.6
Overvoltage and undervoltage detection at VCC
In case of power-on (VCC increases from undervoltage to VPOR OFF = 2.9 V) the circuit is
initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases
below the minimum threshold (VPOR ON = 2.0 V), the outputs are switched to tristate (high
impedance) and the status registers are cleared.
3.7
Temperature warning and thermal shutdown
If the junction temperature rises above Tj TW, a temperature warning flag is set after at least
32 µs and it can be read via the SPI. If the junction temperature increases above the second
threshold Tj SD, the thermal shutdown bit is set and the power DMOS transistors of all output
stages are switched off to protect the device after at least 32 µs.
The temperature warning and thermal shutdown flags are latched and the bits must be
cleared by the microcontroller. This is possible only if the temperature has decreased below
trigger temperature. If the thermal shutdown bit has been cleared the output stages are
reactivated.
3.8
Inductive loads
Each half bridge is built by internally connected highside and lowside power DMOS
transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can
be driven at the outputs OUT1 to OUT6 without external free-wheeling diodes. The highside
drivers OUT7 to OUT11 are intended to drive resistive loads. Therefore only a limited energy
(E<1mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For
inductive loads (L>100µH) an external free-wheeling diode connected between GND and
the corresponding output is required.
The low side driver at ECV does not have a freewheel diode built into the device.
Doc ID 15162 Rev 3
25/47
Application information
3.9
L99DZ70XP
Open load detection
The open load detection monitors the load current in each activated output stage. If the load
current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding
open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without
changing the mechanical/electrical state of the loads.
3.10
Over-load detection
In case of an over-current condition a flag is set in the status register in the same way as
during open load detection. If the over-current signal is valid for at least tISC(typ) = 55 µs, the
over-current flag is set and the corresponding driver is switched off to reduce the power
dissipation and to protect the integrated circuit. If the over-current recovery bit of the output
is zero, the microcontroller has to clear the status bits to reactivate the corresponding driver.
3.11
Current monitor
The current monitor output sources a current image at the current monitor output which has
two fixed ratios of the instantaneous current of the selected highside driver. Outputs with a
resistance of 500 mΩ and higher have a ratio of 1/2000 and those with a lower resistance of
1/10000. The signal at output CM is blanked after switching on the driver until correct
settlement of the circuitry (at least for 64 µs). The bits 0 to 3 of the control register 3 define
which of the outputs are multiplexed to the current monitor output CM/PWM2. The current
monitor output allows a more precise analysis of the actual state of the load rather than the
detection of an open- or overload condition. For example it can be used to detect the motor
state (starting, free-running, stalled). Moreover, it is possible to control the power of the
defroster more precisely by measuring the load current. The current monitor output is
bidirectional (PWM inputs).
3.12
PWM inputs
Each driver has a corresponding PWM enable bit, which can be programmed by the SPI
interface. If the PWM enable bit is set in control registers 2 or 3, the output is controlled by
the logically AND-combination of the PWM signal and the output control bit in Control
Registers 0 and 1. The outputs OUT1-4, 6, 7, 9, OUT11 are controlled by the PWM1 input
and the outputs OUT5, 8 and OUT10 are controlled by the bidirectional input CM/PMW2.
For example, the two PWM inputs can be used to dim two lamps independently by external
PWM signals. In case of switching off a high/low side switch in PWM mode a minimum off
time of appr. (256 µs – tdon+ tdoff) is predefined by the state machine, to avoid switching on
the high/low side again during the negative slope. For a PWM frequency of 100Hz this
means the maximum duty cycle is about 98%. Larger duty cycles can be realized by
applying pulse skipping.
26/47
Doc ID 15162 Rev 3
L99DZ70XP
3.13
Application information
Cross-current protection
The six half-brides of the device are cross-current protected by an internal delay time. If one
driver (LS or HS) is turned off, the activation of the other driver of the same half bridge will
be automatically delayed by the cross-current protection time. After the cross-current
protection time is expired the slew-rate limited switch-off phase of the driver is changed to a
fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this
behaviour it is always guaranteed that the previously activated driver is completely turned off
before the opposite driver starts to conduct.
3.14
Programmable soft-start function to drive loads with higher
inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable softstart function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device automatically switches
the outputs on again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition. The PWM frequency settles at 1.7kHz
and 3kHz. The device itself cannot distinguish between a real overload and a non linear load
like a light bulb. A real overload condition can only be qualified by time. For over-load
detection the microcontroller can switch on the light bulbs by setting the over-current
recovery bit for the first e.g. 50ms. After clearing the recovery bit the output will be
automatically switched off, if the overload condition remains. This over-load detection
procedure has to be followed in order make it possible to switch on the low-side driver of a
bridge output, if the associated high-side driver has been used in recovery mode before.
Figure 9.
Example of programmable soft-start function for inductive loads
Doc ID 15162 Rev 3
27/47
Application information
3.15
L99DZ70XP
Controller for electrochromic glass
The voltage of an electrochromic element connected at pin ECV can be controlled to a
target value, which is set by the bits 7 down to 2 of control register 1. Setting bit 1 of control
register 1 enables this function. An on-chip differential amplifier and an external MOS
source follower, with its gate connected to pin ECDR and which drives the electrochrome
mirror voltage at pin ECV, form the control loop. The drain of the external MOS transistor is
supplied by OUT10. A diode from pin ECV (anode) to pin ECDR (cathode) has been placed
on the chip to protect the external MOS source follower. A capacitor of at least 5 nF has to
be added to pin ECDR for loop-stability.
The target voltage is binary coded with a full scale range of 1.5V. If Bit 0 of control register 2
is set to '1', the maximum controller output voltage is clamped to 1.2V without changing the
resolution of bits 7-2 of control register 1. When setting the target voltage to 0V and
programming the ECVLS driver to on-state, the voltage at pin ECV is pulled to ground by a
1.6 Ohm low-side switch (fast discharge).
The status of the voltage control loop is reported via SPI. Bit 0 in the status register 2 is set,
if the voltage at pin ECV is higher, whereas Bit 1 in the same status register is set, if the
voltage at pin ECV is lower than the target value. Both status bits are valid, if they are stable
for at least 150 µs.
Since OUT10 is the output of a high-side driver, it contains the same diagnose functions as
the other high-side drivers (e.g. During an over current detection, the control loop is
switched off). In electrochrome mode OUT10 cannot be controlled by PWM mode. For EMS
reasons the loop capacitor at pin ECDR as well as the capacitor between ECV and GND
have to be placed to the respective pins as close as possible.
28/47
Doc ID 15162 Rev 3
L99DZ70XP
Functional description of the SPI
4
Functional description of the SPI
4.1
General description
Standard ST-SPI Interface Version 3.0.
The SPI communication is based on a Serial Peripheral Interface interface structure using
CSN (Chip Select Not), DI (Serial Data In), DO (Serial Data Out/Error) and CLK (Serial
Clock) signal lines.
4.1.1
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) is in high impedance state. A low signal wakes up the device and a serial
communication can be started. The state when CSN is going low until the rising edge of
CSN will be called a communication frame.
4.1.2
Serial Data In (DI)
The input pin is used to transfer data serially into the device. The data applied to the DI will
be sampled at the rising edge of the CLK signal.
4.1.3
Serial Clock (CLK)
This input signal provides the timing of the serial interface. The Data Input (DI) is latched at
the rising edge of Serial Clock CLK . The SPI can be driven by a micro controller with its SPI
peripheral running in following mode: CPOL = 0 and CPHA = 0. Data on Serial Data Out
(DO) is shifted out at the falling edge of the serial clock (CLK). The serial clock CLK must be
active only during a frame (CSN low). Any other switching of CLK close to any CSN edge
could generate set up/hold violations in the SPI logic of the device.
The clock monitor counts the number of clock pulses during a communication frame (while
CSN is low). If the number of CLK pulses does not correspond to the frame width indicated
in the <SPI-frame-ID> (ROM address 03H) the frame is ignored and the <frame error> bit in
the <Global Status Byte> is set.
Note:
Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
4.1.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the global status bit 7 (Global Error
Flag). The first rising edge of the CLK input after a high to low transition of the CSN pin will
transfer the content of the selected status register into the data out shift register. Each
subsequent falling edge of the CLK will shift the next bit out.
Doc ID 15162 Rev 3
29/47
Functional description of the SPI
4.1.5
L99DZ70XP
SPI communication flow
At the beginning of each communication the master can read the contents of the <SPIframe-ID> register (ROM address 03H) of the slave device. This 8-bit register indicates the
SPI frame length (24 bit) and the availability of additional features.
Each communication frame consists of a command byte which is followed by 2 data bytes.
The data returned on DO within the same frame always starts with the <Global Status>
Byte. It provides general status information about the device. It is followed by 2 data bytes (i.
e. ‘In-frame-response’).
For Write cycles the <Global Status> Byte is followed by the previous content of the
addressed register.
Figure 10. Write and read SPI
30/47
Doc ID 15162 Rev 3
L99DZ70XP
Table 20.
Functional description of the SPI
SPI frame
Command Byte
Data Byte
Data Byte
Bit
23
22
21
29
19
18
17
16
15
14
13
12
11
10
9
8
Name
OC1
OC0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Ocx: Operation code
Ax: Address
Dx: Data Bit
4.2
Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (<Read>, <Write>, <Read and Clear>, <Read Device
Information>) and a 6 bit address. If less than 6 address bits are required, the remaining bits
are unused but are reserved.
4.2.1
Operation code definition
Table 21.
Operation code definition
OC1
OC0
Meaning
0
0
<Write Mode>
0
1
<Read Mode>
1
0
<Read and Clear Mode>
1
1
<Read Device Information>
The <Write Mode> and <Read Mode> operations allow access to the RAM of the device.
A <Read and Clear Mode> operation is used to read a status register and subsequently
clear its content.
The <Read Device Information> allows access to the ROM area which contains device
related information such as <ID-Header>, <Product Code>, <Silicon Version and Category>
and <SPI-frame-ID>.
Doc ID 15162 Rev 3
31/47
Functional description of the SPI
4.3
L99DZ70XP
Global status byte
Table 22.
Global status byte
Bit
7
6
5
4
3
2
1
0
Name
GL_ER
CO_ER
C_RESET
TSD
TW
UOV_OC
OL
NR
Reset
0
0
1
0
0
0
0
0
Description:
32/47
●
GL_ER : Global Error Flag. Failures of Bits 0-6 are always linked to the Global Error
Flag. This flag is generated by an OR combination of all failure events of the device. It
is reflected via the DO pin while CSN is held low and no clock signal is available. The
flag will remain as long as CSN is low. This operation does not cause the
Communication Error bit in the <Global Status> to be set. The signal TW bit3 and OL
bit1can be masked.
●
CO_ER : Communication Error. If the number of clock pulses within the previous frame
is not 24 the frame is ignored and this bit is set.
●
C_RESET : Chip RESET. If a stuck at ‘1’ on input DI during any SPI frame occurs, or if
a Power On Reset (VCC monitor) occurs. C_RESET will be reset (‘1’) with any SPI
command. When STK_RESET_Q is active (‘0’), the Gate drivers are switched off
(resistive path to source).
After a startup of the circuit the STK_RESET_Q is active because of the POR pulse
and the Gate drivers are switched off. The Gate drivers can only be activated after the
STK_RESET_Q has been reset with a SPI command.
●
TSD : Thermal shutdown due to an internal sensor. All the gate drivers and the charge
pump must be switched off (resistive path to source). The TSD bit has to be cleared
through a software reset to reactivate the gate drivers and the charge pump.
●
TW : Thermal Warning. This bit is maskable by configuration register.
●
UOV_OC : Logical OR among the filtered under-/over-voltage signals and over-current
signals.
●
OL : Open Load. Logical OR among the filtered under-current signals. This bit is
maskable by configuration register.
●
NR : Not Ready. After switching the device from standby mode to active mode an
internal timer is started to allow chargepump to settle before the outputs can be
activated. This bit is cleared automatically after start up time has finished.
Doc ID 15162 Rev 3
L99DZ70XP
Functional description of the SPI
Figure 11.
4.4
Global error flag definition
Address mapping
Table 23.
RAM memory map
Address
Name
00h
Control register 0
Read/write Enable of device and bridge control
01h
Control register 1
Read/write
High/low-side control and Electrocrome block set
up
02h
Control register 2
Read/write
Bridge recovery mode and PWM set up and
Electrocrome block set up
03h
Control register 3
Read/write
Highside recovery mode and PWM set up and
current monitor selection
10h
Status register 0
Read only
Bridge over-current diagnosis
11h
Status register 1
Read only
Bridge open load (under-current) diagnosis
12h
Status register 2
Read only
Open load (under-current) diagnosis, VS and
electrocrome diagnosis
3Fh
Configuration
register
Read/write
Mask of bits in global status register and for global
error bit
Table 24.
Access
Content
ROM memory map
Address
Name
Access
Content
00h
ID header
Read only
4300h (ASSP ST_SPI)
01h
Version
Read only
0300h
02h
Product code 1
Read only
4300h (67 ST_SPI)
03h
Product code 2
Read only
4800h (H ST_SPI)
3Eh
SPI-frame ID
Read only
0200h SPI-Frame-ID register (ST_SPI)
Doc ID 15162 Rev 3
33/47
SPI - control and status registers
L99DZ70XP
5
SPI - control and status registers
5.1
Control register 0
Table 25.
34/47
Control register 0 (read/write)
Bit
Name
15
OUT1 – HS
on/off
14
OUT1 – LS
on/off
13
OUT2 – HS
on/off
12
OUT2 – LS
on/off
11
OUT3 – HS
on/off
10
OUT3 – LS
on/off
9
OUT4 – HS
on/off
8
OUT4 – LS
on/off
7
OUT5 – HS
on/off
6
OUT5 – LS
on/off
5
OUT6 – HS
on/off
4
OUT6 – LS
on/off
3
0
2
0
1
0
0
Enable bit
Comment
If a bit is set the selected output driver is switched on. If the corresponding
PWM enable bit is set the driver is only activated if PWM1 (PWM2) input
signal is high. The outputs of OUT1-OUT6 are half bridges. If the bits of
HS- and LS-driver of the same half bridge are set, the internal logic
prevents that both drivers of this output stage can be switched on
simultaneously in order to avoid a high internal current from Vs to GND.
Reserved (has to be set to '0')
If enable bit is set the device will be switched in active mode. If enable bit is
cleared, the device enters standby mode and all bits are cleared.
Doc ID 15162 Rev 3
L99DZ70XP
5.2
SPI - control and status registers
Control register 1
Table 26.
Control register 1 (read/write)
Bit
Name
15
OUT7 – HS1
on/off
14
OUT7 – HS2
on/off
Comment
OUT
7/8
HS1 HS2
Mode
1
1
Off
OUT8 – HS1
on/off
1
0
Low on-resistance
0
1
High on-resistance
OUT8 – HS2
on/off
0
0
Off
12
11
OUT9 – HS
on/off
10
OUT10 – HS
on/off
9
OUT11 – HS
on/off
8
ECV – LS on/off
7
EC bit 5
6
EC bit 4
5
EC bit 3
4
EC bit 2
3
EC bit 1
2
EC bit 0
13
1
EC switch
0
0
If a bit is set, the selected output driver is switched on. If the corresponding
PWM enable bit is set the driver is only activated if PWM1 (PWM2) input
signal is high. The outputs of OUT1-OUT6 are half bridges. If the bits of HSand LS-driver of the same half bridge are set, the internal logic prevents that
both drivers of this output stage can be switched on simultaneously in order to
avoid a high internal current from VS to GND.
Reference value for difference voltage amplifier at pin ECV is binary coded.
Full scale value is set in control register 2. If all EC bits are set to zero the
reference value is 0V. For fast discharge a lowside switch can be activated at
pin ECV, if the ECV – LS on/off bit is set to '1'..
In case this bit is set to 1, the electrochrome control is active and enables the
driver at pin ECDR for the external MOS transistor. The bit switches the
highside OUT10 directly on, ignoring bit 10 in control register 1. If the drain of
the external MOS transistor is connected to OUT10, the current from supply
VS to the load at ECV can be monitored.
Reserved (has to be set to '0')
Doc ID 15162 Rev 3
35/47
SPI - control and status registers
5.3
Control register 2
Table 27.
Control register 2 (read/write)
Bit
Name
15
OUT1 – OCR
enable
14
OUT2 – OCR
enable
13
OUT3 – OCR
enable
12
OUT4 – OCR
enable
11
OUT5 – OCR
enable
10
OUT6 – OCR
enable
9
ECV – OCR
enable
8
0
7
OUT1 PWM1
enable
6
OUT2 PWM1
enable
5
OUT3 PWM1
enable
4
OUT4 PWM1
enable
3
OUT5 PWM2
enable
2
OUT6 PWM1
enable
1
ECV PWM1
enable
0
36/47
L99DZ70XP
ECV-low voltage
Comment
In case of an over-current event the over-current status bit (Status
Register 0) is set and the output is switched off. If the Over-current
Recovery Enable bit (OCR) is set, the output will be automatically
reactivated after a delay time resulting in a PWM modulated current with
a programmable duty cycle (bit 5 of control register 3).
Depending on occurrence of over-current event and internal clock phase
it is possible that one recovery cycle is executed even if this bit is set to
zero. The ECV-OCR enable bit is disabled in electrochrome mode
(bit1=1 control register 1).
Reserved (has to be set to '0')
If the PWM1/2 Enable bit is set and the output is enabled (control
register 0 or 1) the output is switched on if PWM1/2 input is high and
switched off if PWM1/2 input is low. OUT5, 8 and OUT10 are controlled
by PWM2 input, all other outputs are controlled by PWM1 input.
The maximum ECV voltage in electrochrome mode is 1.5V. It
corresponds to the full scale range of the digital to analog converter DAC
set by the bits 7 to 2 of control register 1. If the ECV_low voltage bit is
set to '0', the maximum voltage is limited to 1.2V without changing the
resolution of the DAC. This is the default mode.
Doc ID 15162 Rev 3
L99DZ70XP
5.4
SPI - control and status registers
Control register 3
Table 28.
Control register 3 (read/write)
Bit
Name
Comment
15
OUT7-OCR enable
14
OUT8-OCR enable
13
OUT9-OCR enable
12
OUT10-OCR enable
11
OUT11-OCR enable
In case of an over-current event the over-current status bit (Status
register 1) is set and the output is switched off. If the Over-current
Recovery Enable bit (OCR) is set the output will be automatically
reactivated after a delay time resulting in a PWM modulated current
with a programmable duty cycle (bit 5). Depending on the
occurrence of the over-current event and the internal clock phase it
is possible that one recovery cycle is executed even if this bit is set
to zero.
10
OUT7 PWM1 enable
9
8
7
6
If the PWM1/2 Enable bit is set and the output is enabled (control
register 0 or 1) the output is switched on if PWM1/2 input is high and
OUT9 PWM1 enable switched off if PWM1/2 input is low. OUT5, 8 and OUT10 are
controlled by PWM2 input all other outputs are controlled by PWM1
OUT10 PWM2 enable
input.
OUT11 PWM1 enable
OUT8 PWM2 enable
5
OCR frequency
0: 1.7 kHz
1: 3 kHz
This bit defines in combination with the over-current recovery bit
(Input Register 1) the over-current recovery frequency of an
activated driver.
4
OV/UVR disable
If this bit is set the microcontroller has to clear the status register
after undervoltage/overvoltage event to enable the outputs.
Depending on combination of bit 3 to 0 the current image of
the selected highside output OUTn will be multiplexed to the
CM/PWM2 output (see table below).
Other combinations deactivate the current monitor.
3
2
1
0
CM select bit 3
Bit 3
Bit 2
Bit 1
Bit 0
Current image of
0
0
0
0
OUT1
0
0
0
1
OUT2
0
0
1
0
OUT3
0
0
1
1
OUT4
0
1
0
0
OUT5
0
1
0
1
OUT6
0
1
1
0
OUT7
0
1
1
1
OUT8
1
0
0
0
OUT9
1
0
0
1
OUT10
1
0
1
0
OUT11
CM select bit 2
CM select bit 1
CM select bit 0
Doc ID 15162 Rev 3
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SPI - control and status registers
5.5
L99DZ70XP
Status register 0
Table 29.
Status register 0 (read)
Bit
Name
15
OUT1 – HS OC
14
OUT1 – LS OC
13
OUT2 – HS OC
12
OUT2 – LS OC
11
8
OUT3 – HS OC In case of an over-current event the corresponding status bit is set and the
output driver is disabled. If the over-current Recovery Enable bit is set the
OUT3 – LS OC output will be automatically reactivated after a delay time resulting in a
OUT4 – HS OC PWM modulated current with a programmable duty cycle.
If the over-current recovery bit is not set, the micro controller has to clear
OUT4 – LS OC the over-current bit to reactivate the output driver.
7
OUT5 – HS OC
6
OUT5 – LS OC
5
OUT6 – HS OC
4
OUT6 – LS OC
3
0
2
0
1
0
0
0
10
9
Comment
Reserved
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Doc ID 15162 Rev 3
L99DZ70XP
5.6
SPI - control and status registers
Status register 1
Table 30.
Bit
15
Status register 1 (read)
Name
Comment
14
OUT1 – HS UC Maskable by the
OUT1 – LS UC configuration register
13
OUT2 – HS UC
12
OUT2 – LS UC
11
OUT3 – HS UC
10
7
The open load detection monitors the load current in each activated output
stage. If the load current is below the under-current detection threshold for
OUT4 – HS UC at least 1 ms (t
dOL) , the corresponding under-current bit UC is set. Due to
OUT4 – LS UC mechanical/electrical inertia of typical loads a short activation of the outputs
(e.g. 3ms) can be used to test the open load status without changing the
OUT5 – HS UC mechanical/electrical state of the loads.
6
OUT5 – LS UC
5
OUT6 – HS UC
4
OUT6 – LS UC
3
0
2
0
1
0
0
0
9
8
OUT3 – LS UC
Reserved
Doc ID 15162 Rev 3
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SPI - control and status registers
5.7
Status register 2
Table 31.
Status register 2 (read)
Bit
Name
15
OUT7 – OC
14
OUT7 – UC
13
OUT8 – OC
12
OUT8 – UC
11
OUT9 – OC
10
OUT9 – UC
9
OUT10 – OC
8
OUT10 – UC
7
OUT11 – OC
6
OUT11 – UC
5
ECV – OC
4
ECV – UC
3
VS
under-voltage
2
VS
over-voltage
1
0
40/47
L99DZ70XP
Comment
In case of an over-current event the corresponding status bit OC is set and
the output driver is disabled. If the over-current recovery enable bit is set
the output will be automatically reactivated after a delay time resulting in a
PWM modulated current with a programmable duty cycle.
If the over-current recovery bit is not set the micro controller has to clear the
over-current bit to reactivate the output driver.
The open load detection monitors the load current in each activated output
stage. If the load current is below the under-current detection threshold for
at least 1 ms (tdOL) the corresponding under-current bit UC is set. Due to
mechanical/electrical inertia of typical loads a short activation of the outputs
(e.g. 3ms) can be used to test the open load status without changing the
mechanical/electrical state of the loads.
In case of an over-voltage or under-voltage event the corresponding bit is
set and the outputs are deactivated. If VS voltage recovers to normal
operating conditions outputs are reactivated automatically (if bit 4 of control
register 3 is not set).
ECV voltage not Two comparators monitor the voltage at pin ECV in electrocrome mode. If
reached
this voltage is below / above the programmed target these bits signal the
difference after at least 32 µs. The bits are not latched and may toggle after
ECV voltage
at least 32 µs, if the ECV voltage has not yet reached the target. They are
too high
not assigned to the Global Error Flag.
Doc ID 15162 Rev 3
L99DZ70XP
5.8
SPI - control and status registers
Configuration register
Table 32.
Configuration register (read/write)
Bit
Name
Comment
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
Mask for bit 15 of
status reg. 1
Openload event (under-current status bit of OUT1 HS) is not
considered in openload bit 1 of global status register.
4
Mask for bit 14 of
status reg. 1
Openload event (under-current status bit of OUT1 LS) is not
considered in openload bit 1 of global status register.
3
Mask for bit 3 of
global status reg.
Temperature warning event is not considered in the 'Global Error
Flag'.
2
0
1
Mask for bit 1 of
global status reg.
0
0
Reserved (has to be set to '0')
Reserved (has to be set to '0')
Openload event (under-current status bit of OUTn) is not considered
in the 'Global Error Flag'.
Reserved (has to be set to '0')
Doc ID 15162 Rev 3
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Packages thermal data
6
L99DZ70XP
Packages thermal data
Figure 12. Packages thermal data
42/47
Doc ID 15162 Rev 3
L99DZ70XP
Package and packing information
7
Package and packing information
7.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.2
PowerSSO-36 package information
Figure 13. PowerSSO-36 package dimensions
Doc ID 15162 Rev 3
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Package and packing information
Table 33.
L99DZ70XP
PowerSSO-36 mechanical data
Symbol
Millimeters
Min.
Typ.
Max.
A
-
-
2.45
A2
2.15
-
2.35
a1
0
-
0.1
b
0.18
-
0.36
c
0.23
-
0.32
D(1)
10.10
-
10.50
E
7.4
-
7.6
e
-
0.5
-
e3
-
8.5
-
F
-
2.3
-
G
-
-
0.1
G1
-
-
0.06
H
10.1
-
10.5
h
-
-
0.4
k
0°
-
8°
L
0.55
-
0.85
M
-
4.3
-
N
-
-
10°
O
-
1.2
-
Q
-
0.8
-
S
-
2.9
-
T
-
3.65
-
U
-
1
-
X
4.3
-
5.2
Y
6.9
-
7.5
1. “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm
per side (0.006”).
44/47
Doc ID 15162 Rev 3
L99DZ70XP
7.3
Package and packing information
PowerSSO-36 packing information
Figure 14. PowerSSO-36 tube shipment (no suffix)
C
Base Qty
Bulk Qty
Tube length (±0.5)
A
B
C (±0.1)
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 15. PowerSSO-36 tape and reel shipment (suffix “TR”)
Reel dimensions
Base Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (±0.1)
P
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Doc ID 15162 Rev 3
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Revision history
8
L99DZ70XP
Revision history
Table 34.
46/47
Document revision history
Date
Revision
Description of changes
12-Nov-2008
1
Initial release.
02-Jul-2009
2
Table 33: PowerSSO-36 mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.50 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed L (max) value from 0.90 to 0.85
19-Nov-2010
3
Updated Figure 1: Block diagram
Doc ID 15162 Rev 3
L99DZ70XP
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