Specification 910.71 DC Motor Controller with Ripple Detection (Pulse Count) Features Brief Functional Description • 6 Half Bridges configurable to drive 3, 4, or 5 DC Motors • Half Bridges not needed for Motor Control may drive other kinds of loads • Output Current max. 540 mA per Half Bridge • Three independent Pulse Detectors and Counters • Servo Control Positioning of Actuators • Excellent Positioning Performance • SPI for communication with µC • Short Circuit Protection • Overtemperature Protection • Battery Supply and 5V Monitor • Diagnostic Data via SPI Application • The integrated circuit (IC) E 910.71 features 6 configurable half bridges to drives up to 3 DC motors simultaneously or up to 5 motors sequentially. 3 independent pulse detection circuits convert the commutation current of the motors into countable digital signals for positioning especially of HVAC flap actuators. µC sends motor address, direction and pulse count commands to the device via a SPI. The corresponding motor will then be driven to the desired position and the actual number of counts is sent back to the µC. Diagnostic data, such as over-current, overtemperature and motor stall, is also transmitted via the SPI. An open drain low-side output indicates when a required motor position is reached or diagnostic data is available. ICs can be connected in a Daisy Chain. Positioning of HVAC Flaps *) *) according to US patent 5,203,499 owned by BHTC ELMOS Semiconductor AG Design Specification 1 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Typical Application CB2 D1 CB1 µC Interface RPU CVDD +5V CLK PGND CSB OUT6 RXD VBAT TXD OUT5 CSOB PGND DRB OUT4 TPIN VBAT TMODE OUT3 VSS PGND VDD OUT2 TANA VBAT CLP1 CLP1 OUT1 CLP2 CLP2 PGND CLP3 CLP3 CCP n.c. M M3 M M5 (optional) M M2 M M4 (optional) M M1 Vbat CCP n.c. = not connected Gnd Figure 1: Application Circuit for SO28 CVDD CLP1 CLP2 CLP3 CCP CB1 CB2 D1 RPU Recommended External Components Function bypass capacitor for 5 V supply capacitance for low pass filter in ripple counter 1 capacitance for low pass filter in ripple counter 2 capacitance for low pass filter in ripple counter 3 storage capacitor for charge pump bypass capacitor for battery supply buffer capacitor for battery supply diode for reverse voltage protection pull up resistor for open drain pin DRB ELMOS Semiconductor AG Specification 2 / 51 Typ. Value 100 nF (+-20%) 47 nF (+-20%) 47 nF (+-20%) 47 nF (+-20%) 47 nF (+-20%) 100 nF (+-20%) 220 µF (+-20%) 10 kΩ (+-20%) (min. 2.2 kΩ) max. 100 kΩ ) 03SP0350E.03 Oct. 24, 2006 910.71 1 Pinout 1.1 Pin Description Name Pin No. SO28 Pin No. QFN.L32 MLFP.L32 MLPQ32L7 Type ESD Protection Description VDD CLK 1 29 D I PD Clock input of SPI VSS CSB 2 30 D I PU see CSB Chip Select Bar input, active low RXD 3 31 D I PD see CSB Receive data input of SPI VDD TXD 4 32 DO Transmit data output of SPI VSS NC - 1 No internal connection, to be connected to ground VDD CSOB 5 2 DO VSS Chip Select Out Bar output / Daisy Chain output, active low VDD DRB 6 3 D O OD VSS Data Ready Bar flag output, open drain, active low VDD TPIN 7 4 D I/O Digital test input pin, to be connected to ground VSS VDD TMODE 8 5 DI Test enable, to be connected to ground VSS VSSD 9 6 G - Digital Ground VSSA 9 7 G - Analog Ground VDD 10 8 SI VSS ELMOS Semiconductor AG 5 V supply input for analog and digital part (not for motor driver) Specification 3 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Name Pin No. SO28 Pin No. QFN.L32 MLFP.L32 MLPQ32L7 Type ESD Protection Description VDD TANA 11 9 Test in/out analog, must not be connected D/A I/O VSS VDD CLP1 12 10 A I/O Low pass filter capacitor for ripple detection 1 VSS VDD CLP2 13 11 A I/O Low pass filter capacitor for ripple detection 2 VSS VDD CLP3 14 12 A I/O Low pass filter capacitor for ripple detection 3 VSS VDD CCP 15 13 AO External charge pump capacitor VSS PGND 16 14 G - Power gnd VBAT OUT1 17 15 DO Output half bridge 1 PGND VBAT 18 16 S Battery supply PGND NC No internal connection, to be connected to ground - 17 - OUT2 19 18 DO PGND 20 19 G OUT3 21 20 DO see OUT1 Output half bridge 3 VBAT 22 21 S see above Battery supply OUT4 23 22 DO see OUT1 Output half bridge 4 PGND 24 23 G OUT5 25 24 DO - 25 NC ELMOS Semiconductor AG see OUT1 - see OUT1 - - Output half bridge 2 Power gnd Power gnd Output half bridge 5 No internal connection, to be connected to ground Specification 4 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Pin No. SO28 Pin No. QFN.L32 MLFP.L32 MLPQ32L7 VBAT 26 26 OUT6 27 PGND NOVDD Name ESD Protection Description S see above Battery supply 27 DO see OUT1 Output half bridge 6 28 28 G - - Type DO see TXD Power gnd Test: Indicates that VDD=0V D = digital, A = analog, I = input, O = output, S = supply, G = gnd, PD = pull down, PU = pull up, OD = open drain ELMOS Semiconductor AG Specification 5 / 51 03SP0350E.03 Oct. 24, 2006 910.71 1.2 Package Pinout Top View 1 CLK PGND 28 2 CSB OUT6 27 3 RXD VBAT 26 4 TXD OUT5 25 5 CSOB PGND 24 6 DRB OUT4 23 7 TPIN VBAT 22 8 TMODE OUT3 21 9 VSS PGND 20 10 VDD OUT2 19 11 TANA VBAT 18 12 CLP1 OUT1 17 13 CLP2 PGND 16 14 CLP3 CCP 15 Figure 1.2-1: Pinout SO28 ELMOS Semiconductor AG Specification 6 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Top View 26 VBAT OUT6 PGND CLK 27 25 NC/GND 23 3 DRB OUT4 22 4 TPIN VBAT 21 5 TMODE OUT3 20 6 VSSD PGND 19 7 VSSA OUT2 18 8 VDD NC/GND 17 TANA 9 OUT1 PGND PGND CSOB CCP 24 10 11 12 13 14 15 16 CLP3 2 28 OUT5 CLP2 NC/GND CLP1 1 CSB TXD 31 30 29 RXD 32 VBAT Exposed die pad on back side to be connected to ground Figure 1.2-2: Pinout QFN.L32.7x7/ MLFP.L32.7x7 / MLPQ32L7 ELMOS Semiconductor AG Specification 7 / 51 03SP0350E.03 Oct. 24, 2006 910.71 2 Block Diagram VCP VBAT Charge Pump VBAT Half Bridge 1 Internal Supply References Gate Drive Oscillator VDD OUT1 Ctrl. Digital Control Logic +5V Gate Drive M M1 M M4 (optional) M M2 M M5 (optional) M M3 Diag. CLK CSB RXD TXD CSOB Clock Chip Select Data-in Data-out Chip Sel. Out DRB Data Ready TPIN Test Pin TMODE Test Mode Motor Control SPI Interface Rip. Det. 1 Rip. Det. 2 MUX Rip. Det. 3 Test Mode Register OUT2 Half Bridge 2 OUT3 TANA OUT4 Half Bridge 3 Analog Test Mupliplexer OUT5 Half Bridge 4 OUT6 Half Bridge 5 Half Bridge 6 VSS PGND Low Pass Filter Caps CLP1 CLP2 CLP3 GND Figure 2-1: Block Diagram ELMOS Semiconductor AG Specification 8 / 51 03SP0350E.03 Oct. 24, 2006 910.71 3 Operating Conditions 3.1 Absolute Maximum Ratings Operating the device beyond these limits may cause permanent damage. Parameter Condition Min. Max. Unit VBAT - 0.3 28 V VBAT - 0.3 40 V VDD - 0.3 5.5 V VDD - 0.3 6 V Vout - 0.3 VBAT + 0.3 V Iout - 800 800 mA Output voltage TXD, DC, DRB Vout - 0.3 VDD + 0.3 V Output current TXD, DC, DRB Iout -5 5 mA Input voltage RXD, CSB, CLK, TMODE - 4 Vin - 0.3 VDD + 0.3 V Input current RXD, CSB, CLK, TMODE - 4 Iin - 10 10 mA Thermal resistance junction to ambiSO 28 ent RTJA 80 K/W Battery supply voltage Battery supply voltage t < 500 ms Digital supply voltage Digital supply voltage t < 500 ms Output voltage Out 1 – Out 6 Output current Out 1 – Out 6 0 V < Vout < Vbat Internally limited Symbol Power dissipation Tamb ≤ 85 °C Pdiss 820 mW Thermal resistance junction to case QFN.L32.7x7 / MLFP.L32.7x7 / MLPQ32L7 RTJC1 0.5 K/W QFN.L32.7x7 / Thermal resistance junction to ambiMLFP.L32.7x7 / ent MLPQ32L7 RTJA1 1) 30 K/W Thermal resistance junction to case RTJC2 24 K/W Thermal resistance junction to ambiSO28 ent RTJA2 1) 80 K/W Junction temperature TJ - 40 150 °C Storage temperature TSTG - 40 150 °C ELMOS Semiconductor AG SO28 Specification 9 / 51 03SP0350E.03 Oct. 24, 2006 910.71 1) Thermal Resistance depends on many factors. These values should be attainable with a good PCB layout, see. example (tbd.) ELMOS Semiconductor AG Specification 10 / 51 03SP0350E.03 Oct. 24, 2006 910.71 3.2 Recommended Operating Conditions Parameters are guaranteed within the range of operating conditions unless otherwise specified. Parameter Condition Symbol Min. Max. Unit Battery supply voltage VBAT 6 18 V Logic supply voltage VDD 4.5 5.5 V Operating temperature range Tamb - 40 85 °C All voltages are referred to gnd and currents are positive when flowing into the node, unless otherwise specified. ELMOS Semiconductor AG Specification 11 / 51 03SP0350E.03 Oct. 24, 2006 910.71 4 Detailed Electrical Specification 4.1 Supply Section 4.1.1 DC Characteristics Battery Supply No. Parameter Condition Symbol Min. Typ. Max. Unit 6 12 18 V 0.42 3 mA 8 50 µA Battery Supply VBAT 1 Operating voltage range 2 Operating supply current 3 Stand-by current IBAT,stby 4 Undervoltage detection VBAT,low 4.1 4.6 5.1 V 5 Undervoltage hysteresis VBAT,l,hys 70 150 225 mV 6 Overvoltage detection VBAT,high 18 20.5 23 V 7 Overvoltage hysteresis VBAT,h,hys 170 400 630 mV Symbol Min. Typ. Max. Unit VBAT all outputs unloaded IBAT 4.1.2 AC Characteristics Battery Supply No. Parameter Condition Battery Supply VBAT 1 Overvoltage debounce* Tdebvb,ov,off 7 10 18 ms 2 Turn on debounce after overvoltage shut off* Tdebvb,ov,on 7 10 18 ms 3 Under-voltage debounce* Tdebvb,uv,off 7 10 18 ms ELMOS Semiconductor AG Specification 12 / 51 03SP0350E.03 Oct. 24, 2006 910.71 4.1.3 DC Characteristics Digital/Analog Supply No. Parameter Condition Symbol Min. Typ. Max. Unit 4.5 5 5.5 V 1.8 5 mA 15 50 µA 3 3.4 V Digital/Analog Supply VDD 1 Operating voltage range VDD 2 Operating supply current IDD 3 Stand-by current 4 Under voltage reset in stand-by mode IDD,stby VDD,low 2.6 Under voltage detection of VDD creates reset in digital part, directly, without debounce time. 4.1.4 Overtemperature Shut Off No. Parameter Condition Symbol Min. Typ. Max. Unit 1 Overtemperature shut off threshold Referred to Junction Temperature 1) Tso 145 170 190 °C 2 Overtemperature turn on hysteresis 1) Thys 5 20 38 °C 1) Measured only during qualification, general function tested in production 5b High side current limitation VBAT = 12 V -40°C ≤ T < 0°C -1100 -750 -550 mA Min. Typ. Max. Unit Vbat + 0.3 V 3 Ω 4.2 Motor Driver Half Bridges 4.2.1 DC Characteristics Outputs OUT1 - OUT6 No. Parameter Condition Symbol Outputs OUT1 - OUT6 1 Input voltage 2 On resistance VBAT = 12 V |IOUT| = 200mA Ron,12 1.8 3 On resistance VBAT = 6 V |IOUT| = 200mA Ron,6 3 ELMOS Semiconductor AG Vin,rev Specification 13 / 51 - 0.3 Ω 03SP0350E.03 Oct. 24, 2006 910.71 No. Parameter Condition Symbol Min. Typ. Max. Unit 5 µA 4 Leakage current in Tri State Mode VOUT = 0 V Ileak -5 5a High side current limitation VBAT = 12 V 0°C ≤ T< 85°C Ilim,h - 1000 - 750 - 550 mA 5a High side current limitation VBAT = 12 V -40°C ≤ T < 0°C Ilim,h_m40 -1100 -750 -550 mA 6a Low side current limitation VBAT = 12 V 0°C ≤ T< 85°C Ilim,l 550 750 1000 mA 6b Low side current limitation VBAT = 12 V -40°C ≤ T< 0°C Ilim,l_m40 550 750 1100 mA 4.2.2 AC Characteristics Outputs OUT1 - OUT6 No. Parameter Condition Symbol Min. Typ. Max. Unit Outputs OUT1 - OUT6 1 Turn on slew rate 20% - 80% Vbat, RLOAD= 50 Ohm dV/dt,on to PGND 0.3 0.5 1.1 V/µs 2 Turn off slew rate 80% - 20% Vbat, RLOAD= 50 Ohm dV/dt, off to PGND -1.1 - 0.5 - 0.3 V/µs 3 Over-current shut off debounce 7 10 18 ms ELMOS Semiconductor AG Tso,oc Specification 14 / 51 03SP0350E.03 Oct. 24, 2006 910.71 4.2.3 DC Characteristics Charge Pump No. Parameter Condition Symbol Min. Typ. Max. Unit 2 Vbat V Charge Pump 1 2 3 Output voltage Vbat < 11 V, Icp = 5 µA, OUTx = high Z tested at Vbat=6V Output voltage 11 V < Vbat < 16 Icp = 5 µA, Vcp12 OUTx = high Z tested at Vbat=12V Output voltage Vbat > 16 V, Icp = 5 µA, Vcp18 OUTx = high Z tested at Vbat=18V Vcp6 2 Vbat - 3 21 16 + 7 V 16 + 11 V 4.3 Ripple Detection 4.3.1 DC Characteristics Gain of Input Amplifier No. Parameter Condition Symbol Min. Typ. Max. Unit Gain of Input Amplifier 1 Motor cur- high gain=”11” rent normal nonlinearity =”01” Imot 1) - 15 200 mA 2 Motor cur- medium gain=”10” rent normal nonlinearity =”01” Imot 1) - 23 320 mA 3 Motor cur- low gain=“01“ rent normal nonlinearity =”01” Imot 1) - 37 540 mA 4 Motor cur- high gain=”11” rent high nonlinearity =”11” Imot 1) -15 540 mA 5 Motor cur- medium gain=”10” Imot rent medium nonlinearity =”10” 1) -23 540 mA 6 nonlin bits =”01” Open load gain bits=”11” detection Imot_olp threshold obs_ov_un_vbat_imot_gt_ 07p='1'; 10 mA 1) Max. value is maximum motor stall current, min. value is reverse current from motor operating in generator mode. ELMOS Semiconductor AG Specification 15 / 51 03SP0350E.03 Oct. 24, 2006 910.71 4.3.2 AC Characteristics Conditions for Pulse Shapes No. Parameter Condition Symbol Min Typ Max Unit Amplitude threshold for pulses to be detected by pulse detector 1 gain bits=”11” pulse threshold bits=”011” pulse length bits=”010” Threshold of nonlin bits=”01” negative current Idr,neg drop amplitude tau_inc bit='1' @ Imot,DC= 10mA max. tfall=20µs min. tpulsewidth=150µs 0.68 mA 2 gain bits=”10” pulse threshold bits=”011” pulse length bits=”010” Threshold of nonlin bits=”01” negative current Idr,neg drop amplitude tau_inc bit='1' @ Imot,DC= 16mA max. tfall=20µs min. tpulsewidth=150µs 1.0 mA 3 gain bits=”01” pulse threshold bits=”011” pulse length bits=”010” Threshold of nonlin bits=”01” negative current Idr,neg drop amplitude tau_inc bit='1' @ Imot,DC= 27mA max. tfall=20µs min. tpulsewidth=150µs 1.75 2.6 mA 4 Pulse width threshold for pulses to be detected 100 160 µs pulse length bits=”010” ELMOS Semiconductor AG tpl 1) 60 Specification 16 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Min. peak-peak-value threshold of sine wave signals to be detected by sine wave detector 5 6 7 Threshold of sinusoidal peak-peak current gain bits =”11” nonlin bits =”01” tau_inc bit='1' @ Isin,pp Imot,DC=10mA (min.) fsin=70 Hz 0.86 mA Threshold of sinusoidal peak-peak current gain bits =”10” nonlin bits =”01” tau_inc bit='1' Isin,pp @ Imot,DC=16mA (min.) fsin=70 Hz 1.3 mA Threshold of sinusoidal peak-peak current gain bits =”01” nonlin bits =”01” tau_inc bit='1' Isin,pp @ Imot,DC=27mA (min.) fsin=70 Hz 2.1 mA Related Motor Control Timing 1 Turn off delay after last pulse Switch to High-Z mode Toff,ar 1) 70 100 160 ms Brake delay after Both low side Tbr,stall 1) 140 200 320 ms motor stall transistors on 1) Time is not tested during production test. Time is guaranteed by internal oscillator frequency and by digital design. 2 ELMOS Semiconductor AG Specification 17 / 51 03SP0350E.03 Oct. 24, 2006 910.71 4.4 Serial Peripheral Interface, SPI 4.4.1 DC Characteristics I/O Pins No. Parameter Condition Symbol Min. Typ. Max. Unit Input pins CLK, CSB, RXD 1 Input low voltage Vil 0 1.5 V 2 Input high voltage Vih VDD - 1 VDD V 3 Pull-down current Pins CLK, RXD 2 V < Vin < VDD Ipd 40 120 260 µA 4 Pull-up current Pin CSB 0 < Vin < VDD - 2V Ipu - 300 - 200 - 100 µA 0.25 0.4 V Output pins TXD, CSOB 9 Output low voltage Iout = 2.1 mA Vout,l 10 Output high voltage Iout = - 1 mA Vout,h VDD - 0.4 VDD – 0.25 V Output pin DRB (open drain) 11 Output low voltage Iout = 2.1 mA Vout 12 Leakage current DRB not active Ileak ELMOS Semiconductor AG Specification 18 / 51 0.25 0.4 V 2 µA 03SP0350E.03 Oct. 24, 2006 910.71 4.4.2 AC Characteristics I/O Pins No. Parameter Condition Symbol Min. 0.5 Typ. Max. Unit 1000 µs no limit - tspiclkper100ns ns no limit - Input pin CLK 1 Clock Period 1) tspiclkper 2 Slope time 1) tsl 3 High time of CLK 1) tspiclkh 1) tsl 100 tspiclkper/2 Input pins CSB, RXD 4 Slope time Output pins TXD, CSOB 5 Output rising slope time 10% - 90%, Cl = 10 pF 1) tsl,r 8 13 ns 6 Output falling slope time 10% - 90%, Cl = 10 pF 1) tsl,f 5 7 ns Output pin DRB 7 Output rising slope time 10% - 90%, Cl = 10 pF RPU = 10kΩ 1) tsl,r,drb 250 8 Output falling slope time 10% - 90%, Cl = 10 pF RPU = 10kΩ 1) tsl,f,drb 5 ns 8 ns Relative Timing Parameters 9 Setup time RXD before rising CLK 1) tspisu 100 tspiclkper/2 ns 10 Hold time RXD after 1) rising CLK tspiho 100 tspiclkper/2 ns 11 Time before and after clock cycles, when CSB must be active 1) tspicsb 100 tspiclkper/2 ns 12 Output delay of TXD 1) after CLK and CSB tspitxdd 50 ns Ready Time after sending first “Wake Up Command” after Stand-by Mode Ready time when leaving stand-by 13 trdy mode for activating the charge pump. 1) tested only during qualification, not in production ELMOS Semiconductor AG Specification 19 / 51 7 10 17 ms 03SP0350E.03 Oct. 24, 2006 910.71 5 Functional Description 5.1 Supply Section 5.1.1 Functional Description The device is powered by two supply voltages, Vbat and VDD. Vbat is the battery voltage behind a reverse protection diode, and VDD is the digital 5 V supply, also needed for several analog functions. Both voltages are monitored internally. For all outputs in motor control mode, in case of an overvoltage or under voltage on Vbat, all outputs are switched into brake mode (low side drivers on). Ripple detection is still performed as long as VDD is present. All outputs, which are driving other loads than motors, are only switched off in case of overvoltage. When VDD drops below the low voltage threshold all outputs are switched to High-Z (High-Impedance) mode to avoid destruction in case of a short circuit. The internal charge pump will be turned off, and the device draws only stand-by current from the Vbat supply (50 µA, max.). When VDD is present stand-by mode for both Vbat and VDD can be activated via an SPI telegram (see chapter “StandBy Mode”). Vbat and VDD may be turned on and off in any sequence. 5.2 Serial Peripheral Interface, SPI Power-on the ASIC After power-on, the ASIC starts in stand-by mode. The first commands sent to the 910.71 have to define the configuration register and read and acknowledge the diagnostic error data. Otherwise the 910.71 stays in Error Mode, i.e., signal DRB is pulled down. The idea is, that if the configuration registers become corrupt or reset (during normal operation), it will be indicated by low DRB in Error Mode. The activation can be done in the following scheme: 1. “Wake up and Read Command” to leave the stand-by mode ASIC. 2. Waiting the ready time “trdy” (see. chapter 4.4.2) after stand-by to allow the charge pump to power up. During this time all commands are ignored. The ASIC enters the error mode “command overflow”, if commands (other than “NOP” commands) are send to the ASIC during this time. 3. Writing the two configuration register with proper values. 4. Read out hardware error (configuration register error). 5. Acknowledge the hardware error, i. e. acknowledge that the configuration registers were not okay. 6. The ASIC is now properly activated and can receive further commands. Please refer chapter 5.2.22for example commands. ELMOS Semiconductor AG Specification 20 / 51 03SP0350E.03 Oct. 24, 2006 910.71 5.2.1 Functional Description Data from and to the µC is transferred by means of an SPI. Received data is translated into switching commands for all half bridge outputs, and into positioning information, in case of motor control. A single data telegram from the µC may consist of 1 byte or 3 bytes. 1 byte information is used to turn an individual output on or off, 3 bytes information is necessary to move a motor into a defined direction with a given number of commutation ripples. To stop a motor which is still moving takes a 1 byte command as well. As shown in Fig. 5.2.1-1, to start a data transmission the input signal CSB (Chip Select Bar) first has to be pulled low. Synchronised by a clock signal on CLK data is transferred into a shift register in the IC. The first bit of the data stream defines whether a 1 byte or a 3 byte information will be sent. After the appropriate number of bits has been received the shift register is stopped, and the output CSOB (Chip Select Out Bar) is pulled low, which can be seen at last falling edge of clock CLK. This signal can be used to activate the next IC in a Daisy Chain cascaded configuration. Again the first bit of the following data stream defines whether a 1 byte or a 3 byte information will be sent to the next IC. Status data, position information of motor (that has been moved) as well as hardware error information (like over-current, overtemperature) are available on output pin TXD. At the rising edge of clock CLK the data and TXD and RXD are valid and can be sampled. The bit transmission of TXD and RXD occurs simultaneously. Telegram length is defined by the leading bit no.10 transferred to RXD and may be 1 byte or 3 bytes. The 1st byte carries diagnostic information while the 2nd and 3rd byte, in case of position mode, consist of motor address, direction and actual number of ripple pulses to be counted during motor movement. In case of hardware error they contain over-current, overtemperature, voltage error or other diagnostic information. Be aware, that the maximum possible request for motor position is 2047 (=2^11-1). But in this case an overflow in the results appears, due to additional pulses in the brake phase of the motor. Therefore the maximum recommended request for motor position is 2037, supposing not more than 10 pulses in the brake mode.. CSB tspiclkh tspicsb tspiclkper tspicsb CLK tspisu tspiho RXD Bit10 Bit11 Bit12 Bit13 Bit14 Bit15 Bit16 Bit17 tspitxdd TXD HZ Bit10 Bit11 Bit12 Bit13 Bit14 Bit15 Bit16 Bit17 HZ CSOB Figure 5.2.1-1: SPI Timing for 1-Byte Transfer: Transmission starts with CSB. On rising edge of CLK (driven by µC) the transfer data RXD and TXD are valid and can be sampled. To read data from the IC without changing any output state the µC can send a telegram with the address "000". The available data, with a length defined by the leading bit of the µC's telegram, will be output on pin TXD. ELMOS Semiconductor AG Specification 21 / 51 03SP0350E.03 Oct. 24, 2006 910.71 The output DRB "Data Ready Bar" indicates that data is available. It may be diagnostic information and/or position information of a motor after it has been stopped. Definition of Data Telegram Content RXD 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 TXD 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 Byte 1 Byte 2 Byte 3 Transmission in both directions starts with Bit 10 and ends with Bit 37 5.2.2 Data received from µC, Input RXD Table 1: Byte No. 1 of RXD Data in Case of Half Bridge Control Bit No. Name Description 10 Selection Bit "0" direct control of half bridges, length of telegram is 1 byte 11 SwitchStop Bit "0" output goes low, "1" output goes high 12 ErrPos Bit ''0'' Position data of motor will be read in case of a 3 byte telegram ''1'' Hardware error will be read in case of a 3 byte telegram 13 Acknowledge "1" reset of either error or position information, depending on bit 12 14 Address Bit MSB of half bridge address 15 Address Bit 2nd bit of half bridge address 16 Address Bit LSB of half bridge address 17 Parity Bit odd parity of first byte => constant "0" or "1" leads to parity error End of data telegram after Bit 17 Table 2a: Byte No. 1 of RXD Data in Case of Motor Control Bit No. Name Description 10 Selection Bit "1" motor control, length of telegram is 3 bytes, exception: Bit 11 = "1" 11 SwitchStop Bit "1" motor with the following address will be stopped, length of telegram is 1 byte 12 ErrPos Bit ''0'' Position data of motor will be read in case of a 3 byte telegram ''1'' Hardware error will be read in case of a 3 byte telegram 13 Acknowledge "1" reset of either error or position information, depending on bit 12 14 Address Bit MSB of motor address 15 Address Bit 2nd Bit of motor address 16 Address Bit LSB of motor address 17 Parity Bit odd parity of first byte => constant "0" or "1" leads to parity error End of data telegram after Bit 17 in case Bit '11' has been '1' ELMOS Semiconductor AG Specification 22 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Table 2b: Byte No. 2 and No. 3 of RXD Data in Case of Motor Control and Bit '11' has been '0' Bit No. Name Description 20 Direction Bit "0" half bridge with the lower number is switched to high level, "1" vice versa 21 Position Bit MSB of position command, 210 22 Position Bit 2nd Bit of position command, 29 23 Position Bit 3rd Bit of position command, 28 24 Position Bit 4th Bit of position command, 27 25 Position Bit 5th Bit of position command, 26 26 Position Bit 6th Bit of position command, 25 27 Parity Bit odd parity of second byte 30 Position Bit 7th Bit of position command, 24 31 Position Bit 8th Bit of position command, 23 32 Position Bit 9th Bit of position command, 22 33 Position Bit 10th Bit of position command, 21 34 Position Bit LSB Bit of position command, 20 35 reserved 36 reserved 37 Parity Bit odd parity of third byte End of data telegram after Bit 37 Table 3: 3 Bytes Configuration Register 1 Bit No. Name Description 10 Selection Bit=1 "1" motor control, length of telegram is 3 bytes, exception: Bit 11 = "1" 11 SwitchStop Bit=0 "1" motor with the following address will be stopped, length of telegram is 1 byte 12 Write/Read Bit ''0'' Configuration register is read by external µC ''1'' Configuration register is read and overwritten by external µC Acknowledge "1" reset of error information if bit12='1' or reset of position information if bit12='0'. 14 Address Bit=1 MSB of motor address 15 Address Bit=1 2nd Bit of motor address 16 Address Bit=0 LSB of motor address 17 Parity Bit odd parity of first byte => constant "0" or "1" leads to parity error 13 ELMOS Semiconductor AG Specification 23 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Bit No. Name Description 20 Gain_Norm[1] MSB of gain of all ripple counters in normal mode 21 Gain_Norm[0] LSB of gain of all ripple counters in normal mode 22 Gain_Break[1] MSB of gain of all ripple counters in break mode 23 Gain_Break[0] LSB of gain of all ripple counters in break mode 24 PulsTh_Norm[2] MSB of pulse detector threshold for all ripple counters in normal mode 25 PulsTh_Norm[1] 2nd Bit of pulse detector threshold 26 PulsTh_Norm[0] LSB of pulse detector threshold for all ripple counters in normal mode 27 Parity Bit odd parity of second byte => constant "0" or "1" leads to parity error 30 PulsTh_Break[2] MSB of pulse detector threshold for all ripple counters in break mode 31 PulsTh_Break[1] 2nd Bit of pulse detector threshold 32 PulsTh_Break[0] LSB of pulse detector threshold for all ripple counters in break mode TauInc_Norm This bit increases Tau in the high pass of the ripple detector in normal mode by factor 6. TauInc_Break This bit increases Tau in the high pass of the ripple detector in break mode by factor 6. 33 34 35 reserved 36 reserved 37 Parity Bit odd parity of third byte => constant "0" or "1" leads to parity error Table 4: 3 Bytes Configuration Register 2 Bit No. Name Description 10 Selection Bit=1 "1" motor control, length of telegram is 3 bytes, exception: Bit 11 = "1" 11 SwitchStop Bit=0 "1" motor with the following address will be stopped, length of telegram is 1 byte 12 Write/Read Bit ''0'' Configuration register is read by external µC ''1'' Configuration register is read and overwritten by external µC Acknowledge "1" reset of error information if bit12='1' or reset of position information if bit12='0'. 14 Address Bit=1 MSB of motor address 15 Address Bit=1 2nd Bit of motor address 16 Address Bit=1 LSB of motor address 17 Parity Bit odd parity of first byte => constant "0" or "1" leads to parity error 20 NonLin_Norm[1] MSB of nonlinear shape function in normal mode 13 ELMOS Semiconductor AG Specification 24 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Bit No. Name Description 21 NonLin_Norm[0] LSB of nonlinear shape function in normal mode 22 NonLin_Break[1] MSB of nonlinear shape function in break mode 23 NonLin_Break[0] LSB of nonlinear shape function in breakl mode PulsT_Norm[2] MSB of Minimum Pulse Width to be detected as regular pulse in break mode PulsT_Norm[1] 2nd of Minimum Pulse Width to be detected as regular pulse PulsT_Norm[0] LSB of Minimum Pulse Width to be detected as regular pulse in break mode Parity Bit odd parity of second byte => constant "0" or "1" leads to parity error PulsT_Break[2] MSB of Minimum Pulse Width to be detected as regular pulse in break mode PulsT_Break[1] 2nd of Minimum Pulse Width to be detected as regular pulse PulsT_Break[0] LSB of Minimum Pulse Width to be detected as regular pulse in break mode 24 25 26 27 30 31 32 33 reserved 34 reserved 35 reserved 36 reserved 37 Parity Bit odd parity of third byte => constant "0" or "1" leads to parity error Table 5: Address Correlation Address Bits SwitchStop Bit Half Bridge Control Selection Bit = 0 Motor Control Selection Bit = 1 0001 - no reaction (NOP) no reaction (NOP) 001 0 OUT1='0' Motor 1, OUT1 - OUT2 001 1 OUT1='1' Stop Motor 1 010 0 OUT2='0' Motor 2, OUT3 - OUT4 010 1 OUT2='1' Stop Motor 2 011 0 OUT3='0' Motor 3, OUT5 - OUT6 011 1 OUT3='1' Stop Motor 3 100 0 OUT4='0' Motor 4, OUT2 - OUT3 100 1 OUT4='1' Stop Motor 4 101 0 OUT5='0' Motor 5, OUT4 - OUT5 1Address "0 0 0" can be used to read data back from TXD without changing the state of any output or to wake up the ASIC. ELMOS Semiconductor AG Specification 25 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Address Bits SwitchStop Bit Half Bridge Control Selection Bit = 0 Motor Control Selection Bit = 1 101 1 OUT5='1' Stop Motor 5 110 0 OUT6='0' Configuration Register 1 110 1 OUT6='1' invalid, no reaction 111 0 Stand-by Mode Configuration Register 2 111 1 Software Reset Software Reset 5.2.3 Data Telegram Supervision If the result of any of the parity checks is incorrect the complete telegram is ignored, and DRB gets activated. The clock input CLK is checked during CSB low time for a minimum frequency of 1 kHz. In case the frequency is lower, the data is ignored and DRB gets activated. For supervision in standby mode, the oscillator is switched on after a falling edge on CSB and the supervision gets started. The first detection period is prolonged by the settling time of internal references, which causes a start up time of the oscillator in the order of a few 100 µs. Short pulses of CSB without any SPI clock CLK are not interpreted as invalid data, DRB doesn't go low. During the short pulse, the internal oscillator is switched on. If CSB goes high, the oscillator is switched off and the ASIC stays in stand-by mode. 5.2.4 Simultaneous and/or Sequential Motor Control 4 different configurations are possible using all 6 half bridges for motor control: 1. Motors 1, 2, and 3 connected to OUT1/2, OUT3/4, and OUT5/6, respectively. All motors can be driven independently and simultaneously, no precautions to be taken in the µC. 2. Motors 1 and 4 are connected to OUT1/2, and OUT 2/3, motors 3 and 5 to OUT5/6, and OUT4/5, respectively. Only one of motors 1 and 4 can run simultaneously with only one of motors 3 and 5. 3. Motor 1 is connected to OUT1/2, motors 2, 3, and 5 are connected to OUT3/4, OUT5/6, and OUT4/5, respectively. Motor 1 can be driven independently of all others, only one of motors 2, 3, and 5 can run at a time. 4. Motors 1 through 5 are connected to OUT1/2, OUT3/4, OUT5/6, OUT2/3, and OUT4/5, respectively. All motors can only be driven sequentially. For motor numbers please refer to Fig. 1 (application circuit). If any of the motors can only be driven sequentially this has to be considered by the µC software. This is an easy task when the configuration of motors is known. The DRB flag is set when a motor has reached its required position or diagnostic data is available. So the next one may be addressed only after the motor has come to a stop. 5.2.5 Selection Bit 10, Combination of Motor Control and Half Bridge Control All half bridge outputs, that have been directly addressed once by setting Selection Bit 10 to "0", will stay in this direct access mode. Thus they will not be switched to High-Z regardless of any motor control command. The status will change when the same half bridge gets addressed by a motor control command. Status change works in both directions, the last valid command defines whether the half bridge output is under direct access or is part of a motor driver. ELMOS Semiconductor AG Specification 26 / 51 03SP0350E.03 Oct. 24, 2006 910.71 5.2.6 Motor Stop Bit 11 Motor Stop Bit 11 allows halting a motor before it has reached its final position. The motor will be stopped after the next ripple has been detected (or time-out has been expired in case of motor stall). Pulses will be counted during braking, as in any normal case, and after no ripples have been detected for 100 ms, DRB will be activated and the actual position is available via SPI. No position command has to be transferred when Bit 11 is set to "1", so the length of the data telegram is reduced to 1 Byte. 5.2.7 Gain Bits The gain bits are used to match the input amplifier's gain with the motors connected to the ASIC independently for normal mode and for break mode: All ripple detector are operating with the same gain. '00' motor with ≤ 540 mA maximum stall current (low gain) '01' motor with ≤ 540 mA maximum stall current (low gain) '10' motor with ≤ 320 mA maximum stall current (medium gain) '11' motor with ≤ 200 mA maximum stall current (high gain) 5.2.8 Pulse Threshold Bits The pulse threshold bits [2:0] control the threshold voltage of the pulse detector independently for normal mode and for break mode. The threshold can be varied according to the following table: Code Pulse Threshold in % 000 56% 001 70% 010 83% 011 100% 100 130% 101 170% 110 220% 111 280% 5.2.9 Pulse Length Bits With the pulse length bits [2:0] the minimum pulse length tpl of pulse to be detected by the pulse detector can be controlled independently for normal mode and for break mode. Pulses with a shorter length are suppressed. Code 000 001 010 011 100 typical Pulse Length tpl 60 µs 80 µs 100 µs 120 µs 140 µs ELMOS Semiconductor AG Specification 27 / 51 03SP0350E.03 Oct. 24, 2006 910.71 101 110 111 160 µs 180 µs Counter is disabled and no infinit Tau of high pass is activated 5.2.10 Nonlinearity Shape Function of Nonlinear Amplifier The nonlinear function of the input amplifier can be influenced by two bits independently for normal mode and for break mode. The nominal value is “01” for typical motors. With code “10” motorcurrent signals can amplified with one higher gain level than usual. With code “11” motor current signals can amplified with two higher gain levels than usual, without going into saturation. With code “00” the nonlinearity is reduced. Code 00 01 10 11 Influence on Nonlinearity weak non linearity normal shape higher non linearity highest non linearity 5.2.11 Tau Increase Bit The increase bit increase the Tau time constant of the high pass filter in the ripple detector by factor six independently for normal mode and for break mode. Code 0 1 Tau of high pass filter mode not allowed (Tau reduced by factor six) normal Tau 5.2.12 Recommended Configuration for Different Type of DC Motors The following table shows the recommended configuration for different 12V DC motor type for flap control. Parameter Asymmetrical Motor Symmetrical Motor (high current) Symmetrical Motor (low current) Gain in Normal Mode 01 01 11 (tbd.) Gain in Break Mode 11 10 11 (tbd.) Nonlinearity in Normal Mode 01 01 01 (tbd.) Nonlinearity in Break Mode 11 10 01 (tbd.) Pulsthreshold in Normal Mode 110 110 101 Pulsthreshold in Break Mode 100 011 101 Pulselength in Normal Mode 010 010 010 Pulselength in Break Mode 010 010 010 Tau Increase in Normal Mode 1 1 1 Tau Increase in Break Mode 1 1 1 ELMOS Semiconductor AG Specification 28 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Note: The best configuration for a specific motor has to be proven by tests. Motors (including gearing) are not recommened, if they are turning for them-self, when not driven, e.g. turning backward after breaking and surpassing a commutation point. 5.2.13 Data sent to µC, Output TXD Table: Byte No. 1 of TXD Data Bit No. Name Description 10 Invalid Data "1" last data telegram from µC has been ignored due to parity error or fclk < 1 kHz or CSB going high before the expected end of telegram 11 reserved read as zero 12 Busy "1" indicates that ASIC is not able to receive new data. Usually this bit is high for a period of typically 6 µs after a command has been sent. This bit can be polled from the external µC. 13 Command overflow "1" indicates that at least one command which has been sent from the µC is ignored. This can happen, when • the bit “Busy“ is active, while the command has been sent • a motor is running, while the motor controller receives a new command • a count value is not read and acknowledged by the µC before a new command is sent • a half bridge receives a direct command, while it is being used to drive a motor. 14 Hardware Error "1" some hardware error has occurred, such as over-current or overtemperature 15 Position Data "1" positioning data is available for reading out 16 reserved read as zero 17 Parity Bit odd parity of first byte => constant "0" or "1" leads to parity error Table: Byte No. 2 and No.3 of TXD Data for Reading Motor Count and Hardware Error Bit No. Motor Position Data Hardware Error Data 20 Address Bit MSB of motor address Over-current 6 "1" OUT6 has been switched off due to over-current 21 Address Bit 2nd Bit of motor address Over-current 5 "1" OUT5 has been switched off due to over-current 22 Address Bit LSB of motor address Over-current 4 "1" OUT4 has been switched off due to over-current ELMOS Semiconductor AG Specification 29 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Bit No. Motor Position Data Hardware Error Data 23 Motor Stall unexpected stop due to motor Over-current 3 stall "1" OUT3 has been switched off due to over-current 24 Position Bit MSB of position counter, 210 Over-current 2 "1" OUT2 has been switched off due to over-current 25 Position Bit 2nd Bit of position counter, 29 Over-current 1 "1" OUT1 has been switched off due to over-current 26 Position Bit 3rd Bit of position counter, 28 Overtemperature. all OUTx pins have been switched into high ohmic state due to overtemperature 27 Position Bit 4th Bit of position counter, 27 Under VBAT all motors are stopped due to overvoltage of VBAT and the count values are stored 30 Position Bit 5th Bit of position counter, 26 Over VBAT all motors are stopped due to undervoltage of VBAT and the count values are stored 31 Position Bit 6th Bit of position counter, 25 Open Loop at least one pin OUTx is not connected externally, “floating“ Position Bit 7th Bit of position counter, 24 Configuration Register Error the configuration register is not or is badly initialised or it is corrupted due to external distortions. Position Bit 8th Bit of position counter, 23 reserved read as zero reserved read as zero reserved read as zero reserved read as zero 32 33 34 35 Position Bit Position Bit th 9 Bit of position counter, 2 2 th 10 Bit of position counter, 2 1 0 36 Position Bit LSB of position counter, 2 37 Parity Bit odd parity of second and third Parity Bit byte odd parity of second and third byte Table: Byte No. 2 and No.3 of TXD Data for Reading Configuration Register 1 and 2 Bit No. Configuration Register 1 Configuration Register 2 20 Gain_Norm[1] MSB of gain of all ripple counters in normal mode NonLin_Norm[1] MSB of nonlinear shape function in normal mode 21 Gain_Norm[0] LSB of gain of all ripple counters in normal mode NonLin_Norm[0] LSB of nonlinear shape function in normal mode 22 Gain_Break[1] MSB of gain of all ripple counters in break mode NonLin_Break[1] MSB of nonlinear shape function in break mode 23 Gain_Break[0] LSB of gain of all ripple counters in break mode NonLin_Break[0] LSB of nonlinear shape function in breakl mode ELMOS Semiconductor AG Specification 30 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Bit No. Configuration Register 1 Configuration Register 2 24 PulsTh_Norm[2] MSB of pulse detector threshold for all ripple counters in normal mode PulsT_Norm[2] MSB of Minimum Pulse Width to be detected as regular pulse in break mode 25 PulsTh_Norm[1] 2nd Bit of pulse detector threshold PulsT_Norm[1] 2nd of Minimum Pulse Width to be detected as regular pulse 26 PulsTh_Norm[0] LSB of pulse detector threshold for all ripple counters in normal mode PulsT_Norm[0] LSB of Minimum Pulse Width to be detected as regular pulse in break mode 27 reserved reserved read as zero 30 PulsTh_Break[2] MSB of pulse detector threshold for all ripple counters in break mode PulsT_Break[2] MSB of Minimum Pulse Width to be detected as regular pulse in break mode 31 PulsTh_Break[1] 2nd Bit of pulse detector threshold PulsT_Break[1] 2nd of Minimum Pulse Width to be detected as regular pulse PulsTh_Break[0] LSB of pulse detector threshold for all ripple 32 counters in break mode PulsT_Break[0] LSB of Minimum Pulse Width to be detected as regular pulse in break mode read as zero TauInc_Norm This bit increases Tau in reserved the high pass of the ripple detector in normal mode by factor 6. read as zero TauInc_Break reserved read as zero 34 This bit increases Tau in the high pass of the ripple detector in break mode by factor 6. 35 reserved read as zero reserved read as zero 36 reserved read as zero reserved read as zero 37 Parity Bit odd parity of second and Parity Bit third byte 33 odd parity of second and third byte 5.2.14 Overtemperature Shut Off When overtemperature is detected, all half bridge outputs will be turned into High-Z state, and the Data Ready flag is set (output DRB goes low). As an indication, the overtemperature bit of byte no. 2 in hardware error mode is set to "1". ELMOS Semiconductor AG Specification 31 / 51 03SP0350E.03 Oct. 24, 2006 910.71 5.2.15 Over / Under Voltage Shut Off In case of overvoltage or under-voltage a moving motor is stopped, the currently counted number of ripples is stored, and the DRB flag is set. Outputs in Half Bridge Control mode switch on again automatically after power supply has gone back into normal operating range. No diagnostic information will be generated. 5.2.16 Open Load Detection Open load detection in Motor Control mode is performed by the internal current threshold Imot_olp (see. 4.3.1), in combination with the stall detection. When the half bridges to drive the motor are turned on, but no ripple pulses are detected for 200 ms, this usually means that the motor is stalled. Motor current thus should be stall current. If in this case the motor current is lower than Imot_olp threshold mentioned above, the interpretation is "Open Load". 5.2.17 Output DRB, Acknowledge of Positioning and Diagnostic Data Data Ready Output pin DRB goes low whenever a required motor position is reached or diagnostic data is available. DRB is reset after the complete set of data has been transmitted via TXD, simultaneously with a valid data telegram received at the input RXD. There are several conditions under which it is not possible to transmit data completely: - Positioning data of more than 1 motor is available - Positioning data is available, but received data telegram is only 1 byte long (Bit 10 is "0", Bit 11 is "1") - New data has become valid after CSB has gone low and transmission has started - Received data telegram has been detected to be corrupted. - The configuration registers are badly/not initialised or corrupted. In any of these cases DRB stays active (low) until data is completely transferred. Positioning data and diagnostic data are reset if they have been successfully transferred to the µC and have been acknowledged by the µC. Acknowledge is performed by setting the Acknowledge Bit (no. 13) to '1'. Pending Error Conditions (like overtemperature) prevent resetting of DRB signal even after acknowledge. If a command is sent from the µC to activate an output that has been shut off, but diagnostic data has not yet been acknowledged, the command will be ignored and DRB is activated again. It is possible to reactivate any output OUTX with the same telegram that contains the acknowledge. 5.2.18 Stand-By Mode Sending stand-by command to the IC switches the device into Stand-by mode. All half bridge outputs are turned into High-Z mode, charge pump and oscillator are switched off, and current consumption in both VDD and VBAT supplies is reduced to < 50 µA each. ELMOS Semiconductor AG Specification 32 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Sending a stand-by command while a motor is running sets the motor into break mode, i.e. both low side drivers are turned on. Ripples are counted until the motor has stopped, and DRB becomes zero. After a time-out of 100 ms Stand-by mode is activated, if in the meantime the µC did not initialise any other activity. It takes a data telegram other than the stand-by or softreset command to get back to normal operation. A delay of “trdy” (see. chapter 4.4.2) is realised to allow the charge pump to power up before any output is activated. After leaving the stand-by mode all half bridges stay in high Z mode, unless they get a activating command from the µC. After power on, the ASIC starts in stand-by mode. 5.2.19 Software Reset The µC can reset all registers of the chip by sending a “Software Reset“ command. It contains address “111“ and Switch Bit '1' in a half bridge control telegram. The decoder is hard-wired and generates a reset signal for all registers. Reset signal remains until the next rising edge of CSB. 5.2.20 Acknowledge All data (diagnostic information or position data) indicated by an active DRB output have to be acknowledged by the µC. The ASIC stores the information, and even though the over-current or overtemperature condition may no longer be present, all data is available until reset by acknowledge. Acknowledging the position of a motor allows the µC to send new positioning data for the same motor with the same SPI protocol . If there is no position data available in the ASIC, in the case of a data transmission to the µC the address is “000“ and the position data is undefined (random). 5.2.21 Daisy Chain Configuration Several Ripple Counter ASICs can be connected in Daisy Chain configuration as shown in Fig. 5.2.21-1. Daisy Chain is used to increase the number of available half bridge to control more than five motors. In fact only the chip select signal CSB is connected in Daisy Chain configuration. All other signal are connected in parallel to all ASICs and the µC. The data ready signal DRB is connected wired-or with external pull-up resistor RPU. ELMOS Semiconductor AG Specification 33 / 51 03SP0350E.03 Oct. 24, 2006 µC Interface 910.71 VDD RPU CSOB DRB TXD RXD CLK ... CSB CSOB DRB TXD RXD CLK CSB CSOB DRB TXD RXD CLK CSB n.c. 910.71 910.71 910.71 6x Half Brigdes 6x Half Brigdes 6x Half Brigdes Figure 5.2.21-1: Daisy Chain Configuration 5.2.22 Examples of Data Transfer from µC to 910.71 and vice versa The following table contains typical commands send to and received from 910.71. Signal on RXD (from µC to 910.71): Command Command hex Command binary Description [10:17] or [10:17] or [10:17,20:27,30:37] [10:17,20:27,30:37] Software Reset 0x4F “0100 1111” Stand-By 0x0E “0000 1110” Wake Up and Read Status 0x01 “0000 0001” Writing Configuration Register 1 gain bits normal=”01” gain bits break=”11” puls threshold=”011” tau_inc bit=”0” Bosch Motor 0x AD 76 61 “1010 1101 0111 0110 0110 0001” Writing Configuration Register 2 nonlin bits normal=”01” nonlin bits break=”11” puls length=”010” Bosch Motor 0x AE 75 40 “1010 1110 0111 0101 0100 0000” Read Hardware Error (Conf. Register Error) 0x A1 01 01 “1010 0001 0000 0001 0000 0001” Acknowledge Hardware Error 0x31 “0011 0001” ELMOS Semiconductor AG Specification 34 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Command Description Command hex [10:17] or [10:17,20:27,30:37] Command binary [10:17] or [10:17,20:27,30:37] Half bridge-Mode OUT1=0 0x02 “0000 0010” Half bridge-Mode OUT1=1 0x43 “0100 0011” Half bridge-Mode OUT2=0 0x04 “0000 0100” Hal fbridge-Mode OUT2=1 0x45 “0100 0101” Motor Controller No. 1: 8 pulses right 0x 83 01 40 “1000 0011 0000 0001 0100 0000” Motor Controller No. 1: 2016 pulses right 0x 83 7F 01 “1000 0011 0111 1111 0000 0001” Motor Controller No. 1: 2016 pulses left 0x 83 FE 01 “1000 0011 1111 1110 0000 0001 Read Command Positioning Data 0x 80 01 01 “1000 0000 0000 0001 0000 0001” Acknowledge Positioning Data 0x10 “0001 0000” 0x 10 “1000 0000” Position Data Available 0x 04 “0000 0100” Position Data of RippleDetector 1 with 13 pulses 0x 04 20 1A “0000 0100 0010 0000 0001 1010” Signal on TXD (from 910.71 to µC): Parity Error on last RXD transfer 5.3 Half Bridge Outputs 5.3.1 Functional Description The IC features six half bridge driver outputs. Switching these drivers on and off is performed by SPI commands (see chapter “Serial Peripheral Interface, SPI”). Using an address scheme as shown in Table 1, the six half bridges can be used to drive 3 DC motors simultaneously, or up to 5 motors sequentially. In case outputs are not needed for DC motor control, they can be used to drive other kinds of loads like as well, such as relays. Each half bridge output features bias-free switching, slew rate control, current limitation and over-current shut off. Any half bridge output is shut off into High-Z mode after current limitation has been continuously detected for a debounce time of typically 10 ms. Output DRB is activated to indicate that diagnostic data is present. A corresponding SPI command has to be sent in order to turn the output on again. A common overtemperature shut off switches all outputs into High-Z mode when a chip temperature of > 150°C has been detected. Output DRB is activated to indicate that diagnostic data is present. After cooling down by typically 20°C, the outputs are ready to be turned on again by an SPI command. ELMOS Semiconductor AG Specification 35 / 51 03SP0350E.03 Oct. 24, 2006 910.71 5.3.2 High-Impedance State of Half Bridge Outputs in Motor Control Mode To brake a motor from movement, and count pulses until it has actually stopped, it is necessary to switch on both low side transistors of the related half bridges. On the other hand to avoid unintended current flow through motors that are not addressed, it is mandatory to switch all half bridges, that are not involved in driving the addressed motor, into High-Impedance (or High-Z) state. Therefore, each pair of half bridges switches back into High-Z state after motor stop has been detected, i.e. 100 ms after the last ripple has been detected in brake mode (both low side transistors on). 5.3.3 Short Circuit to external Battery Supply A diode in the supply line Vbat is recommended for reverse battery protection. Thus the supply voltage of the IC is one diode forward voltage lower than the actual battery voltage. If a short circuit of an output to the battery occurs, the high side transistor will conduct current into the IC's supply if it is turned on. If it is off, current will be conducted by its reverse diode, which is connected in parallel to the external reverse voltage protection diode. A parasitic pnp bipolar transistor will also drive current into the IC's substrate. This current may cause significant power dissipation, and after some time the overtemperature shut off may switch all outputs into High-Z mode. The IC's current consumption from Vbat will go down below 50 µA and the remaining power dissipation caused by the parasitic pnp transistor cannot damage the IC. To achieve this self-protection feature it is important that no additional current is drawn from the IC's battery supply. Therefore it is recommended to use a separate reverse voltage protection diode for the IC. 5.3.4 Driving Loads other than DC Motors Half bridge outputs that are not used for DC motor control may drive other kinds of load such as relays or LEDs, as well. In case of over voltage half bridge outputs are switched to "0", which means low side transistors are switched on. This is to avoid bulk current being induced by inductive loads in case the output has been switched into High-Z mode. Therefore, loads like relays have to be connected to ground and not to battery supply. Due to some parasitic currents that may flow in case of ground shift, it is recommended to use the half bridge outputs only for relays, LEDs, and similar loads that are placed on the same printed circuit board (PCB). Switching an output to high level is performed by setting the corresponding direction bit to “1“, for low level a “0“ has to be transmitted. All functions related to ripple detection are switched off. Protection features for over-current, and overtemperature are the same as in Motor Control mode. Overvoltage leads to shut off (i.e. switch off, low side driver active) of the output after a debounce time of typically 10 ms. But other than in motor control mode, the output will be turned on automatically after the voltage has returned to normal condition, again after the same debounce time. Undervoltage does not switch off the outputs. Both overvoltage and under-voltage do not activate output DRB and no diagnostic information is created. ELMOS Semiconductor AG Specification 36 / 51 03SP0350E.03 Oct. 24, 2006 910.71 5.4 Positioning by means of Ripple Detection 5.4.1 Block Diagram Pulse Detection OUT1 OUT 2 MUX Arbi tration Counter GAIN Sine Wave Detection CLP1 OUT 3 Counter MUX Detection Block 2 OUT 4 CLP 2 GAIN Counter OUT 5 MUX Detection Block 3 OUT 6 CLP 3 GAIN Figure 5.4.1-1: Block-Diagram of Ripple Detection 5.4.2 Functional Description of Ripple Detection Three independent ripple detection blocks are implemented in the IC, as shown in Fig. 5.4.1-1 This allows positioning of three DC motors simultaneously. Connections are: Motor 1 => OUT1/OUT2, Motor 2 => OUT3/OUT4, Motor 3 => OUT5/OUT6. It is also possible to operate up to 5 motors sequentially. Additional motors 4 and 5 are connected to OUT2/OUT3, and OUT4/OUT5, respectively. For this purpose input multiplexers (MUX) of Ripple Detection Blocks 1 and 3 provide selection of 3 half bridges each. ELMOS Semiconductor AG Specification 37 / 51 03SP0350E.03 Oct. 24, 2006 910.71 The current consumption of a DC motor from the supply voltage under constant power and load conditions is not constant, but features an AC component caused by the induced voltages of the motor windings and the current commutation to consecutive windings. The shape of this AC component depends very much on the construction of the motor. A common characteristic is the presence of a periodical signal with a frequency that is defined by the motor speed and the number of rotor windings, equal to the number of commutator segments. If this “n“ is an even number, commutation of the brushes from one commutator segment to the next takes place simultaneously on both brushes. If “n“ is an odd number, commutation occurs alternatingly. Thus the ripple frequency “frip“ of the AC component is given by the following equations: frip = s ∗ n if “n“ is an even number, frip = s ∗ 2n if “n“ is an odd number, where “s“ is the motor speed in revolutions per second. IMot a) High Motor Current IMot b) Medium Motor Current IMot c) Low Motor Current Figure 5.4.2-1: Typical Motor Current under different Load Conditions Fig. 5.4.2-1 shows the typical current shape of a small, symmetrical DC motor with three rotor windings as used in HVAC actuators under different load conditions. It can be interpreted as the superposition of a sequence of inverse sinusoidal "peaks" (from 60° to 120°, i.e. +/- 30° around the amplitude value of the generator voltage), and exponential inrush curves defined by the L-R time constant of the motor windings. ELMOS Semiconductor AG Specification 38 / 51 03SP0350E.03 Oct. 24, 2006 910.71 At the moment of commutation current direction is changed in the winding which is connected to the two consecutive commutator segments involved. This change of direction is delayed due to the winding inductance, which leads to a very rapid current drop on every commutation, visible at high and medium motor currents. When the average motor current becomes very small with even negative momentary values (see Fig. 5.4.2-1 c), this significant drop gets very small, and can even vanish completely. The reason is, that when the motor comes close to generator mode the momentary current during commutation becomes very small or even zero. This condition may occur in an HVAC system when air pressure on the flap is in the same direction as the flap movement. IMot Figure 5.4.2-2: Typical Motor Current during Start When the motor gets started or braked, or when transients on supply voltage or load appear, the average motor current changes rapidly, and these transients can be higher than the ripple signal to be detected. These conditions are shown in Fig. 5.4.2-2 for a motor start as an example. What is still visible under these conditions are the rapid current drops on every commutation. Based on the different signal shapes the ripple detection circuit features two different signal pathes to realise safe recognition under all conditions. One signal path, called pulse detection, reacts on the rapid current drop, while the other signal path, called sine wave detection, reacts on AC components that are more sinusoidally shaped. An arbitration is implemented to avoid interference of the two pathes. Commutation points can only be detected, if the current signal shape fulfil the specification of chapter 4.3.2. I.e. for pulses a maximum fall time tfall, a minimum length tpulsewidth of around tpl(max) and a minimum drop amplitude Idr,neg(max) is necessary. I.e. for sine pulses a maximum sine frequency fsin and a minimum peak peak value Isin,pp(max) is necessary. 5.4.3 Current Measurement Current is measured as voltage drop across the on resistance of a half bridge's low side driver. When the motor brakes, both low side drivers of a full bridge are turned on. The generator voltage of the motor reverses current. So to get a positive voltage for measurement, the detection input is switched to the “other“ transistor. ELMOS Semiconductor AG Specification 39 / 51 03SP0350E.03 Oct. 24, 2006 910.71 It is necessary to adapt the gain of the input amplifier to the current that the specific type of motor draws from the supply. The highest possible gain that does not override the amplifier should be selected. Three different gain settings (low, medium, high) can be selected via SPI. For each motor an individual gain can be chosen in the related ripple detection block. Therefore, different types of motors can be connected to the ASIC. Motor stall current at maximum battery voltage (e.g. 18 V) must not exceed the values given in chapter “Ripple Detection - DC Characteristics”. During normal operation switching into brake mode is only possible immediately after a ripple signal has been detected by either the pulse detection or the sine wave detection. A debounce of typically 1 ms after the rising edge of the digitised signal is implemented in order to avoid multiple pulses caused by commutator noise, as well as unintended counting on the transition from run to brake mode. 5.4.4 Stall Detection If the motor gets stalled no ripple signals are detected. A time-out of typically 200 ms is implemented to switch the motor off, i.e. into brake mode. A diagnostic signal "Motor Stall" is stored and can be read out together with the position information. 5.4.5 Actuator Positioning The four actuator positioning parameters motor address, direction, number of counts and the gain have to be transferred via the SPI. The IC activates the corresponding two half bridges and counts commutation pulses until the required number is reached. The motor will then be braked by activating both low side drivers, still counting commutation pulses. Motor stop is detected when no ripple pulses have occurred for typically 100 ms. After the motor has stopped the output DRB is activated and the actual number of counts can be read back from the SPI. This number will normally be higher than the required one since in brake mode the motor delivers an unpredictable number of additional pulses. This number is relatively small, so there is no reason to try to correct it by moving the motor back. Some compensation can be implemented into the control unit by reducing the required number of counts by an average value derived from statistical tests. Nevertheless, to keep the correct position it is mandatory to consider the real number of counts read back from the SPI. Different fault conditions may occur during motor movement. In case of Vbat over/under-voltage, and motor stall (no ripples for 200 ms), low side switches of both half bridges will be turned on to brake the motor, and no pulses will get lost. Output DRB gets activated and the actual detected number of counts, eventually together with the diagnostic information "Motor Stall", are available via SPI. Over-current as well as overtemperature causes half bridges to be switched into High-Z mode. Pulses that occur during motor run-out will thus not be detected. DRB will be activated and the last number of counts that has been detected is available together with the diagnostic information from which can be seen that the position might be incorrect. 5.5 Test Modes Input pin TMODE, in combination with SPI ports, activates a variety of test modes. The test modes are used in production test to ensure a high quality of the ripple counter IC. The pin TMODE has to be connected to ground for not entering a test mode unintentionally. ELMOS Semiconductor AG Specification 40 / 51 03SP0350E.03 Oct. 24, 2006 910.71 6 Package 6.1 Marking 6.1.1 Top Side Elmos E 910.71A XXX#YWW*@ where E/M/T Volume Production / Prototype / Test Circuit 910.71 ELMOS Project Number A Version # Assembler Code YWW Year and Week of Fabrication * Mask Revision Number @ ELMOS internal Marking 6.1.2 Bottom Side No Marking ELMOS Semiconductor AG Specification 41 / 51 03SP0350E.03 Oct. 24, 2006 910.71 6.2 Package Dimensions 6.2.1 SO28 Package N -BE Index Area H Detail 'B' 1 2 3 h X 45° Detail 'A' L Detail 'B' e A A1 D -C- Mould Parting Line C Seating Plane -A- B Detail 'A' Figure 6.2.1-1: Package Outlines of SO28 The package is compliant to JEDEC MS-013-AE Issue C. ELMOS Semiconductor AG Specification 42 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Description Distance from the seating plane to the highest point of body Distance between the seating plane and the base plane Width of terminal leads, including lead finish Coplanarity lead to lead Thickness of leads measured in a plane perpendicular to the seating plane including lead finish. The longest body dimension measured perpendicular to the body width E The smallest body width dimension Linear spacing between true lead positions which applies over the entire lead length or at the gauge plane Largest overall package width dimension of mounted package Body chamfer angle Length of terminal for soldering to substrate Number of terminal positions Angle of lead mounting area Symbol min mm typ min inch typ max max A - - 2.64 - - .104 A1 0.10 - - .004 - - B 0.36 0.51 .014 - .020 b2 - - 0.10 - - .004 C 0.23 - 0.33 .009 - .013 D 17.73 - 18.13 .598 - .714 E 7.40 - 7.60 .291 - .299 e - 1.27 - - .050 - H 10.11 10.65 .398 h 0.25 - 0.75 .010 - .029 L 0.51 - 1.01 .020 - .040 N a 0° 28 - 8° 0° 28 - 8° .419 Thermal resistances (Θ JA, Θ JC) are described in chapter “Absolute Maximum Ratings”. ELMOS Semiconductor AG Specification 43 / 51 03SP0350E.03 Oct. 24, 2006 910.71 6.2.2 QFN.L32.7x7 / MLFP.L32.7x7 / MLPQ32L7 Package SYMBOL D E D/2 E/2 D2 E2 N ND NE NL NB e A A1 A3 DESCRIPTION = = = = = = = = = = = = = = = BODY SIZE BODY SIZE BODY CENTRE BODY CENTRE EXPOSED DIE-PADDLE SIZE EXPOSED DIE-PADDLE SIZE TOTAL NUMBER OF TERMINALS NUMBER OF TERMINALS, SIDE "D" NUMBER OF TERMINALS, SIDE "E" TERMINAL LENGTH TERMINAL WIDTH TERMINAL PITCH PACKAGE THICKNESS PACKAGE STAND OFF LEADFRAME THICKNESS TYPE TOLERANCE DIMENSION +/-0,1mm 7,0mm +/-0,1mm 7,0mm 3,5mm +/-0,1mm 3,5mm +/-0,1mm 5,45mm +/-0,1mm 5,45mm +/-0,1mm 32 8 8 0,40mm +/-0,08mm 0,30mm +/-0,07mm 0,65mm +/-0,02mm 0,90mm +/-0,1mm 0,02mm +/-0,02mm 0,20mm +/-0,02mm Figure 6.2.2-1: Package Outlines of QFN.L32.7x7 / MLFP.L32.7x7 / MLPQ32L7 The package is compliant to JEDEC MO-220VKKC Issue C. Thermal resistances (Θ JA, Θ JC) are described in chapter “Absolute Maximum Ratings”. ELMOS Semiconductor AG Specification 44 / 51 03SP0350E.03 Oct. 24, 2006 910.71 7 General 7.1 General Information Customer Elmos Internal Address Heinrich-Hertz-Str. 1 Telephone +49 231-7549-0 Telefax E-Mail Technical Contact Erhard Muesch Customer's Project No. Revision ELMOS Project Name 910.71 Package SO28 or QFN.L32.7x7/MLFP.L32.7x7/MLPQ32L7 Process L08HCZQ 7.2 ELMOS Documents QM No.: 07PL0009.XX Elmos Standard Qualifications Plan Design Specification E910.71 7.3 Customer Documents None 7.4 Other Documents None ELMOS Semiconductor AG Specification 45 / 51 03SP0350E.03 Oct. 24, 2006 910.71 8 Quality 8.1.1ESD Protection Circuit ESD protection circuits are shown in chapter „Pin Description“. 8.1.2ESD Sensitivity Classification Test Method The ESD Protection circuitry is measured using MIL-STD-883C Method 3015 (Human Body Model) with following condition : Pins Conditions All Pins VIN = 2000V REXT = 1500 Ohm CEXT = 100 pF ESD conditions 8.1 Latch-up tbd. mA positive and negative pulses at room temperature according to JEDEC-17 into pins OUT1 - OUT6 100 mA positive and negative pulses at room temperature according to JEDEC-17 into all other pins. 9 Reliability 10 Storage, Handling, Packaging, and Shipping ELMOS Semiconductor AG Specification 46 / 51 03SP0350E.03 Oct. 24, 2006 910.71 11 Record of Revisions Chapter Rev. Change and Reason for Change Date Released ELMOS Customer - all 00 New Document 04.10.2005 E. Muesch 1.2 01 Pin names of pin out QFN.L32 7x7 in Fig. 1.2-2 from pin 13 to 16 corrected 15.11.2005 RUA all 02 All chapters modified 27.06.2006 RUA 5.1.20 03 replaced “... non-linearity is reduced by 50%.” with “... non-linearity is reduced.” 03.07.2006 RUA 4.2.1 03 Leakage Current only against VOUT= 0V, so with loads to ground 25.07.2006 RUA 4 03 Correction of limits of electrical parameters 24.10.2006 RUA ELMOS Semiconductor AG Specification 47 / 51 03SP0350E.03 Oct. 24, 2006 910.71 12 Index Table of Content 1 Pinout............................................................................................................................................................3 1.1 Pin Description......................................................................................................................................3 1.2 Package Pinout.....................................................................................................................................6 2 Block Diagram...............................................................................................................................................8 3 Operating Conditions....................................................................................................................................9 3.1 Absolute Maximum Ratings..................................................................................................................9 3.2 Recommended Operating Conditions................................................................................................11 4 Detailed Electrical Specification..................................................................................................................12 4.1 Supply Section....................................................................................................................................12 4.1.1 DC Characteristics Battery Supply.............................................................................................12 4.1.2 AC Characteristics Battery Supply..............................................................................................12 4.1.3 DC Characteristics Digital/Analog Supply...................................................................................13 4.1.4 Overtemperature Shut Off..........................................................................................................13 4.2 Motor Driver Half Bridges...................................................................................................................13 4.2.1 DC Characteristics Outputs OUT1 - OUT6................................................................................13 4.2.2 AC Characteristics Outputs OUT1 - OUT6................................................................................ 14 4.2.3 DC Characteristics Charge Pump..............................................................................................15 4.3 Ripple Detection..................................................................................................................................15 4.3.1 DC Characteristics Gain of Input Amplifier................................................................................15 4.3.2 AC Characteristics Conditions for Pulse Shapes......................................................................16 4.4 Serial Peripheral Interface, SPI..........................................................................................................18 4.4.1 DC Characteristics I/O Pins........................................................................................................18 4.4.2 AC Characteristics I/O Pins.......................................................................................................19 5 Functional Description................................................................................................................................20 5.1 Supply Section....................................................................................................................................20 5.1.1 Functional Description................................................................................................................20 5.2 Serial Peripheral Interface, SPI..........................................................................................................20 5.2.1 Functional Description................................................................................................................21 5.2.2 Data received from µC, Input RXD.............................................................................................22 5.2.3 Data Telegram Supervision........................................................................................................26 5.2.4 Simultaneous and/or Sequential Motor Control..........................................................................26 5.2.5 Selection Bit 10, Combination of Motor Control and Half Bridge Control...................................26 5.2.6 Motor Stop Bit 11 .......................................................................................................................27 5.2.7 Gain Bits ....................................................................................................................................27 5.2.8 Pulse Threshold Bits...................................................................................................................27 5.2.9 Pulse Length Bits........................................................................................................................27 5.2.10 Nonlinearity Shape Function of Nonlinear Amplifier.................................................................28 5.2.11 Tau Increase Bit.......................................................................................................................28 5.2.12 Recommended Configuration for Different Type of DC Motors............................................... 28 5.2.13 Data sent to µC, Output TXD...................................................................................................29 ELMOS Semiconductor AG Specification 48 / 51 03SP0350E.03 Oct. 24, 2006 910.71 5.2.14 Overtemperature Shut Off........................................................................................................31 5.2.15 Over / Under Voltage Shut Off..................................................................................................32 5.2.16 Open Load Detection................................................................................................................32 5.2.17 Output DRB, Acknowledge of Positioning and Diagnostic Data...............................................32 5.2.18 Stand-By Mode.........................................................................................................................32 5.2.19 Software Reset.........................................................................................................................33 5.2.20 Acknowledge............................................................................................................................33 5.2.21 Daisy Chain Configuration........................................................................................................33 5.2.22 Examples of Data Transfer from µC to 910.71 and vice versa...............................................34 5.3 Half Bridge Outputs............................................................................................................................35 5.3.1 Functional Description................................................................................................................35 5.3.2 High-Impedance State of Half Bridge Outputs in Motor Control Mode...................................... 36 5.3.3 Short Circuit to external Battery Supply......................................................................................36 5.3.4 Driving Loads other than DC Motors..........................................................................................36 5.4 Positioning by means of Ripple Detection..........................................................................................37 5.4.1 Block Diagram............................................................................................................................37 5.4.2 Functional Description of Ripple Detection.................................................................................37 5.4.3 Current Measurement.................................................................................................................39 5.4.4 Stall Detection.............................................................................................................................40 5.4.5 Actuator Positioning....................................................................................................................40 5.5 Test Modes.........................................................................................................................................40 6 Package......................................................................................................................................................41 6.1 Marking...............................................................................................................................................41 6.1.1 Top Side.....................................................................................................................................41 6.1.2 Bottom Side................................................................................................................................41 6.2 Package Dimensions..........................................................................................................................42 6.2.1 SO28 Package...........................................................................................................................42 6.2.2 QFN.L32.7x7 / MLFP.L32.7x7 / MLPQ32L7 Package............................................................... 44 7 General.......................................................................................................................................................45 7.1 General Information............................................................................................................................45 7.2 ELMOS Documents............................................................................................................................45 7.3 Customer Documents.........................................................................................................................45 7.4 Other Documents................................................................................................................................45 8 Quality.........................................................................................................................................................46 8.1.1ESD Protection Circuit.................................................................................................................46 8.1.2ESD Sensitivity Classification Test Method.................................................................................46 8.1 Latch-up..............................................................................................................................................46 9 Reliability.....................................................................................................................................................46 10 Storage, Handling, Packaging, and Shipping...........................................................................................46 11 Record of Revisions..................................................................................................................................47 12 Index.........................................................................................................................................................48 13 Approvals..................................................................................................................................................52 ELMOS Semiconductor AG Specification 49 / 51 03SP0350E.03 Oct. 24, 2006 910.71 Table of Figures Figure 1: Application Circuit for SO28..............................................................................................................2 Figure 1.2-1: Pinout SO28...............................................................................................................................6 Figure 1.2-2: Pinout QFN.L32.7x7/ MLFP.L32.7x7 / MLPQ32L7....................................................................7 Figure 2-1: Block Diagram...............................................................................................................................8 Figure 5.2.1-1: SPI Timing for 1-Byte Transfer: Transmission starts with CSB. On rising edge of CLK (driven by µC) the transfer data RXD and TXD are valid and can be sampled.............................................21 Figure 5.2.21-1: Daisy Chain Configuration...................................................................................................34 Figure 5.4.1-1: Block-Diagram of Ripple Detection.......................................................................................37 Figure 5.4.2-1: Typical Motor Current under different Load Conditions........................................................ 38 Figure 5.4.2-2: Typical Motor Current during Start........................................................................................39 Figure 6.2.1-1: Package Outlines of SO28....................................................................................................42 Figure 6.2.2-1: Package Outlines of QFN.L32.7x7 / MLFP.L32.7x7 / MLPQ32L7........................................44 ELMOS Semiconductor AG Specification 50 / 51 03SP0350E.03 Oct. 24, 2006 910.71 13 Approvals Customer Part No.: ”E 910.71 DC Motor Controller with Ripple Detection” Customer: Name: Title: Date / Sign: ELMOS: Name: Erhard Muesch Title: VP Product Development Date / Sign: Jan. 16, 2006 ELMOS Semiconductor AG Specification 51 / 51 03SP0350E.03 Oct. 24, 2006