Technical Data Sheet

STP08DP05
Low voltage 8-bit constant current LED sink with full outputs error
detection
Datasheet - production data
serial-in, parallel-out shift register that feeds a 8bitD-type storage register. In the output stage,
eight regulated current sources were designed to
provide 5-100 mA constant current to drive the
LEDs.
DIP-16
TSSOP16
(Exposed pad)
TSSOP16
The STP08DP05 is backward compatible in the
functionality and footprint with STP8C/L596 and
extends its functionality with open and short
detection on the outputs. The detection circuit
checks 3 different conditions that can occur on
the output line: short to GND, short to VO or open
line. The data detection results are loaded in the
shift register and shifted out via the serial line
output.
SO-16
Features
• Low voltage power supply down to 3 V
• 8 constant current output channels
• Adjustable output current through external
resistor
• Short and open output error detection
• Serial data IN/parallel data OUT
• 3.3 V micro driver-able
• Output current: 5-100 mA
• 30 MHz clock frequency
• Available in high thermal efficiency TSSOP
exposed pad
• ESD protection 2.5 kV HBM, 200 V MM
Description
The detection functionality is implemented without
increasing the pin number, through a secondary
function of the output enable and latch pin (DM1
and DM2 respectively), a dedicated logic
sequence allows the device to enter or leave from
detection mode. Through an external resistor,
users can adjust the STP08DP05 output current,
controlling in this way the light intensity of LEDs,
in addition, user can adjust LED’s brightness
intensity from 0% to 100% via OE/DM2 pin.
The STP08DP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high clock frequency,
30 MHz, also satisfies the system requirement of
high volume data transmission. The 3.3 V of
voltage supply is well useful for applications that
interface any micro from 3.3 V. Compared with a
standard TSSOP package, the TSSOP exposed
pad increases heat dissipation capability by a 2.5
factor.
The STP08DP05 is a monolithic, low voltage, low
current power 8-bit shift register designed for LED
panel displays. The STP08DP05 contains a 8-bit
Table 1. Device summary
Order codes
Package
Packaging
STP08DP05B1R
DIP-16
25 parts per tube
STP08DP05MTR
SO-16 (Tape and reel)
2500 parts per reel
STP08DP05TTR
TSSOP16 (Tape and reel)
2500 parts per reel
STP08DP05XTTR
TSSOP16 exposed-pad (Tape and reel)
2500 parts per reel
July 2013
This is information on a product in full production.
DocID13405 Rev 5
1/34
www.st.com
Contents
STP08DP05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7
Truth table and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.1
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.2
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10
Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1
Phase one: “entering in detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2
Phase two: “error detection“ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10.3
Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.4
Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
12
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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STP08DP05
1
Summary description
Summary description
Table 2. Typical current accuracy
Current accuracy
Output voltage
Output current
Between bits
Between ICs
±1.5%
±5%
≥1.3 V
1.1
20 to 100 mA
Pin connection and description
Figure 1. Connections diagram
Note:
The exposed pad should be electrically connected to a metal land electrically isolated or
connected to ground.
Table 3. Pin description
Pin n°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal
4
LE/DM1
Latch input terminal
5-12
OUT 0-7
Output terminal
13
OE/DM2
Output enable input terminal (active low)
14
SDO
15
R-EXT
16
VDD
Serial data out terminal
Constant current programming
5 V supply voltage terminal
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34
Block diagram
2
STP08DP05
Block diagram
Figure 2. Normal mode - block diagram
4/34
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STP08DP05
3
Maximum rating
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
3.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol
3.2
Parameter
Value
Unit
0 to 7
V
VDD
Supply voltage IGND
VO
Output voltage
-0.5 to 20
V
IO
Output current
100
mA
IGND
GND terminal current
800
mA
fCLK
Clock frequency
50
MHz
TOPR
Operating temperature range
-40 to +125
°C
TSTG
Storage temperature range
-55 to +150
°C
Thermal data
Table 5. Thermal data
Symbol
Parameter
RthJA
Thermal resistance junction-ambient
DIP-16 SO-16 TSSOP-16
90
125
140
TSSOP-16 (1)
(exposed pad)
Unit
37.5
°C/W
1. The exposed-pad should be soldered to the PBC to realize the thermal benefits
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34
Maximum rating
3.3
STP08DP05
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
3.0
-
5.5
V
-
20
V
-
100
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SERIAL-OUT
-
+1
mA
IOL
Output current
SERIAL-OUT
-
-1
mA
VIH
Input voltage
0.7VDD
-
VDD+0.3
V
VIL
Input voltage
-0.3
-
0.3VDD
V
5
twLAT
LE/DM1 pulse width
20
-
ns
twCLK
CLK pulse width
20
-
ns
twEN
OE/DM2 pulse width
200
-
ns
7
-
ns
4
-
ns
15
-
ns
tSETUP(D) Setup time for DATA
VDD = 3.0 to 5.0V
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
fCLK
Clock frequency
Cascade operation
(1)
-
30
MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please
consider the timings carefully.
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STP08DP05
4
Electrical characteristics
Electrical characteristics
VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.
Table 7. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIH
Input voltage high level
0.7 VDD
VDD
V
VIL
Input voltage low level
GND
0.3 VDD
V
IOH
Output leakage current
VOH = 20 V
0.5
10
μA
VOL
Output voltage
(Serial-OUT)
IOL = 1 mA
0.03
0.4
V
VOH
Output voltage
(Serial-OUT)
IOH = -1 mA
VOH - VDD =- 0.4V
V
VO = 0.3 V, Rext = 3.9 kΩ
4.25
5
5.75
VO = 0.3 V, Rext = 970 Ω
19
20
21
VO = 1.3 V, Rext = 190 Ω
96
100
104
VO = 0.3 VREXT = 3.9 kΩ
±5
±8
VO = 0.3 VREXT = 970 Ω
± 1.5
±3
VO = 1.3 VREXT =190 Ω
± 1.2
±3
150
300
600
kΩ
100
200
400
kΩ
REXT = 980
OUT 0 to 7 = OFF
4
5
IDD(OFF2)
REXT = 250
OUT 0 to 7 = OFF
11.2
13.5
IDD(ON1)
REXT = 980
OUT 0 to 7 = ON
4.5
5
REXT = 250
OUT 0 to 7 = ON
11.7
13.5
IOL1
IOL2
Output current
IOL3
ΔIOL1
ΔIOL2
ΔIOL3
RSIN(up)
Output current error
between bit
(All Output ON)
Pull-up resistor
RSIN(down) Pull-down resistor
IDD(OFF1)
mA
%
Supply current (OFF)
mA
Supply current (ON)
IDD(ON2)
Thermal
Thermal protection (1)
170
°C
1. Guaranteed by design (not tested)
The thermal protection switches OFF only the outputs current
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34
Switching characteristics
5
STP08DP05
Switching characteristics
VDD = 5 V, T = 25 °C, unless otherwise specified.
Table 8. Switching characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Propagation delay time,
CLK-OUTn, LE\DM1 = H,
OE\DM2 = L
VDD = 3.3 V
36
46.8
tPLH1
VDD = 5 V
19
24.7
Propagation delay time,
LE\DM1 -OUTn,
OE\DM2 = L
VDD = 3.3 V
38
49.4
tPLH2
VDD = 5 V
21
27.3
Propagation delay time,
OE\DM2-OUTn,
LE\DM1 = H
VDD = 3.3 V
42
54
tPLH3
VDD = 5 V
23
30
Propagation delay time,
CLK-SDO
VDD = 3.3 V
22
28.6
tPLH
VDD = 5 V
18
23.4
Propagation delay time,
CLK-OUTn, LE\DM1 = H,
OE\DM2 = L
VDD = 3.3 V
9
11.7
tPHL1
VDD = 5 V
5
6.5
Propagation delay time,
LE\DM1 -OUTn,
OE\DM2 = L
VDD = 3.3 V
4
5.2
tPHL2
VDD = 5 V
3
3.9
Propagation delay time,
OE\DM2-OUTn,
LE\DM1 = H
VDD = 3.3 V
6
7.8
tPHL3
VDD = 5 V
3
3.9
Propagation delay time,
CLK-SDO
VDD = 3.3 V
25
32.5
tPHL
VDD = 5 V
20
26
Output rise time
10~90% of voltage
waveform
VDD = 3.3 V
30
39
tON
VDD = 5 V
15
19.5
Output fall time
90~10% of voltage
waveform
VDD = 3.3 V
7
9.1
tOFF
VDD = 5 V
6
7.8
tr
tf
ns
ns
ns
VDD = 3.3 V
VIL = GND
IO = 20 mA
REXT = 1 KΩ
VIH = VDD
CL = 10pF
VL = 3.0 V
RL = 60 Ω
ns
ns
ns
ns
ns
(1)
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
8/34
ns
ns
CLK rise time (1)
CLK fall time
Unit
DocID13405 Rev 5
5000
ns
5000
ns
STP08DP05
6
Equivalent circuit and outputs
Equivalent circuit and outputs
Figure 3. OE/DM2 terminal
Figure 4. LE/DM1 terminal
Figure 5. CLK, SDI terminal
Figure 6. SDO terminal
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Truth table and timing diagram
STP08DP05
7
Truth table and timing diagram
7.1
Truth table
Table 9. Truth table
Clock
LE/DM1
OE/DM2
SDI
OUT0 ........ OUT0 ........ OUT7
SDO
H
L
Dn
Dn ..... Dn -5 ..... Dn -7
Dn -7
L
L
Dn + 1
No change
Dn -7
H
L
Dn + 2
Dn +2 ..... Dn -3 ..... Dn -5
Dn -5
X
L
Dn + 3
Dn +2 ..... Dn -3 ..... Dn -5
Dn -5
X
H
Dn + 3
OFF
Dn -5
Note:
OUT0 to OUT7 = ON when Dn = H; OUT0 to OUT7 = OFF when Dn = L.
7.2
Timing diagram
Figure 7. Timing diagram - normal mode
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STP08DP05
Truth table and timing diagram
Figure 8. Clock, serial-in, serial-out
Figure 9. Clock, serial-in, latch, enable, outputs
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Truth table and timing diagram
STP08DP05
Figure 10. Outputs
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STP08DP05
8
Typical characteristics
Typical characteristics
Figure 11. Output current-REXT resistor
TA = 25 °C, Vdrop = 0.3 V; 1.2 V, Iset = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 80 mA, Max
Table 10. Output current-REXT resistor
Note:
Output current (mA)
3
5
10
20
50
80
130
Rext (Ω)
6740
3930
1913
963
386
241
124
Maximum output current capabilities setting was 130 mA applying a Rext = 124 Ω
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34
Typical characteristics
STP08DP05
Figure 12. ISET vs drop out voltage (VDROP)
910
810
Vdrop (mV)
710
610
Vdd 5.0V
Vdd 3.0V
510
410
310
210
110
10
0
10
20
30
40
50
60
70
80
90
100 110
Iset (mA)
Table 11. ISET vs drop out voltage (VDROP)
Vdd
(V)
3
5
14/34
I set
(mA)
Rext
(Ω)
Vdrop min
(mV)
Vdrop max
(mV)
Vdrop AVG
(mV)
3
6470
30.6
31.2
30.93
5
3930
46.5
52.9
48.63
10
1910
80.9
100
82.26
20
963
150
161
157
50
386
392
396
394.3
80
241
636
646
640.3
100
192
846
850
848
3
6470
25.6
29
26.96
5
3930
40.8
41.7
41.16
10
1910
80.1
105
89.2
20
963
153
154
154
50
386
379
386
382
80
241
618
626
621
100
192
825
830
827
DocID13405 Rev 5
STP08DP05
Typical characteristics
Figure 13. Power dissipation vs temperature package
Note:
The exposed-pad should be soldered to the PBC to realize the thermal benefits.
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34
Test circuit
9
STP08DP05
Test circuit
Figure 14. DC characteristics
Figure 15. AC characteristics
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STP08DP05
Test circuit
Figure 16. Timing example for open and/or short detection
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34
Detection mode functionality
STP08DP05
10
Detection mode functionality
10.1
Phase one: “entering in detection mode“
From the “normal mode” condition the device can switch to the “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins as showed in the following table and diagram:
Table 12. Entering in detection truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 17. Entering in detection timing diagram
After these five CLK cycles the device goes into the “error detection mode” and at the 6th
rise front of CLK the SDI data are ready for the sampling.
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STP08DP05
10.2
Detection mode functionality
Phase two: “error detection“
The eight data bits must be set “1” in order to set ON all the outputs during the detection.
The data are latched by LE/DM1 and after that the outputs are ready for the detection
process. When the micro controller switches the OE/DM2 to LOW, the device drives the
LEDs in order to analyze if an OPEN or SHORT condition has occurred.
Figure 18. Detection diagram
The LEDs status will be detected at least in 1 microsecond and after this time the
microcontroller sets OE\DM2 in HIGH state and the output data detection result will go to the
microprocessor via SDO.
Detection mode and normal mode use both the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status the device must go back in normal mode and reentering in error detection mode.
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34
Detection mode functionality
10.3
STP08DP05
Phase three: “resuming to normal mode”
The sequence for re-entering in normal mode is showed in the following table and diagram:
Table 13. Resuming to normal mode timing diagram
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
Figure 19. Resuming to normal mode timing diagram
Note:
20/34
For proper device operation the “entering in detection” sequence must be follow by a
“resume mode” sequence, isn’t possible to insert consecutive equal sequence.
DocID13405 Rev 5
STP08DP05
10.4
Detection mode functionality
Error detection conditions
VDD = 3.3 to 5 V temperature range 25 °C.
Table 14. Detection condition
Note:
SW-1 or SW-3b
Open line or output
No error
==> IODEC ≤ 0.5 x IO
short to GND detected
detected
==> IODEC ≥ 0.5 x IO
SW-2 or SW-3a
Short on LED or short
==> VO ≥ 2.5V
to V-LED detected
==> VO ≤ 2.2 V
No error
detected
Where: IO = the output current programmed by the REXT,
IODEC = the detected output current in detection mode.
Figure 20. Detection circuit
16
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Package mechanical data
11
STP08DP05
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 15. DIP16 mechanical data
mm
Dim.
Min.
a1
0.51
B
0.77
Typ.
1.65
b
0.5
b1
0.25
D
20
E
8.5
e
2.54
e3
17.78
F
7.1
I
5.1
L
3.3
Z
22/34
Max.
1.27
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STP08DP05
Package mechanical data
Figure 21. DIP16 drawing
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34
Package mechanical data
STP08DP05
Table 16. HTSSOP16 exposed pad mechanical data
(mm)
Dim.
Min.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
4.90
5.00
5.10
D1
2.8
3
3.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
2.8
3
3.2
e
L
k
1.00
1.05
0.65
0.45
L1
0.60
0.75
1.00
0.00
aaa
24/34
Typ.
8.00
0.10
DocID13405 Rev 5
STP08DP05
Package mechanical data
Figure 22. HTSSOP16 exposed pad drawing
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34
Package mechanical data
STP08DP05
Table 17. HTSSOP16 mechanical data
(mm)
Dim.
Min.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
4.90
5.00
5.10
D1
2.8
3
3.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
2.8
3
3.2
e
L
k
1.00
1.05
0.65
0.45
L1
0.60
0.75
1.00
0.00
aaa
26/34
Typ.
8.00
0.10
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STP08DP05
Package mechanical data
Figure 23. HTSSOP16 mechanical drawing
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34
Package mechanical data
STP08DP05
Table 18. SO16N dimensions
mm
Dim.
Min.
Typ.
A
1.75
A1
0.10
0.25
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
9.80
9.90
10.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
1.27
h
0.25
0.50
L
0.40
1.27
k
0
8°
ccc
28/34
Max.
0.10
DocID13405 Rev 5
STP08DP05
Package mechanical data
Figure 24. Package drawing
0016020_F
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34
Package mechanical data
STP08DP05
Figure 25. Recommended footprint (dimensions are in mm)
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STP08DP05
12
Packaging mechanical data
Packaging mechanical data
Table 19. HTSSOP16 EP tape and reel mechanical data
(mm)
Dim.
Min.
A
Typ.
Max.
330
C
12.8
D
20.2
N
60
T
13.2
22.4
Ao
6.7
6.9
Bo
5.3
5.5
Ko
1.6
1.8
Po
3.9
4.1
P
7.9
8.1
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Packaging mechanical data
STP08DP05
Figure 26. Tape and reel for HTSSOP16 EP
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STP08DP05
13
Revision history
Revision history
Table 20. Document revision history
Date
Revision
Changes
3-Apr-2007
1
First release
21-May-2007
2
Updated Table 7 on page 7
08-Aug-2008
3
Updated Section 8: Typical characteristics on page 13 added
Figure 12 and Figure 11 on page 14 updated Figure 13 on
page 15
22-Oct-2009
4
Updated Note: on page 3
29-Jul-2013
5
Updated Section 11: Package mechanical data, Figure 3:
OE/DM2 terminal and Figure 4: LE/DM1 terminal.
Added Section 12: Packaging mechanical data.
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