STP16DPPS05 - STMicroelectronics

STP16DPPS05
Low voltage 16-bit constant current LED sink driver with output error
detection and auto power-saving
Datasheet - production data
SO-24
QSOP-24
TSSOP24
TSSOP24
(exposed pad)
Features
• Low voltage power supply down to 3 V
• 16 constant current output channels
• Adjustable output current through external
resistor
• Short and open output error detection
• Serial data IN/parallel data OUT
• Auto power-saving
• 3.3 V MCU-driving capability
• Output current: 3 to 40 mA
• 30 MHz clock frequency
• Available in high thermal efficiency TSSOP
exposed pad
• ESD protection: 2 kV HBM, 200 V MM
Description
LED panel displays. The device features a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the output stage,
sixteen regulated current sources are designed to
provide 3 to 40 mA of constant current to drive the
LEDs. The STP16DPPS05 features open and
short LED detection on the outputs. The detection
circuit checks for 3 different conditions that can
occur on the output line: short to GND, short to VO
or open line. The data detection results are
loaded in the shift registers and shifted out via the
serial line output. The detection functionality is
implemented without increasing the pin count,
through a secondary function of the output enable
and latch pin (DM1 and DM2 respectively). A
dedicated logic sequence allows the device to
enter or exit from detection mode. The
STP16DPPS05 output current can be adjusted
through an external resistor to control the light
intensity of the LEDs. LED brightness is
adjustable from 0% to 100% via the OE/DM2 pin.
The auto power-shutdown and auto power-ON
feature allows the device to save power with no
external intervention. The STP16DPPS05
guarantees a 20 V output driving capability,
allowing users to connect more LEDs in series.
The high 30 MHz clock frequency makes the
device suitable for high data rate transmission.
The 3.3 V supply is well suited for applications
which interface a 3.3 V MCU. Compared to a
standard TSSOP package, the TSSOP with
exposed pad increases heat dissipation capability
by a factor of 2.5
The STP16DPPS05 is a monolithic, low voltage,
low current power 16-bit shift register designed for
Table 1. Device summary
Order codes
Package
Packaging
STP16DPPS05MTR
SO-24 (tape and reel)
1000 parts per reel
STP16DPPS05TTR
TSSOP24 (tape and reel)
2500 parts per reel
STP16DPPS05XTTR
TSSOP24 exposed pad
(tape and reel)
2500 parts per reel
STP16DPPS05PTR
QSOP-24
2500 parts per reel
June 2014
This is information on a product in full production.
DocID15817 Rev 3
1/35
www.st.com
Contents
STP16DPPS05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
2
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Error detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1
Phase one: entering error detection mode . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2
Phase two: error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3
Phase three: resuming normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4
Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5
Auto power-saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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STP16DPPS05
1
Summary description
Summary description
Table 2. Typical current accuracy
Current accuracy
Output voltage
≥ 1.3 V
1.1
Between bits
Between ICs
± 1%
± 2%
Output current
VDD
Temperature
5 to 40 mA
3.3 V to 5 V
25 °C
Pin connection and description
Figure 1. Pin connection
Note:
The exposed pad should be electrically connected to a metal land electrically isolated or
connected to ground.
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35
Summary description
STP16DPPS05
Table 3. Pin description
4/35
Pin n°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal
4
LE/DM1
5-20
OUT 0-15
Output terminal
21
OE/DM2
Input terminal of output enable (active low) - detect mode 1
(see operation principle)
22
SDO
23
R-EXT
24
VDD
Latch input terminal - detect mode 1 (see operation principle)
Serial data out terminal
Input terminal for an external resistor for constant current
programming
Supply voltage terminal
DocID15817 Rev 3
STP16DPPS05
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other condition above those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
50
mA
VI
Input voltage
-0.4 to VDD
V
IGND
GND terminal current
800
mA
fCLK
Clock frequency
50
MHz
-40 to +170
°C
Value
Unit
Operating free-air temperature range
-40 to +125
°C
Operating thermal junction temperature range
-40 to +150
°C
Storage temperature range
-55 to +150
°C
SO-24
42.7
°C/W
TSSOP24
55
°C/W
37.5
°C/W
55
°C/W
TJ
Junction temperature range (1)
1. Such absolute value is based on the thermal shutdown protection.
2.2
Thermal data
Table 5. Thermal data
Symbol
TA
TJ-OPR
TSTG
RthJA
Parameter
Thermal resistance junctionambient (1)
TSSOP24(2)
Exposed Pad
QSOP-24
1. According with JEDEC standard 51-7B
2. The exposed pad should be soldered directly to the PCB to obtain the thermal benefits.
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35
Electrical ratings
2.3
STP16DPPS05
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
3.0
-
5.5
V
-
20
V
-
40
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SERIAL-OUT
-
+1
mA
IOL
Output current
SERIAL-OUT
-
-1
mA
VIH
Input voltage
0.7 VDD
-
VDD
V
VIL
Input voltage
-0.3
-
0.3 VDD
V
3
twLAT
LE/DM1 pulse width
20
-
ns
twCLK
CLK pulse width
10
-
ns
twEN
OE/DM2 pulse width
100
-
ns
8
-
ns
5
-
ns
8
-
ns
tSETUP(D) Setup time for DATA
VDD = 3.0 V to 5.0 V
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
fCLK
Clock frequency
Cascade operation
(1)
-
30
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer.
Please consider the timings carefully.
6/35
DocID15817 Rev 3
MHz
STP16DPPS05
3
Electrical characteristics
Electrical characteristics
VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.
Table 7. Electrical characteristics
Symbol
Parameter
Test conditions
VIH
Input voltage high level
VIL
Input voltage low level
IOH
Output leakage current
VOL
VOH
Max.
Unit
0.7 VDD
VDD
V
GND
0.3 VDD
V
VOH = 20 V
1
μA
Output voltage
(serial-OUT)
IOL = 1 mA
0.4
V
Output voltage
(serial-OUT)
IOH = -1 mA
IOL1
Min.
Typ.
VDD-0.4V
V
VO = 0.3 V, Rext = 4 kΩ
4.75
5
5.25
VO = 0.3 V, Rext = 1 kΩ
19
20
21
VO = 1.3 V, Rext = 497 Ω
38
40
42
VO = 0.3 V, IO = 5 mA
REXT = 4 kΩ
±1
±5
VO = 0.3 V, IO = 20 mA
REXT = 980 Ω
± 0.5
±3
VO = 1.3 V, IO = 40 mA
REXT = 490 Ω
± 0.5
±3
150
300
600
kΩ
100
200
400
kΩ
REXT = 1 kΩ,
IOUT = 20 mA,
OUT 0 to 15 = OFF
5.4
7.5
IDD(OFF2)
REXT = 497 Ω,
IOUT = 40 mA OUT 0 to
15 = OFF
8.0
9.5
IDD(ON1)
REXT = 1 kΩ,
IOUT = 20 mA,
OUT 0 to 15 = ON
5.5
7.5
REXT = 497 Ω,
IOUT = 40 mA OUT 0 to
15 = ON
8.1
9.5
IOL2
Output current
IOL3
ΔIOL1
ΔIOL2
Output current error
between bit
(All output ON)
ΔIOL3
RSIN(up)
Pull-up resistor
RSIN(down) Pull-down resistor
IDD(OFF1)
Supply current (OFF)
mA
%
mA
Supply current (ON)
IDD(ON2)
Thermal
Thermal protection
170
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°C
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35
Electrical characteristics
STP16DPPS05
VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.
Table 8. Switching characteristics
Symbol
Parameter
Test conditions
Min
Typ
Max
53.5
86.5
Propagation delay time,
CLK-OUTn, LE/DM1 = H,
OE/DM2 = L
VDD = 3.3 V
tPLH1
VDD = 5 V
32
46.5
Propagation delay time,
LE/DM1-OUTn,
OE/DM2 = L
VDD = 3.3 V
48
75.5
tPLH2
VDD = 5 V
30
43
Propagation delay time,
OE/DM2-OUTn, LE = H
VDD = 3.3 V
71.5
118
tPLH3
43
62
Propagation delay time,
CLK-SDO
VDD = 3.3 V
15
21
31
tPLH
VDD = 5 V
11
15
21
Propagation delay time,
CLK-OUTn, LE/DM1 = H,
OE/DM2 = L
VDD = 3.3 V
27.5
39
tPHL1
22
30.5
11.5
17.5
tPHL2
Propagation delay time,
LE/DM1-OUTn,
OE/DM2 = L
VDD = 5 V
8
11.5
Propagation delay time,
OE/DM2-OUTn,
LE/DM1 = H
VDD = 3.3 V
24
33.5
tPHL3
VDD = 5 V
21
28.5
Propagation delay time,
CLK-SDO
VDD = 3.3 V
17.5
24
36
tPHL
VDD = 5 V
12.5
17
25
Output rise time
10~90% of voltage
waveform
VDD = 3.3 V
29
54
tON
VDD = 5 V
10
17
Output fall time
90~10% of voltage
waveform
VDD = 3.3 V
4.5
6
tOFF
VDD = 5 V
3.5
5
tr
tf
ns
ns
VIH = VDD
VIL = GND
IO = 20 mA
REXT = 1 KΩ
ns
ns
CL = 10 pF
VL = 3.0 V
RL = 60 Ω
VDD = 5 V
VDD = 3.3 V
ns
ns
ns
ns
ns
(1)
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
8/35
ns
VDD = 5 V
CLK rise time (1)
CLK fall time
Unit
DocID15817 Rev 3
5000
ns
5000
ns
STP16DPPS05
4
Equivalent circuit and outputs
Equivalent circuit and outputs
Figure 2. OE/DM2 terminal
Figure 3. LE/DM1 terminal
Figure 4. CLK, SDI terminal
DocID15817 Rev 3
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35
Equivalent circuit and outputs
STP16DPPS05
Figure 5. SDO terminal
Figure 6. Block diagram
%.
& %.
10/35
DocID15817 Rev 3
STP16DPPS05
5
Timing diagrams
Timing diagrams
Table 9. Truth table
CLOCK
Note:
LE/DM1
OE/DM2
SERIAL-IN
OUT0 ............. OUT7 ................ OUT15
SDO
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
Dn - 15
L
L
Dn + 1
No change
Dn - 14
H
L
Dn + 2
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
X
H
Dn + 3
OFF
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L
Figure 7. Timing diagram
Note:
1
Latch and output enable terminals are level-sensitive and are not synchronized with rising or
falling edge of LE/DM1 signal.
2
When LE/DM1 terminal is low level, the latch circuit holds previous set of data.
3
When LE/DM1 terminal is high level, the latch circuit refreshes new set of data from SDI
chain.
4
When OE/DM2 terminal is at low level, the output terminals Out 0 to Out 15 respond to data
in the latch circuits, either ‘1’ for ON or ‘0’ for OFF.
5
When OE/DM2 terminal is at high level, all output terminals are switched OFF.
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35
Timing diagrams
STP16DPPS05
Table 10. Enable IO: shutdown truth table
CLOCK
LE/DM1
SDI0 ........... SDI7 ............ SDI15
SH
H
All = L
Active
L
No change
H
One or more = H
OFF
No change
No change
No change
Not active
Active
X (2)
2. Undefined.
Figure 8. Clock, serial-in, serial-out
DocID15817 Rev 3
Not active
OUTn
(1)
1. At power-up, the device starts in shutdown mode.
12/35
Auto
Power-up
STP16DPPS05
Timing diagrams
Figure 9. Clock, serial-in, latch, enable, outputs
LE/DM1
OE/DM2
OUTn
Figure 10. Outputs
OUTn
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35
Typical characteristics
6
STP16DPPS05
Typical characteristics
Figure 11. Output current vs. R-EXT resistor
25000
R external (Ohm)
20000
15000
10000
5000
0
0
10
20
30
40
50
60
70
Current (mA)
Table 11. Output current vs. R-EXT resistor
14/35
R-EXT (Ω)
Output current (mA)
23700
1
11730
2
6930
3
4090
5
2025
10
1000
20
667
30
497
40
331
60
DocID15817 Rev 3
STP16DPPS05
Typical characteristics
Conditions:
Temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 60 mA.
Figure 12. ISET vs. dropout voltage (Vdrop)
1200
Min Drop Voltage (mV)
1000
800
Avg @ 3.3V
Avg @ 5.0V
600
400
200
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65
Current (mA)
Table 12. ISET vs. dropout voltage (Vdrop)
Iout (mA)
Avg (mV) @ 3.3 V
Avg (mV)@ 5.0 V
3
36
37
5
71
72
10
163
163
20
346
347
40
724
726
60
1080
1110
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35
Typical characteristics
STP16DPPS05
TA = 25 °C, Vdd = 3.3 V; 5 V
Figure 13. Output current vs. ± ΔIOL(%)
Figure 14. Idd ON/OFF
12
11
10
9
Idd (mA)
8
AVG IDD ON @ 5.0V
7
AVG IDD ON @ 3.3V
6
AVG IDD OFF @ 5.0V
5
AVG IDD OFF @ 3.3V
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
Iset (mA)
16/35
DocID15817 Rev 3
50
55
60
65
STP16DPPS05
Typical characteristics
Figure 15. Power dissipation vs. package temperature
Note:
The exposed pad should be soldered to the PCB to obtain the thermal benefits.
Figure 16. Turn ON output current
characteristics (1)
Figure 17. Turn OFF output current
characteristics (2)
Electrical conditions:
Vdd = 3.3 V, Vin = Vdd, Vled = 3.0 V, RL = 60 Ω, CL = 10 pF
Ch1 (Yellow) = OE/DM2, Ch2 (Blue) = SDI, Ch3 (Purple) = VOUT, Ch4 (Green) = OUT
1. The reference level for the TON characteristics is 50% of OE/DM2 signal and 90% of output current
2. The reference level for the TOFF characteristics is 50% of OE/DM2 signal and 10% of output current
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35
Error detection mode functionality
STP16DPPS05
7
Error detection mode functionality
7.1
Phase one: entering error detection mode
From the “normal mode” condition the device can switch to “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and diagram:
Table 13. Entering error detection mode - truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 18. Entering error detection mode - timing diagram
CLK
OE/DM2
LE/DM1
After these five CLK cycles, the device goes into “error detection mode” and at the rising
edge of the 6th CLK cycle, the SDI data are ready for sampling.
18/35
DocID15817 Rev 3
STP16DPPS05
7.2
Error detection mode functionality
Phase two: error detection
The 16 data bits must be set to “1” in order for all the outputs to be ON during error
detection. The data are latched by LE/DM1, after which the outputs are ready for the
detection process. When the microcontroller switches the OE/DM2 to LOW, the device
drives the LEDs to analyze if an OPEN or SHORT condition has occurred.
Figure 19. Detection diagram
The status of the LEDs is detected in at least 1 microsecond, and after this period the
microcontroller sets OE/DM2 to HIGH state and the output data detection result is sent to
the microcontroller via SDO.
Error detection mode and normal mode both use the same data format. As soon as all the
detection data bits are available on the serial line, the device may return to normal mode of
operation. To re-detect the status, the device must first return to normal mode and reenter
error detection mode.
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35
Error detection mode functionality
STP16DPPS05
D.U.T.
D.U.T.
D.U.T.
D.U.T.
D.U.T.
Figure 20. Timing example for open and/or short-circuit detection
20/35
DocID15817 Rev 3
STP16DPPS05
7.3
Error detection mode functionality
Phase three: resuming normal mode
The sequence for reentering normal mode is shown in the following table:
Figure 21. Resuming normal mode - timing diagram
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
Note:
For proper device operation, the “entering error detection” sequence must be followed by a
“resume mode” sequence, it is not possible to insert consecutive equal sequences.
7.4
Error detection conditions
Table 14. Detection conditions (VDD = 3.3 to 5 V, temperature range -40 to 125 °C)
Configuration
Note:
Detect mode
Detection results
SW-1 or
SW-3b
Open line or output
No error
==> IODEC ≤ 0.5 x IO
short to GND detected
detected
==> IODEC ≥ 0.5 x IO
SW-2 or
SW-3a
Short on LED or short
==> VO ≥ 2.6 V
to V-LED detected
==> VO ≤ 2.3 V
No error
detected
Where: IO = the output current programmed by the R-EXT, IODEC = the detected output
current in detection mode
Figure 22. Detection circuit
STP16DPPS05
16
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35
Error detection mode functionality
STP16DPPS05
Figure 23. Error detection sequence
This LE/DM1 pulse latch
the data to the outputs
Feeding 16 bit of CLK signal af ter
entering the EDM, the SDI signal, set to
1, is loaded in the shif t register
OE/DM2 and LE/DM1
sequence signals to
start the error
detection sequence
Ignore
On the rising edge of f irst CLK pulse af ter the detection, the SDO
provides the Output status f eedback with the sequence Out 15;
Out 14…Out 0.
In this case all the outputs are in f ault condition (Open or Short)
Turn ON the output with the OE/DM2 pin and wait 1 µs to
have the correct output status acquisition. During this time
a minimum of three CLK pulses are required (2 at the
beginning and 1 at the end) to rewrite the shif t register.
22/35
This OE/DM2 pulse put the
device in Normal Mode
Condition af ter EDM test
DocID15817 Rev 3
STP16DPPS05
7.5
Error detection mode functionality
Auto power-saving
The auto power-saving feature minimizes the quiescent current if no active data is detected
on the latches and auto powers-up the device as the first active data is latched.
Figure 24. Auto power-saving feature
Conditions:
Temp. = 25 °C, Vdd = 3.3 V, Vin = Vdd, VLed = 3.0 V, Iset = 20 mA
Ch1 (Yellow) = CLK, Ch2 (Blue) = SDI, Ch3 (Purple) = LE/DM1, Ch4 (Green) = IDD
Idd consumption:
Idd (normal operation) = 2.93 mA
Idd (shutdown condition) = 170 µA
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35
Error detection mode functionality
STP16DPPS05
Figure 25. Auto power-saving feature
Conditions:
Temp. = 25°C, Vdd = 3.3 V, Vin = Vdd, VLed = 3.0 V, Iset = 20 mA
Ch1 (Yellow) = CLK, Ch2 (Blue) = SDI, Ch3 (Purple) = LE/DM1, Ch4 (Green) = IDD
Note:
24/35
When the device goes from auto power-saving to normal operating condition, the first output
that switches ON shows the TON condition as seen in the plot above.
DocID15817 Rev 3
STP16DPPS05
8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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35
Package mechanical data
STP16DPPS05
Figure 26. QSOP-24 package dimensions
26/35
DocID15817 Rev 3
STP16DPPS05
Package mechanical data
Table 15. QSOP-24 mechanical data
mm.
Dim.
Min
Typ
Max
A
1.54
1.62
1.73
A1
0.1
0.15
0.25
A2
1.47
b
0.31
0.2
c
0.254
0.17
D
8.56
8.66
8.76
E
5.8
6
6.2
E1
3.8
3.91
4.01
e
0.635
L
0.4
0.635
0.89
h
0.25
0.33
0.41
<
8°
0°
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Package mechanical data
STP16DPPS05
Figure 27. TSSOP24 package dimensions
Table 16. TSSOP24 mechanical data
mm
Dim.
Min.
Typ.
A
A1
1.1
0.05
A2
0.15
0.9
b
0.19
0.30
c
0.09
0.20
D
7.7
7.9
E
4.3
4.5
e
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Max.
0.65 BSC
H
6.25
6.5
K
0°
8°
L
0.50
0.70
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Package mechanical data
Figure 28. SO-24 package dimensions
Table 17. SO-24 mechanical data
mm.
Dim.
Min
Typ
A
a1
Max
2.65
0.1
0.2
a2
2.45
b
0.35
0.49
b1
0.23
0.32
C
0.5
c1
45°(typ.)
D
15.20
15.60
E
10.00
10.65
e
1.27
e3
13.97
F
7.40
7.60
L
0.50
1.27
S
°(max.) 8
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Package mechanical data
STP16DPPS05
Figure 29. TSSOP24 exposed pad dimensions
7100778_D
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Package mechanical data
Table 18. TSSOP24 exposed pad mechanical data
mm
Dim.
Min.
Typ.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
7.70
7.80
7.90
D1
4.80
5.00
5.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
3.00
3.20
3.40
e
L
1.05
0.65
0.45
L1
k
1.00
0.60
0.75
1.00
0
aaa
8
0.10
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Packaging mechanical data
9
STP16DPPS05
Packaging mechanical data
Figure 30. TSSOP24, TSSOP24 exposed pad and SO-24 reel dimensions
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Packaging mechanical data
Table 19. TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data
mm
Dim.
Min.
A
Typ.
Max.
-
330
13.2
C
12.8
-
D
20.2
-
N
60
-
T
-
22.4
Ao
6.8
-
7
Bo
8.2
-
8.4
Ko
1.7
-
1.9
Po
3.9
-
4.1
P
11.9
-
12.1
Table 20. SO-24 tape and reel mechanical data
mm.
Dim.
Min
A
Typ
Max
-
330
13.2
C
12.8
-
D
20.2
-
N
60
-
T
-
30.4
Ao
10.8
-
11.0
Bo
15.7
-
15.9
Ko
2.9
-
3.1
Po
3.9
-
4.1
P
11.9
-
12.1
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Revision history
10
STP16DPPS05
Revision history
Table 21. Document revision history
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Date
Revision
Changes
05-Jun-2009
1
Initial release.
23-Oct-2009
2
Updated document status from preliminary status to final and
Note: on page 3
17-Jun-2014
3
Updated Section 8: Package mechanical data.
Added Section 9: Packaging mechanical data.
Minor text changes.
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