M24M01 1 Mbit Serial I²C Bus EEPROM FEATURES SUMMARY 2 ■ 400 kHz High Speed Two Wire I C Serial Interface ■ Figure 1. Packages Single Supply Voltage: – 2.7V to 3.6V for M24M01-V – 1.8V to 3.6V for M24M01-S ■ Write Control Input ■ BYTE and PAGE WRITE (up to 128 Bytes) ■ RANDOM and SEQUENTIAL READ Modes ■ Self-Timed Programming Cycle ■ Automatic Address Incrementing ■ Enhanced ESD/Latch-Up Behavior ■ More than 100000 Erase/Write Cycles ■ More than 40 Year Data Retention January 2003 LGA LGA8 (LA) 1/19 M24M01 SUMMARY DESCRIPTION The M24M01 is a 1 Mbit (131,072 x 8) electrically erasable programmable memory (EEPROM) accessed by an I2C-compatible bus. Figure 2. Logic Diagram VCC When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Figure 3. LGA Connections 2 E1-E2 SCL SDA M24M01 M24M01 DU E1 E2 VSS WC VSS 1 2 3 4 8 7 6 5 VCC WC SCL SDA AI04051C AI04048B Table 1. Signal Names E1, E2 Chip Enable SDA Serial Data SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit. 2/19 Note: 1. DU = Don’t Use (should be left unconnected, or tied to VSS) Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal. When the power supply is turned on, V CC rises from VSS to VCC(min), passing through a value Vth in between. The device ignores all instructions until a time delay of tPU has elapsed after the moment that VCC rises above the Vth threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min).No instructions should be sent until the later of: – tPU after V CC passed the Vth threshold – VCC passed the VCC(min) level These values are specified in Table 9. M24M01 SIGNAL DESCRIPTION Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V CC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E1, E2) These input signals are used to set the value that is to be looked for on bits b3 and b2 of the 7-bit Device Select Code. These inputs must be tied to VCC or V SS, to establish the Device Select Code. When unconnected, the Chip Enable (E1, E2) signals are internally read as VIL (see Tables 10 and 11). Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. Figure 4. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus VCC Maximum RP value (kΩ) 20 16 RL 12 RL SDA MASTER 8 fc = 100kHz 4 fc = 400kHz CBUS SCL CBUS 0 10 100 1000 CBUS (pF) AI01665 3/19 M24M01 DEVICE OPERATION The device supports the I2C protocol. This is summarized in Figure 2. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24M01 device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 2-bit Chip Enable “Address” (E1, E2). To address the memory array, the 4-bit Device Type Identifier is 1010b. Up to four memory devices can be connected on a single I 2C bus. Each one is given a unique 2-bit code on the Chip Enable (E1, E2) inputs. When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode. Table 2. Device Select Code 1 Device Type Identifier Device Select Code RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2 E1 A16 RW Note: 1. The most significant bit, b7, is sent first. 4/19 Chip Enable Address M24M01 Figure 5. I2C Bus Protocol SCL SDA SDA Input START Condition SCL 1 2 SDA MSB SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition AI00792B Table 3. Operating Modes Mode Current Address Read RW bit WC 1 Bytes 1 X 1 0 X Random Address Read Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address 1 reSTART, Device Select, RW = 1 1 X Sequential Read 1 X ≥1 Byte Write 0 VIL 1 START, Device Select, RW = 0 Page Write 0 VIL ≤ 128 START, Device Select, RW = 0 Similar to Current or Random Address Read Note: 1. X = VIH or VIL. 5/19 M24M01 Figure 6. Write Mode Sequences with WC=1 (data write inhibited) WC ACK BYTE ADDR ACK BYTE ADDR NO ACK DATA IN STOP DEV SEL START BYTE WRITE ACK R/W WC ACK DEV SEL START PAGE WRITE ACK BYTE ADDR ACK BYTE ADDR NO ACK DATA IN 1 DATA IN 2 R/W WC (cont'd) NO ACK DATA IN N STOP PAGE WRITE (cont'd) NO ACK AI01120C Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 6. Each data byte in the memory has a 17-bit address. The most significant bit, A16, is sent with the Device Select Code, and the remaining bits, A15-A0, in the two address bytes. The Most Significant Byte is sent first, followed by the Least Sig- 6/19 nificant Byte. Bits A16 to A0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the “10 th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. Byte Write After the Device Select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master M24M01 terminates the transfer by generating a Stop condition, as shown in Figure 7. Page Write The Page Write mode allows up to 128 bytes to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits (b16-b7) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 128 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 7. Write Mode Sequences with WC=0 (data write enabled) WC ACK BYTE ADDR ACK BYTE ADDR ACK DATA IN STOP DEV SEL START BYTE WRITE ACK R/W WC ACK DEV SEL START PAGE WRITE ACK BYTE ADDR ACK BYTE ADDR ACK DATA IN 1 DATA IN 2 R/W WC (cont'd) ACK DATA IN N STOP PAGE WRITE (cont'd) ACK AI01106C 7/19 M24M01 Figure 8. Write Cycle Polling Flowchart using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK Returned YES NO Next Operation is Addressing the Memory YES Send Address and Receive ACK ReSTART NO STOP YES DATA for the WRITE Operation DEVICE SELECT with RW = 1 Continue the WRITE Operation Continue the Random READ Operation Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 12, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 8, is: – Initial condition: a Write cycle is in progress. 8/19 START Condition AI01847C – Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). – Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). M24M01 Figure 9. Read Mode Sequences ACK DATA OUT STOP START DEV SEL NO ACK R/W ACK START DEV SEL * ACK BYTE ADDR ACK DEV SEL * ACK DATA OUT 1 ACK ACK NO ACK DATA OUT N BYTE ADDR ACK BYTE ADDR ACK DEV SEL * START START ACK R/W ACK DATA OUT R/W R/W DEV SEL * NO ACK STOP START DEV SEL SEQUENTIAL RANDOM READ BYTE ADDR R/W ACK SEQUENTIAL CURRENT READ ACK START RANDOM ADDRESS READ STOP CURRENT ADDRESS READ ACK DATA OUT 1 R/W NO ACK STOP DATA OUT N AI01105C Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 st and 4th bytes) must be identical. Read Operations Read operations are performed independently of the state of the Write Control (WC) signal. Random Address Read A dummy Write is performed to load the address into the address counter (as shown in Figure 9) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the 9/19 M24M01 transfer with a Stop condition, as shown in Figure 9, without acknowledging the byte. Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9. The output data comes from consecutive addresses, with the internal address counter automatically 10/19 incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode. M24M01 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute Maximum Ratings Symbol Parameter TSTG Storage Temperature TLEAD Lead Temperature during Soldering LGA: 20 seconds (max) 1 Min. Max. Unit –65 150 °C 235 °C VIO Input or Output range –0.6 4.2 V VCC Supply Voltage –0.3 4.2 V VESD Electrostatic Discharge Voltage (Human Body model) 2 –3000 3000 V Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) 11/19 M24M01 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 5. Operating Conditions (M24M01-V) Symbol VCC TA Parameter Min. Max. Unit Supply Voltage 2.7 3.6 V Ambient Operating Temperature –40 85 °C Min. Max. Unit Supply Voltage 1.8 3.6 V Ambient Operating Temperature –40 85 °C Min. Max. Unit Table 6. Operating Conditions (M24M01-S) Symbol VCC TA Parameter Table 7. AC Measurement Conditions Symbol CL Parameter Load Capacitance 30 Input Rise and Fall Times pF 50 ns Input Pulse Voltages 0.2VCC to 0.8VCC V Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 10. AC Measurement I/O Waveform Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI00825B Table 8. Capacitance Symbol Parameter Min. Max. Unit CIN Input Capacitance (SDA) 8 pF CIN Input Capacitance (other pins) 6 pF tNS Pulse width ignored (Input Filter on SCL and SDA) 50 ns Note: 1. TA = 25 °C, f = 400 kHz 2. Sampled only, not 100% tested. 12/19 Test Condition M24M01 Table 9. Power-Up Timing and Vth Threshold Test Condition1 Symbol Parameter tPU Time delay to Read or Write instruction Vth Threshold Voltage Min. Max. Unit 200 µs 1.1 1.4 V Min. Max. Unit Note: 1. These parameters are characterized only. Table 10. DC Characteristics (M24M01-V) Symbol Test Condition (in addition to those in Table 5) Parameter ILI Input Leakage Current (SCL, SDA, E1, E2, WC) VIN = VSS or VCC ±1 µA ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC, SDA in Hi-Z ±2 µA ICC Supply Current VCC =3.6V, fc=400kHz (rise/fall time < 30ns) 2 mA ICC1 Stand-by Supply Current VIN = VSS or VCC , 2.7 V ≤ VCC ≤ 3.6 V 2 µA VIL Input Low Voltage (E1, E2, SCL, SDA, WC) – 0.3 0.3VCC V VIH Input High Voltage (E1, E2, SCL, SDA, WC) 0.7VCC VCC+1 V VOL Output Low Voltage 0.4 V Max. Unit IOL = 2.5 mA, 2.7 V ≤ VCC ≤ 3.6 V Table 11. DC Characteristics (M24M01-S) Symbol Parameter Test Condition (in addition to those in Table 6) Min. ILI Input Leakage Current (SCL, SDA, E1, E2, WC) VIN = VSS or VCC ±1 µA ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC, SDA in Hi-Z ±2 µA ICC Supply Current VCC =3.6V, fc=400kHz (rise/fall time < 30ns) 2 mA ICC1 Stand-by Supply Current VIN = VSS or VCC , VCC=3.6 V 2 µA VIL Input Low Voltage (E1, E2, SCL, SDA, WC) – 0.3 0.3VCC V VIH Input High Voltage (E1, E2, SCL, SDA, WC) 0.7VCC VCC+1 V V Output Low Voltage IOL = 2.5 mA, 2.7 V ≤ VCC ≤ 3.6 V 0.4 VOL RL = 2.2 kΩ, 1.8 V ≤ VCC ≤ 3.6 V 0.2VCC V 13/19 M24M01 Table 12. AC Characteristics Test conditions specified in Table 7 and Table 5 or Table 6 Symbol Alt. Parameter fC fSCL Clock Frequency tCH1CH2 tR Clock Rise Time tCL1CL2 tF tCHCL Min. Max. Unit 400 kHz 20 300 ns Clock Fall Time 20 300 ns tHIGH Clock Pulse Width High 600 ns tCLCH tLOW Clock Pulse Width Low 1300 ns tDH1DH2 2 tR SDA Rise Time 20 300 ns tDL1DL2 2 tF SDA Fall Time 20 300 ns tDXCX tSU:DAT Data In Set Up Time 100 ns tCLDX tHD:DAT Data In Hold Time 0 ns tCLQX tDH Data Out Hold Time 200 ns tCLQV 3 tAA Clock Low to Next Data Valid (Access Time) 205 tCHDX 1 tSU:STA Start Condition Set Up Time 600 ns tDLCL tHD:STA Start Condition Hold Time 600 ns tCHDH tSU:STO Stop Condition Set Up Time 600 ns tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns tW tWR Write Time 900 10 ns ms Note: 1. For a reSTART condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 14/19 M24M01 Figure 11. AC Waveforms tCHCL tCLCH SCL tDLCL SDA In tCHDX tCLDX START Condition SDA Input SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition SCL SDA In tCHDH tW STOP Condition Write Cycle tCHDX START Condition SCL tCLQV SDA Out tCLQX Data Valid AI00795C 15/19 M24M01 PACKAGE MECHANICAL LGA8 - 8 lead Land Grid Array, Package Outline CONTACT 1 D D1 T3 E1 E k T1 T2 E2 E3 A A2 A1 ddd LGA-Z01B Notes: 1. Drawing is not to scale. LGA8 - 8 lead Land Grid Array, Package Mechanical Data mm inches Symb. 16/19 Typ. Min. Max. Typ. Min. Max. A 1.040 0.940 1.140 0.0409 0.0370 0.0449 A1 0.340 0.300 0.380 0.0134 0.0118 0.0150 A2 0.700 0.640 0.760 0.0276 0.0252 0.0299 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 0.100 – – 0.0039 – – E 5.000 4.900 5.100 0.1969 0.1929 0.2008 E1 1.270 – – 0.0500 – – E2 3.810 – – 0.1500 – – E3 0.390 – – 0.0154 – – k 0.100 – – 0.0039 – – T1 0.410 – – 0.0161 – – T2 0.670 – – 0.0264 – – T3 0.970 – – 0.0382 – – ddd 0.100 – – 0.0039 – – M24M01 PART NUMBERING Table 13. Ordering Information Scheme Example: M24M01 – V LA 6 T Device Type M24 = I2C serial access EEPROM Device Function M01 = 1 Mbit (131,072 x 8) Operating Voltage V = VCC = 2.7 to 3.6V S = VCC = 1.8 to 3.6V Package LA = LGA8 (Land Grid Array) Temperature Range 6 = –40 to 85 °C Option T = Tape & Reel Packing For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 17/19 M24M01 REVISION HISTORY Table 14. Document Revision History Date Rev. 02-Oct-2001 1.0 LGA8 Package mechanical data updated Datasheet released as Product Preview 21-Jun-2002 1.1 Table added on Power-up Timing Full Datasheet released 08-Jan-2003 1.2 Added LGA maximum rating for soldering temperature 18/19 Description of Revision M24M01 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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