M24512-W M24512-R M24512-DF 512-Kbit serial I²C bus EEPROM Datasheet - production data Features • Compatible with all I2C bus modes: – 1 MHz – 400 kHz – 100 kHz TSSOP8 (DW) 169 mil width • Memory array: – 512 Kbit (64 Kbytes) of EEPROM – Page size: 128 bytes – Additional Write lockable page (M24512-D order codes) • Single supply voltage and high speed: – 1 MHz clock from 1.7 V to 5.5 V SO8 (MN) 150 mil width • Write: – Byte Write within 5 ms – Page Write within 5 ms • Operating temperature range: – from -40 °C up to +85 °C UFDFPN8 (MC) • Random and sequential Read modes • Write protect of the whole memory array • Enhanced ESD/Latch-Up protection • More than 4 million Write cycles • More than 200-years data retention Packages • SO8 ECOPACK2® WLCSP (CS) • TSSOP8 ECOPACK2® • UFDFPN8 ECOPACK2® • WLCSP ECOPACK2® • Unsawn wafer (each die is tested) Unsawn wafer May 2015 This is information on a product in full production. DocID16459 Rev 28 1/43 www.st.com Contents M24512-W M24512-R M24512-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 5.2 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 Write Identification Page (M24512-D only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 Lock Identification Page (M24512-D only) . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17 5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 2/43 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DocID16459 Rev 28 M24512-W M24512-R M24512-DF Contents 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Read Identification Page (M24512-D only) . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Read the lock status (M24512-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3 UFDFPN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.4 WLCSP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DocID16459 Rev 28 3/43 3 List of tables M24512-W M24512-R M24512-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. 4/43 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC characteristics (M24512-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC characteristics (M24512-R device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M24512-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TSSOP8 – 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 35 UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 M24512-DFCS6TP/K (WLCSP 8-bump wafer-level chip scale package) related mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DocID16459 Rev 28 M24512-W M24512-R M24512-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP connections for the M24512-DFCS6TP/K (top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33 SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 35 UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 M24512-DFCS6TP/K (WLCSP 8-bump wafer-level chip scale package) outline . . . . . . . . 37 M24512-DFCS6TP/K recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID16459 Rev 28 5/43 5 Description 1 M24512-W M24512-R M24512-DF Description The M24512 is a 512-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 64 K × 8 bits. The M24512-W can operate with a supply voltage from 2.5 V to 5.5 V, the M24512-R can operate with a supply voltage from 1.8 V to 5.5 V and the M24512-DF can operate with a supply voltage from 1.7 V to 5.5 V. All these devices operate with a clock frequency of 1 MHz (or less) over an ambient temperature range of -40 °C / +85 °C. The M24512-D offers an additional page, named the Identification Page (128 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode. Figure 1. Logic diagram 9&& (( 6'$ 0[[[ 6&/ :& 966 $,I Table 1. Signal names Signal name 6/43 Function Direction E2, E1, E0 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage - VSS Ground - DocID16459 Rev 28 M24512-W M24512-R M24512-DF Description Figure 2. 8-pin package connections, top view ( 9&& ( :& ( 6&/ 966 6'$ $,I Figure 3. WLCSP connections for the M24512-DFCS6TP/K (top view, marking side, with balls on the underside) s ^ % ^> Ϯ t ϭ s ^^ $ & ' Ϭ ( 069 DocID16459 Rev 28 7/43 42 Signal description M24512-W M24512-R M24512-DF 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 12 indicates how to calculate the value of the pull-up resistor). 2.3 Chip Enable (E2, E1, E0) (E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must be tied to VCC or VSS, as shown in Figure 4. When not connected (left floating), these inputs are read as low (0). Figure 4. Chip enable inputs connection 9&& 9&& 0[[[ 0[[[ (L (L 966 2.4 966 $L Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 2.5 Signal description VSS (ground) VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). DocID16459 Rev 28 9/43 42 Memory organization 3 M24512-W M24512-R M24512-DF Memory organization The memory is organized as shown below. Figure 5. Block diagram 7# % % % (IGHVOLTAGE GENERATOR #ONTROLLOGIC 3#, 3$! )/SHIFTREGISTER $ATA REGISTER 9DECODER !DDRESSREGISTER ANDCOUNTER PAGE )DENTIFICATIONPAGE 8DECODER -36 10/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications. Figure 6. I2C bus protocol 3#, 3$! 3$! )NPUT 34!24 #ONDITION 3#, 3$! -3" 3$! #HANGE 34/0 #ONDITION !#+ 34!24 #ONDITION 3#, 3$! -3" !#+ 34/0 #ONDITION !)" DocID16459 Rev 28 11/43 42 Device operation 4.1 M24512-W M24512-R M24512-DF Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle. 4.3 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 4.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 12/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 4.5 Device operation Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (most significant bit first). Table 2. Device select code Device type identifier(1) Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 Device select code when addressing the memory array 1 0 1 0 E2 E1 E0 RW Device select code when accessing the Identification page 1 0 1 1 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared with the value read on input pins E0, E1 and E2. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E2, E1, E0) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. DocID16459 Rev 28 13/43 42 Instructions M24512-W M24512-R M24512-DF 5 Instructions 5.1 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 A1 A0 Table 4. Least significant address byte A7 A6 A5 A4 A3 A2 When the bus master generates a Stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition and the successful completion of an internal Write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 8. 14/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. Figure 7. Write mode sequences with WC = 0 (data write enabled) 7# !#+ !#+ !#+ "YTEADDR "YTEADDR !#+ $ATAIN 3TOP $EVSEL 3TART "YTE7RITE 27 7# !#+ 0AGE7RITE !#+ "YTEADDR $EVSEL 3TART !#+ "YTEADDR !#+ $ATAIN $ATAIN 27 7#CONTgD !#+ 0AGE7RITECONTgD !#+ $ATAIN. 3TOP 5.1.1 Instructions DocID16459 Rev 28 !)D 15/43 42 Instructions 5.1.2 M24512-W M24512-R M24512-DF Page Write The Page Write mode allows up to 128 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A7, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. The bus master sends from 1 to 128 bytes of data, each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck, as shown in Figure 8. After each transferred byte, the internal page address counter is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 8. Write mode sequences with WC = 1 (data write inhibited) 7# !#+ "YTEADDR !#+ "YTEADDR ./!#+ $ATAIN 3TOP $EVSEL 3TART "YTE7RITE !#+ 27 7# !#+ "YTEADDR $EVSEL 3TART 0AGE7RITE !#+ !#+ "YTEADDR ./!#+ $ATAIN $ATAIN 27 7#CONTgD ./!#+ $ATAIN. 3TOP 0AGE7RITECONTgD ./!#+ 16/43 DocID16459 Rev 28 !)D M24512-W M24512-R M24512-DF 5.1.3 Instructions Write Identification Page (M24512-D only) The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: • Device type identifier = 1011b • MSB address bits A15/A7 are don't care except for address bit A10 which must be ‘0’. LSB address bits A6/A0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck). 5.1.4 Lock Identification Page (M24512-D only) The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: 5.1.5 • Device type identifier = 1011b • Address bit A10 must be ‘1’; all other address bits are don't care • The data byte must be equal to the binary value xxxx xx1x, where x is don't care ECC (Error Correction Code) and Write cycling(1) The Error Correction Code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(2). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group(2). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 11. 1. Only for devices identified with process letter K 2. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer. DocID16459 Rev 28 17/43 42 Instructions 5.1.6 M24512-W M24512-R M24512-DF Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: • Initial condition: a Write cycle is in progress. • Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). • Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 9. Write cycle polling flowchart using ACK tƌŝƚĞĐLJĐůĞ ŝŶƉƌŽŐƌĞƐƐ ^ƚĂƌƚĐŽŶĚŝƚŝŽŶ ĞǀŝĐĞƐĞůĞĐƚ ǁŝƚŚZtсϬ EK )LUVWE\WHRILQVWUXFWLRQ ZLWK5: DOUHDG\ GHFRGHGE\WKHGHYLFH < ƌĞƚƵƌŶĞĚ z^ EK EĞdžƚ KƉĞƌĂƚŝŽŶŝƐ ĂĚĚƌĞƐƐŝŶŐƚŚĞ ŵĞŵŽƌLJ z^ ^ĞŶĚĚĚƌĞƐƐ ĂŶĚZĞĐĞŝǀĞ< ZĞ^ƚĂƌƚ ^ƚŽƉ EK ĂƚĂĨŽƌƚŚĞ tƌŝƚĞĐƉĞƌĂƚŝŽŶ ŽŶƚŝŶƵĞƚŚĞ tƌŝƚĞŽƉĞƌĂƚŝŽŶ 6WDUW&RQGLWLRQ z^ 'HYLFHVHOHFW ZLWK5: ŽŶƚŝŶƵĞƚŚĞ ZĂŶĚŽŵZĞĂĚŽƉĞƌĂƚŝŽŶ $,H 1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling instruction in the figure). 18/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address. For the Read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its Standby mode. Figure 10. Read mode sequences !#+ $ATAOUT 3TOP 3TART $EVSEL ./!#+ 27 !#+ 2ANDOM !DDRESS 2EAD "YTEADDR $EVSEL !#+ !#+ $ATAOUT $ATAOUT 27 ./!#+ $ATAOUT. 27 !#+ !#+ "YTEADDR !#+ "YTEADDR 27 !#+ $EVSEL 3TART $EVSEL !#+ $ATAOUT 27 ./!#+ $ATAOUT. 3TOP !#+ ./!#+ 3TOP 3TART $EVSEL 3EQUENTION 2ANDOM 2EAD !#+ "YTEADDR 27 !#+ 3EQUENTIAL #URRENT 2EAD !#+ 3TART 3TART $EVSEL !#+ 3TOP #URRENT !DDRESS 2EAD 3TART 5.2 Instructions DocID16459 Rev 28 !)D 19/43 42 Instructions 5.2.1 M24512-W M24512-R M24512-DF Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 5.2.2 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the Identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the Identification page, therefore the next Current Address Read in the memory uses this new address counter value. When accessing the memory, it is safer to always use the Random Address Read instruction (this instruction loads the address counter with the byte location to read in the memory, see Section 5.2.1) instead of the Current Address Read instruction. 5.2.3 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h. 5.3 Read Identification Page (M24512-D only) The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits A15/A7 are don't care, the LSB address bits A6/A0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 100d, the number of bytes should be less than or equal to 28, as the ID page boundary is 128 bytes). 20/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 5.4 Instructions Read the lock status (M24512-D only) The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked. Right after this, it is recommended to transmit to the device a Start condition followed by a Stop condition, so that: • Start: the truncated command is not executed because the Start condition resets the device internal logic, • Stop: the device is then set back into Standby mode by the Stop condition. DocID16459 Rev 28 21/43 42 Initial delivery state 6 M24512-W M24512-R M24512-DF Initial delivery state The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains FFh). 22/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 7 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol TSTG TLEAD Parameter Min. Max. Unit Ambient operating temperature –55 130 °C Storage temperature –65 150 °C (1) °C - 5 mA –0.50 6.5 V –0.50 6.5 V - 4000(3) V Lead temperature during soldering IOL DC output current (SDA = 0) VIO Input or output range VCC Supply voltage VESD Electrostatic pulse (Human Body model)(2) see note 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on different combinations of pin connections, according to AECQ100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012 standard, C1=100 pF, R1=1500 Ω). 3. 4000 V for new devices identified with process letters KB and 3000 V for previous devices identified with process letters KA and AB. DocID16459 Rev 28 23/43 42 DC and AC parameters 8 M24512-W M24512-R M24512-DF DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Operating conditions (voltage range W) Symbol VCC TA fC Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 85 °C (1) 1 MHz Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature –40 85 °C - 1(1) MHz Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature –40 85 °C - 1(1) MHz Max. Unit Operating clock frequency - 1. For devices identified by process letter K. Table 7. Operating conditions (voltage range R) Symbol VCC TA fC Parameter Operating clock frequency 1. For devices identified by process letter K. Table 8. Operating conditions (voltage range F) Symbol VCC TA fC Parameter Operating clock frequency 1. For devices identified by process letter K. Table 9. AC measurement conditions Symbol Cbus 24/43 Parameter Min. Load capacitance 100 - SCL input rise/fall time, SDA input fall time - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing reference levels 0.3 VCC to 0.7 VCC V DocID16459 Rev 28 - pF 50 ns M24512-W M24512-R M24512-DF DC and AC parameters Figure 11. AC measurement I/O waveform )NPUTVOLTAGELEVELS )NPUTANDOUTPUT 4IMINGREFERENCELEVELS 6## 6## 6## 6## -36 Table 10. Input parameters Parameter(1) Symbol Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 30 - kΩ VIN > 0.7 VCC 500 - kΩ ZL ZH Input impedance (E2, E1, E0, WC)(2) 1. Characterized only, not tested in production. 2. E2, E1, E0 input impedance when the memory is selected (after a Start condition). Table 11. Cycling performance Symbol Parameter(1) Ncycle Write cycle endurance(2) Test condition Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(3) 1. Cycling performance for products identified by process letter KB (previous products were specified with 1 million cycles at 25 °C). 2. The write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and qualification. 3. A Write cycle is executed when either a Page Write, a Byte write, a Write Identification Page or a Lock Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling Table 12. Memory cell data retention Parameter Data retention (1) Test condition TA = 55 °C Min. Unit 200(2) Year 1. The data retention behavior is checked in production, while the data retention limit defined in this table is extracted from characterization and qualification results. 2. For products identified by process letter KB (previous products were specified with a data retention of 40 years at 55°C). DocID16459 Rev 28 25/43 42 DC and AC parameters M24512-W M24512-R M24512-DF Table 13. DC characteristics (M24512-W, device grade 6) Symbol Parameter ILI Input leakage current (SCL, SDA, E2, E1, E0) ILO Output leakage current ICC ICC0 ICC1 VIL VIH VOL Supply current (Read) Supply current (Write) Standby supply current Test conditions (in addition to those in Table 6 and Table 9) Min. Max. Unit VIN = VSS or VCC, device in Standby mode - ±2 µA SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 2.5 V, fc = 400 kHz (rise/fall time < 50 ns) - 2(1) VCC = 5.5 V, fc = 400 kHz (rise/fall time < 50 ns) - 2 2.5 V < VCC < 5.5 V, fc = 400 kHz (rise/fall time < 50 ns) - 2 2.5 V ≤VCC ≤ 5.5 V, fc = 1 MHz (rise/fall time < 50 ns) - 2.5 During tW, 2.5 V ≤ VCC ≤ 5.5 V - 5(2) mA Device not selected(3), VIN = VSS or VCC, VCC = 2.5 V - 2 µA Device not selected, VIN = VSS or VCC, VCC = 5.5 V - 3 µA mA Input low voltage (SCL, SDA, WC, E2, E1, E0)(4) - –0.45 0.3 VCC V Input high voltage (SCL, SDA) - 0.7 VCC 6.5 V Input high voltage (WC, E2, E1, E0)(5) - 0.7 VCC VCC+0.6 Output low voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V - 0.4 1. For devices identified by process letter AB: ICC(max) = 1 mA. 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). 4. Ei inputs should be tied to Vss (see Section 2.3). 5. Ei inputs should be tied to Vcc (see Section 2.3). 26/43 DocID16459 Rev 28 V V M24512-W M24512-R M24512-DF DC and AC parameters Table 14. DC characteristics (M24512-R device grade 6) Symbol Test conditions(1) (in addition to those in Table 7) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC, device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.8 V, fc= 400 kHz - 0.8(2) mA fc= 1 MHz(3) - 2.5 mA During tW - 5(4) mA - 1 µA ICC ICC0 Supply current (Read) Supply current (Write) (5), ICC1 Standby supply current Device not selected VIN = VSS or VCC, VCC = 1.8 V VIL Input low voltage (SCL, SDA, WC)(6) 1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V Input high voltage (SCL, SDA) 1.8 V ≤ VCC < 2.5 V 0.75 VCC 6.5 V Input high voltage (WC, E2, E1, E0)(7) 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+ 0.6 Output low voltage IOL = 1 mA, VCC = 1.8 V(8) VIH VOL - 0.2 V V 1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 13 instead of this table. 2. For devices identified by process letters K: ICC(max) = 1.5 mA. 3. Only for devices identified with process letter K. 4. Characterized value, not tested in production. 5. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). 6. Ei inputs should be tied to Vss (see Section 2.3). 7. Ei inputs should be tied to Vcc (see Section 2.3). 8. IOL = 0.7 mA for devices identified by process letters G or S. DocID16459 Rev 28 27/43 42 DC and AC parameters M24512-W M24512-R M24512-DF Table 15. DC characteristics (M24512-DF, device grade 6) Symbol Test conditions(1) (in addition to those in Table 8) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.7 V, fc= 400 kHz - 0.8(2) VCC = 1.6 V, fc= 400 kHz - 2.5 fc = 1.7 MHz(3) - 0.8 During tW - 5(4) mA - 1 µA V ICC ICC0 Supply current (Read) Supply current (Write) (5), ICC1 Standby supply current Device not selected VIN = VSS or VCC, VCC = 1.7 V VIL Input low voltage (SCL, SDA, WC, Ei)(6) 1.7 V ≤ VCC < 2.5 V –0.45 0.25 VCC Input high voltage (SCL, SDA) 1.7 V ≤ VCC < 2.5 V 0.75 VCC 6.5 Input high voltage (WC, E2, E1, E0)(7) 1.7 V ≤ VCC < 2.5 V 0.75 VCC VCC+ 0.6 Output low voltage IOL =1mA, VCC = 1.7 V VIH VOL V - 0.2 1. If the application uses the voltage range F device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 13 instead of this table. 2. For devices identified by process letters K: ICC(max) = 1.5 mA. 3. Only for devices identified by process letter K 4. Characterized value, not tested in production. 5. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). 6. Ei inputs should be tied to VSS(see Section 2.3). 7. Ei inputs should be tied to VCC (see Section 2.3). 28/43 mA DocID16459 Rev 28 V M24512-W M24512-R M24512-DF DC and AC parameters Table 16. 400 kHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tQL1QL2(1) tF tXH1XH2 tR Parameter Min. Max. Unit - 400 kHz Clock pulse width high 600 - ns Clock pulse width low 1300 - ns SDA (out) fall time 20(2) 300 ns Input signal rise time (3) (3) ns (3) (3) ns 100 - ns 0 - ns 100 - ns - 900 ns tXL1XL2 tF Input signal fall time tDXCH tSU:DAT Data in set up time tCLDX tHD:DAT Data in hold time tCLQX (4) tDH Data out hold time tCLQV (5) tAA Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tWLDL(6)(1) tSU:WC WC set up time (before the Start condition) 0 - µs tDHWH(7)(1) tHD:WC WC hold time (after the Stop condition) 1 - µs tW tWR Internal Write cycle duration - 5 ms tNS(1) - Pulse width ignored (input filter on SCL and SDA) - single glitch - 80(8) ns 1. Characterized only, not tested in production. 2. With CL = 10 pF. 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12. 6. WC=0 set up time condition to enable the execution of a WRITE command. 7. WC=0 hold time condition to enable the execution of a WRITE command. 8. The previous device offered tNS = 100 ns(max), while the current device offers tNS = 80 ns (max). Both products offer a safe margin compared to the 50ns minimum value recommended by the I2C specification. DocID16459 Rev 28 29/43 42 DC and AC parameters M24512-W M24512-R M24512-DF Table 17. 1 MHz AC characteristics Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock frequency 0 1 MHz tCHCL tHIGH Clock pulse width high 300 - ns tCLCH tLOW Clock pulse width low 550 - ns tXH1XH2 tR Input signal rise time (1) (1) ns (1) (1) ns tXL1XL2 tF Input signal fall time tQL1QL2(2) tF SDA (out) fall time - 120 ns tDXCH tSU:DAT Data in setup time 80 - ns tCLDX tHD:DAT Data in hold time 0 - ns 50 - ns - 500 ns tCLQX(3) tDH Data out hold time tCLQV(4) tAA Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns tWLDL(5)(2) tSU:WC WC set up time (before the Start condition) 0 - µs tDHWH(6)(2) tHD:WC WC hold time (after the Stop condition) 1 - µs tW tWR Write time - 5 ms tNS(2) - Pulse width ignored (input filter on SCL and SDA) - 80(7) ns 1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz. 2. Characterized only, not tested in production. 3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13. 5. WC=0 set up time condition to enable the execution of a WRITE command. 6. WC=0 hold time condition to enable the execution of a WRITE command. 7. 50 ns for devices identified by process letter A. 30/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF DC and AC parameters "USLINEPULLUPRESISTOR K Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz 2 BU S § (ERE2BUS §#BUSNS 4HE2X#TIMECONSTANT BUS BUS MUSTBEBELOWTHENS TIMECONSTANTLINEREPRESENTED ONTHELEFT 6## # BU S 2BUS N K½ S )£#BUS MASTER 3#, -XXX 3$! P& "USLINECAPACITORP& #BUS AIB Figure 13. Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz "USLINEPULLUPRESISTORK 6## 4HE2BUS§#BUSTIMECONSTANT MUSTBEBELOWTHENS TIMECONSTANTLINEREPRESENTED ONTHELEFT 2 BUS § # BUS NS 2BUS )£#BUS MASTER 3#, -XXX 3$! (ERE 2 BUS § #BUSNS #BUS "USLINECAPACITORP& -36 DocID16459 Rev 28 31/43 42 DC and AC parameters M24512-W M24512-R M24512-DF Figure 14. AC waveforms ^ƚĂƌƚ ĐŽŶĚŝƚŝŽŶ ^ƚŽƉ ĐŽŶĚŝƚŝŽŶ ƚy>ϭy>Ϯ ƚy,ϭy,Ϯ ƚ,> ^ƚĂƌƚ ĐŽŶĚŝƚŝŽŶ ƚ>, ^> ƚ>> ƚy>ϭy>Ϯ ^/Ŷ ƚ,> ƚy,ϭy,Ϯ ^ /ŶƉƵƚ ƚy, ^ ŚĂŶŐĞ ƚ>y ƚ,, ƚ,> t ƚ,t, ƚt>> ^ƚŽƉ ĐŽŶĚŝƚŝŽŶ ^ƚĂƌƚ ĐŽŶĚŝƚŝŽŶ ^> ^/Ŷ ƚt ƚ,, ƚ,> tƌŝƚĞĐLJĐůĞ ƚ,> ^> ƚ>Ys ^KƵƚ 32/43 ƚ>Yy ĂƚĂǀĂůŝĚ ĂƚĂǀĂůŝĚ DocID16459 Rev 28 ƚY>ϭY>Ϯ /ϬϬϳϵϱŝ M24512-W M24512-R M24512-DF 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 9.1 TSSOP8 package information Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline $ C % % A ! ! ! , #0 B , E 433/0"- 1. Drawing is not to scale. Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ. Min. Max. Typ. Min. Max. A – – 1.200 – – 0.0472 A1 – 0.050 0.150 – 0.0020 0.0059 A2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b – 0.190 0.300 – 0.0075 0.0118 c – 0.090 0.200 – 0.0035 0.0079 CP – – 0.100 – – 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 – – 0.0256 – – DocID16459 Rev 28 33/43 42 Package mechanical data M24512-W M24512-R M24512-DF Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data (continued) inches(1) millimeters Symbol Typ. Min. Max. Typ. Min. Max. E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 – – 0.0394 – – α – 0° 8° – 0° 8° 1. Values in inches are converted from mm and rounded to four decimal digits. 34/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 9.2 Package mechanical data SO8N package information Figure 16. SO8N – 8-lead plastic small outline, 150 mils body width, package outline K[Û $ $ F FFF E H PP *$8*(3/$1( ' N ( ( $ / / 62B$B9 1. Drawing is not to scale. Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data inches (1) millimeters Symbol Typ Min Max Typ Min Max A – – 1.750 – – 0.0689 A1 – 0.100 0.250 – 0.0039 0.0098 A2 – 1.250 – – 0.0492 – b – 0.280 0.480 – 0.0110 0.0189 c – 0.170 0.230 – 0.0067 0.0091 ccc – – 0.100 – – 0.0039 D 4.900 4.800 5.000 0.1929 0.1890 0.1969 E 6.000 5.800 6.200 0.2362 0.2283 0.2441 E1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 – – 0.0500 – – h – 0.250 0.500 – 0.0098 0.0197 k – 0° 8° – 0° 8° L – 0.400 1.270 – 0.0157 0.0500 L1 1.040 – – 0.0409 – – 1. Values in inches are converted from mm and rounded to four decimal digits. DocID16459 Rev 28 35/43 42 Package mechanical data 9.3 M24512-W M24512-R M24512-DF UFDFPN8 package information Figure 17. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline 3LQ,'PDUNLQJ Ğ ď >ϭ >ϯ WŝŶϭ Ϯ < > Ϯ ĞĞĞ ϭ =:B0(H9 2. Drawing is not to scale. 3. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. Table 20. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, 2 x 3 mm, data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.550 0.450 0.600 0.0217 0.0177 0.0236 A1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 D 2.000 1.900 2.100 0.0787 0.0748 0.0827 D2 – 1.200 1.600 – 0.0472 0.0630 E 3.000 2.900 3.100 0.1181 0.1142 0.1220 E2 – 1.200 1.600 – 0.0472 0.0630 e 0.500 – – 0.0197 – – K – 0.300 – – 0.0118 – L – 0.300 0.500 – 0.0118 0.0197 L1 – – 0.150 – – 0.0059 L3 – 0.300 – – 0.0118 – – 0.080 – – 0.0031 – eee (2) 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 36/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 9.4 Package mechanical data WLCSP package information Figure 18. M24512-DFCS6TP/K (WLCSP 8-bump wafer-level chip scale package) outline E BBB : $ /RIENTATION REFERENCE $ETAIL! % AAA 7AFERBACKSIDE E /RIENTATION REFERENCE 8 9 E ' & ! ! 8 E ! " # $ % "UMPSIDE 3IDEVIEW "UMP ! EEE : $ETAIL! ROTATEDBY : B 8 CCC- : 8 9 DDD- : 3EATINGPLANE #F?-%?6 1. Drawing is not to scale. Figure 19. M24512-DFCS6TP/K recommended footprint Ϭ͘ϰϯϯŵŵ Ϭ͘ϴϲϲŵŵ Ϭ͘ϱϬϬŵŵ ϭ͘ϬϬϬŵŵ ϴďƵŵƉƐdž TϬ͘ϮϳϬŵŵ ϭĨͺ&Wͺsϭ DocID16459 Rev 28 37/43 42 Package mechanical data M24512-W M24512-R M24512-DF Table 21. M24512-DFCS6TP/K (WLCSP 8-bump wafer-level chip scale package) related mechanical data Symbol inches(1) millimeters Typ Min Max Typ Min Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 - - 0.0075 - - A2 0.350 - - 0.0138 - - b 0.270 - - 0.0106 - - D 1.271 - 1.291 0.0500 - 0.0508 E 1.937 - 1.957 0.0763 - 0.0770 e 1.000 - - 0.0394 - - e1 0.866 - - 0.0341 - - e2 0.500 - - 0.0197 - - e3 0.433 - - 0.0170 - - F 0.202 - - 0.0080 - - G 0.469 - - 0.0185 - - N 8.000 - - 0.3150 - - aaa 0.110 - - 0.0043 - - bbb 0.110 - - 0.0043 - - ccc 0.110 - - 0.0043 - - ddd 0.060 - - 0.0024 - - eee 0.060 - - 0.0024 - - 1. Values in inches are converted from mm and rounded to four decimal digits. 38/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 10 Part numbering Part numbering Table 22. Ordering information scheme Example: M24512 -D W MC 6 T P /K Device type M24 = I2C serial access EEPROM Device function 512 = 512 Kbit (64 x 8 bit) Device family Blank = Without Identification page D = With Identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.5 V Package MN = SO8 (150 mil width)(1) DW = TSSOP8 (169 mil width)(1) MC = UFDFPN8 (MLP8)(1) CS = WLCSP(1) Device grade 6 = Industrial: device tested with standard test flow over –40 to 85 °C Option T = Tape and reel packing blank = tube packing Plating technology P or G = ECOPACK2® Process(2) /K = Manufacturing technology code 1. All package are ECOPACK2® (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants) 2. The process letters apply to WLCSP devices only. The process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information. DocID16459 Rev 28 39/43 42 Part numbering M24512-W M24512-R M24512-DF Table 23. Ordering information scheme (unsawn wafer)(1) Example: M24512 - D F K W 20 I / 90 Device type M24 = I2C serial access EEPROM Device function 512 = 512Kbit (64 K x 8 bit) Device family D = With Identification page Operating voltage F = VCC = 1.7 V to 5.5 V Process K = F8H Delivery form W = Unsawn wafer Wafer thickness 20 = Non-backlapped wafer Wafer testing I = Inkless test Device grade 90 = -40°C to 85°C 1. For all information concerning the M24512 delivered in unsawn wafer, please contact your nearest ST Sales Office. Engineering samples Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 40/43 DocID16459 Rev 28 M24512-W M24512-R M24512-DF 11 Revision history Revision history Table 24.Document revision history Date 31-Jan-2011 Revision 22 Changes Updated Table 7, Table 13, Table 16 and Table 17. Added note (2) to Table 14. Deleted Table 22: Available M24512-W and M24512-R products (package, voltage range, temperature grade) and Table 23: Available M24512-DR products (package, voltage range, temperature grade). – – – – – 01-Mar-2012 23 Deleted reference “M24512-DR” and inserted reference “M24512-DF”. Updated data regarding package UFDFPN8. Updated Section 1: Description. Added Figure 4 and updated title of Figure 3. Updated VESD value in Table 7: Absolute maximum ratings, note (1) under Table 13 and ICC value in Table 14. – Added Table 10: Operating conditions (voltage range F) and Table 15: DC characteristics (voltage range F). – Added values tWLDL and tDHWH in Table 16: 400 kHz AC characteristics and Table 17: 1 MHz AC characteristics. – Replaced Figure 14. 12-Apr-2012 24 Updated Section 1: Description. 25 Datasheet split into: – M24512-125 datasheet for automotive products (range 3), – M24512-W M24512-R M24512-DR M24512-DF for standard products (range 6, this datasheet rev 25). Deleted: – SO8W package – UFDFPN8 (MLP8): MB version package – WLCSP (KA die) dimensions Added: – Reference M24512-DR – Table 11: Cycling performance – Table 12: Memory cell data retention Updated: – Figure 12: Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz – Figure 13: Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz 26 Updated Section 5.2.2: Current Address Read. Modified Figure 3: WLCSP connections for the M24512-DFCS6TP/K (top view, marking side, with balls on the underside) and Figure 18: M24512DFCS6TP/K (WLCSP 8-bump wafer-level chip scale package) outline. 25-Jun-2012 17-Sep-2012 DocID16459 Rev 28 41/43 42 Revision history M24512-W M24512-R M24512-DF Table 24.Document revision history (continued) Date 16-Feb-2015 27-May-2015 42/43 Revision Changes 27 Removed: – Note on Figure 3 – Note 2 on Table 2 Updated: – Note 1 on Table 11 and Table 12 – Table 17 – Figure 11 – Table 20 – titles on Figure 18 and Table 21 – Table 22 – note 1 on Table 21 Added: – Note 2 on Table 11 – Note 4 and 5 on Table 13 – Note 6, 7 and 8 on Table 14 – Note 6, 7 on Table 15 – note 8 on Table 16 – Figure 19 – reference to Engineering sample after Ordering information scheme 28 Added: – Unsawn wafer reference on cover page and Table 23: Ordering information scheme (unsawn wafer) – Note 1 on Table 11 Removed ordering type M24512-DRxxxx from the whole document (device replaced by either M24512-Rxxx or M24512-DFxxx) DocID16459 Rev 28 M24512-W M24512-R M24512-DF IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID16459 Rev 28 43/43 43