R7985A - STMicroelectronics

R7985A
2 A step-down switching regulator for aerospace applications
Datasheet
- target specification
Applications
 Dedicated to aerospace applications
 Aerospace LED driving
Description
HSOP8 exposed pad
Features
 General features
– 2 A DC output current
– 4.5 V to 38 V input voltage
– Output voltage adjustable from 0.6 V
– Large ambient temperature range:
-40 °C to 125 °C
– 250 kHz switching frequency,
programmable up to 1 MHz
– Internal soft-start and enable
– Low dropout operation: 100% duty cycle
– Voltage feed-forward
– Zero load current operation
– Overcurrent and thermal protection
– HSOP8 package
The R7985A is a step-down switching regulator
with a 2.5 A (minimum) current limited embedded
power MOSFET, so it is able to deliver up to 2 A
current to the load depending on the application
conditions.
The input voltage can range from 4.5 V to 38 V,
while the output voltage can be set starting from
0.6 V to VIN.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz. The large ambient
temperature range makes it ideal for aerospace
and defense applications.
The HSOP8 package with exposed pad allows
the reduction of Rth(JA) down to 40 °C/W.
 Aerospace and defense features
– Suitable for use in aerospace and defense
applications
– Dedicated traceability and part marking
– Production parts approval documents
available
– Adapted extended life time and
obsolescence management
– Extended product change notification
process
– Designed and manufactured to meet subppm quality goals
– Advanced mold and frame designs for
superior resilience in harsh environments
(acceleration, EMI, thermal, humidity)
– Extended screening capability on request
October 2014
DocID026995 Rev 1
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/41
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Contents
R7985A
Contents
1
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
7
2/41
5.1
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5
Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4.1
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.2
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1
Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2
Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DocID026995 Rev 1
R7985A
Contents
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID026995 Rev 1
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41
List of tables
R7985A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
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Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input MLCC capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
HSOP8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID026995 Rev 1
R7985A
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sawtooth: voltage and frequency feed-forward; external synchronization . . . . . . . . . . . . . 12
Oscillator frequency vs. the FSW pin resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Soft-start scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
The error amplifier, the PWM modulator and the LC output filter . . . . . . . . . . . . . . . . . . . . 21
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Open loop gain: module Bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Open loop gain Bode diagram with ceramic output capacitor . . . . . . . . . . . . . . . . . . . . . . 25
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Open loop gain: module Bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Open loop gain Bode diagram with electrolytic/tantalum output capacitor . . . . . . . . . . . . . 29
Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Maximum output current according to max. DC switch current (2.0 A): VO = 12 V. . . . . . . 34
Inverting buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Maximum output current according to switch max. peak current (2.0 A): VO = -5 V. . . . . . 36
HSOP8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Pin settings
R7985A
1
Pin settings
1.1
Pin connection
Figure 1. Pin connection (top view)
1.2
Pin description
Table 1. Pin description
6/41
No.
Type
1
OUT
Description
Regulator output.
2
SYNCH
Master/slave synchronization. When it is left floating, a signal with
a phase shift of half a period in respect to the power turn-on is present at
the pin. When connected to an external signal at a frequency higher than
the internal one, the device is synchronized by the external signal, with
zero phase shift.
Connecting together the SYNCH pins of two devices, the one with the
higher frequency works as master and the other as slave; so the two
power turn-ons have a phase shift of half a period.
3
EN
A logical signal (active high) enables the device. With EN higher than
1.2 V the device is ON and with EN lower than 0.63 V the device is OFF.
4
COMP
5
FB
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from VOUT to the FB pin.
6
FSW
The switching frequency can be increased connecting an external
resistor from the FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250 KHz.
7
GND
Ground.
8
VCC
Unregulated DC input voltage.
Error amplifier output to be used for loop frequency compensation.
DocID026995 Rev 1
R7985A
Maximum ratings
2
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
Vcc
OUT
Value
Input voltage
Unit
45
Output DC voltage
-0.3 to VCC
FSW, COMP, SYNCH
Analog pin
-0.3 to 4
EN
Enable pin
-0.3 to VCC
FB
Feedback voltage
-0.3 to 1.5
PTOT
3
Parameter
Power dissipation at TA < 60 °C
HSOP8
V
2
W
TJ
Junction temperature range
-40 to 150
°C
Tstg
Storage temperature range
-55 to 150
°C
Value
Unit
40
°C/W
Thermal data
Table 3. Thermal data
Symbol
Rth(JA)
Parameter
Maximum thermal resistance junction
ambient(1)
HSOP8
1. Package mounted on demonstration board.
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Electrical characteristics
4
R7985A
Electrical characteristics
TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Values
Symbol
Parameter
Test conditions
Unit
Min.
VCC
Operating input voltage range
VCCON
Turn-on VCC threshold
VCCHYS
VCC UVLO hysteresis
RDS(on)
MOSFET on-resistance
4.5
Max.
38
4.5
0.1
2.5
FSW
Switching frequency
210
VFSW
FSW pin voltage
V
0.4
200
Maximum limiting current
ILIM
Typ.
400
m
3.5
A
275
kHz
Oscillator
D
FADJ
250
1.254
Duty cycle
0
Adjustable switching frequency
RFSW = 33 k
V
100
1000
%
kHz
Dynamic characteristics
VFB
Feedback voltage
4.5 V < VCC < 38 V
0.588
0.6
0.612
V
2.4
mA
30
A
DC characteristics
IQ
IQST-BY
Quiescent current
Duty cycle = 0, VFB = 0.8 V
Total standby quiescent current
20
Enable
VEN
EN threshold voltage
IEN
EN current
Device OFF level
Device ON level
0.3
1.2
EN = VCC
7.5
10
8.2
9.8
V
µA
Soft-start
TSS
Soft-start duration
FSW pin floating
7.3
FSW = 1 MHz, RFSW = 33 k
2
ms
Error amplifier
VCH
High level output voltage
VFB < 0.6 V
VCL
Low level output voltage
VFB > 0.6 V
Source COMP pin
VFB = 0.5 V, VCOMP = 1 V
19
mA
Sink COMP pin
VFB = 0.7 V, VCOMP = 0.75 V
30
mA
Open loop voltage gain
(1)
100
dB
IO SOURCE
IO SINK
GV
8/41
DocID026995 Rev 1
3
0.1
V
R7985A
Electrical characteristics
Table 4. Electrical characteristics (continued)
Values
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
Synchronization function
VS_IN,HI
High input voltage
2
VS_IN,LO
Low input voltage
tS_IN_PW
Input pulse width
ISYNCH,LO
Slave sink current
VSYNCH = 2.9 V
VS_OUT,HI
Master output amplitude
ISOURCE = 4.5 mA
tS_OUT_PW
Output pulse width
SYNCH floating
3.3
1
VS_IN,HI = 3 V, VS_IN,LO = 0 V
100
VS_IN,HI = 2 V, VS_IN,LO = 1 V
300
V
ns
0.7
2
1
mA
V
110
ns
Protection
TSHDN
Thermal shutdown
150
Hysteresis
30
°C
1. Guaranteed by design.
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Functional description
5
R7985A
Functional description
The R7985A device is based on a “voltage mode”, constant frequency control. The output
voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V)
providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and
OFF time of the power switch.
The main internal blocks are shown in the block diagram in Figure 2. They are:

A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed-forward are implemented

Soft-start circuitry to limit inrush current during the startup phase

Voltage mode error amplifier

Pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch

High-side driver for embedded P-channel power MOSFET switch

Peak current limit sensing block, to handle overload and short-circuit conditions

A voltage regulator and internal reference. It supplies internal circuitry and provides
a fixed internal reference

A voltage monitor circuitry (UVLO) that checks the input and internal voltages

A thermal shutdown block, to prevent thermal runaway.
Figure 2. Block diagram
VCC
REGULATOR
TRIMMING
EN
&
BANDGAP
EN
1.254V
3.3V
0.6V
COMP
UVLO
PEAK
CURRENT
LIMIT
THERMAL
SOFTSTART
SHUTDOWN
E/A
PWM
DRIVER
S
Q
R
OUT
OSCILLATOR
FB
10/41
FSW
GND
DocID026995 Rev 1
SYNCH
&
PHASE SHIFT
SYNCH
R7985A
5.1
Functional description
Oscillator and synchronization
Figure 3 shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock. Its frequency depends on the resistor externally connected to
the FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as
shown in Figure 5 by an external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 4.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way, a frequency feed-forward is implemented (Figure 4.b) in order
to keep the PWM gain constant versus the switching frequency (see Section 6.4 on page 21
for PWM gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180 ° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with the
higher oscillator frequency works as master, so the slave device switches at the frequency
of the master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor (see the L5988D datasheet).
Figure 3. Oscillator circuit block diagram
Clock
FSW
Clock
Generator
Synchronization
SYNCH
Ramp
Generator
Sawtooth
The device can be synchronized to work at a higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 4.c). This change must be taken into account when the loop stability is studied. To
minimize the change of the PWM gain, the free-running frequency should be set (with
a resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render negligible the
truncation of sawtooth, due to the external synchronization.
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41
Functional description
R7985A
Figure 4. Sawtooth: voltage and frequency feed-forward; external synchronization
Figure 5. Oscillator frequency vs. the FSW pin resistor
)6:>N+]@
5)6:>N2KPV@
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R7985A
Functional description
where:
Equation 1
9
28.5  10
3
R FSW = -----------------------------------------3 – 3.23  10
F SW – 250  10
FSW is desired switching frequency.
5.2
Soft-start
Soft-start is essential to assure the correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monothonically.
The soft-start is performed by a staircase ramp on the non inverting input (VREF) of the error
amplifier. So the output voltage slew rate is:
Equation 2
R1
SR OUT = SR VREF   1 + --------

R2
where SRVREF is the slew rate of the non inverting input, while R1and R2 is the resistor
divider to regulate the output voltage (see Figure 6). The soft-start staircase consists of
64 steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles.
So the soft-start time and then the output voltage slew rate depend on the switching
frequency.
Figure 6. Soft-start scheme
Soft-start time results:
Equation 3
32  64
SS TIME = ----------------Fsw
For example, with a switching frequency of 250 kHz, the SSTIME is 8 ms.
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Functional description
5.3
R7985A
Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier, so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are shown in Table 5.
Table 5. Uncompensated error amplifier characteristics
Parameter
Value
Low frequency gain
100 dB
GBWP
4.5 MHz
Slew rate
7 V/s
Output voltage swing
0 to 3.3 V
Maximum source/sink current
17 mA/25 mA
In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter, a Type II compensation network can be used. Otherwise, a Type
III compensation network must be used (see Section 6.4 on page 21 for details of the
compensation network selection).
The methodology to compensate the loop is to introduce zeroes to obtain a safe phase
margin.
5.4
Overcurrent protection
The R7985A implements the overcurrent protection sensing current flowing through the
power MOSFET. Due to the noise created by the switching activity of the power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids
an erroneous detection of a fault condition. This interval is generally known as “masking
time” or “blanking time”. The masking time is about 200 ns.
If the overcurrent limit is reached, the power MOSFET is turned off, implementing the pulseby-pulse overcurrent protection. Under an overcurrent condition, the device can skip turn-on
pulses in order to keep the output current constant and equal to the current limit. If, at the
end of the “masking time”, the current is higher than the overcurrent threshold, the power
MOSFET is turned off and one pulse is skipped. If, at the following switching-on, when the
“masking time” ends, the current is still higher than the overcurrent threshold, the device
skips two pulses. This mechanism is repeated and the device can skip up to seven pulses.
While, if at the end of the “masking time” the current is lower than the over current threshold,
the number of skipped cycles is decreased by one unit (see Figure 7).
So the overcurrent/short-circuit protection acts by switching off the power MOSFET and
reducing the switching frequency down to one eighth of the default switching frequency, in
order to keep constant the output current around the current limit.
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R7985A
Functional description
This kind of overcurrent protection is effective if the output current is limited. To prevent the
current from diverging, the current ripple in the inductor during the ON-time must not be
higher than the current ripple during the OFF-time. That is:
Equation 4
V IN – V OUT – R DSON  I OUT – DCR  I OUT
V OUT + V F + R DSON  I OUT + DCR  I OUT
------------------------------------------------------------------------------------------------------------  D = -----------------------------------------------------------------------------------------------------------   1 – D 
L  F SW
L  F SW
If the output voltage is shorted, VOUT 0, IOUT = ILIM, D/FSW = TON_MIN, (1-D)/FSW 1/FSW.
So from the above equation the maximum switching frequency that guarantees to limit the
current results:
Equation 5
 V F + DCR  I LIM 
1
F *SW = -------------------------------------------------------------------------------  --------------------- V IN –  R DSON + DCR   I LIM  T ON_MIN
With RDS(on) = 300 m, DRC = 0.08 , the worst condition is with VIN = 38 V, ILIM = 2.5 A;
the maximum frequency to keep the output current limited during the short-circuit results
74 kHz.
Based on the pulse-by-pulse mechanism, that reduces the switching frequency down to one
eighth, the maximum FSW, adjusted by the FSW pin, that assures a full effective output
current limitation is 74 kHz * 8 = 592 kHz.
If, with VIN = 38 V, the switching frequency is set higher than 592 kHz, during short-circuit
condition the system finds a different equilibrium with higher current. For example, with
FSW = 700 kHz and the output shorted to ground, the output current is limited around:
Equation 6
V IN  F *SW – V F  T ON_MIN
I OUT = ---------------------------------------------------------------------------------------------------------------- = 3.68A
 DRC  T ON_MIN  +  R DSON + DCR   F *SW
where FSW* is 700 kHz divided by eight.
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Functional description
R7985A
Figure 7. Overcurrent protection
5.5
Enable function
The enable feature allows the device to be put into standby mode. With the EN pin lower
than 0.3 V, the device is disabled and the power consumption is reduced to less than 30A.
With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an
internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also VCC compatible.
5.6
Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature goes back to about 120 °C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, so ensuring an accurate and fast temperature detection.
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R7985A
6
Application information
Application information
Figure 8. Application circuit
6.1
Input capacitor selection
The capacitor connected to the input must be capable of supporting the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 7
2
2
2D
D
I RMS = I O  D – --------------- + ------2

where Io is the maximum DC output current, D is the duty cycle, is the efficiency.
Considering = 1, this function has a maximum at D = 0.5 and it is equal to Io/2.
In a specific application the range of possible duty cycles must be considered in order to find
out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 8
V OUT + V F
D MAX = ------------------------------------V INMIN – V SW
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41
Application information
R7985A
and
Equation 9
V OUT + V F
D MIN = -------------------------------------V INMAX – V SW
where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across
the internal PDMOS.
The peak-to-peak voltage across the input capacitor can be calculated as:
Equation 10
IO
D
D
V PP = -------------------------   1 – ----  D + ----   1 – D  + ESR  I O
C IN  F SW 


where ESR is the equivalent series resistance of the capacitor.
Given the physical dimension, ceramic capacitors can well meet the requirements of the
input filter sustaining a higher input RMS current than electrolytic/tantalum types.
In this case, the equation of CIN as a function of the target VPP can be written as follows:
Equation 11
IO
D
D
C IN = ---------------------------   1 – ----  D + ----   1 – D 
V PP  F SW 


neglecting the small ESR of ceramic capacitors.
Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum
peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is:
Equation 12
IO
C IN_MIN = -----------------------------------------------2  V PP_MAX  F SW
Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage in the order of 1%
of VINMAX.
In Table 6, some multi-layer ceramic capacitors suitable for this device are reported.
Table 6. Input MLCC capacitors
Manufacturer
Taiyo Yuden
muRata
Series
Cap value (F)
Rated voltage (V)
UMK325BJ106MM-T
10
50
GMK325BJ106MN-T
10
35
GRM32ER71H475K
4.7
50
A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that
additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability
on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.
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R7985A
6.2
Application information
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple must be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
In continuous current mode (CCM), the inductance value can be calculated by the following
equation:
Equation 13
V IN – V OUT
V OUT + V F
I L = ------------------------------  T ON = ----------------------------  T OFF
L
L
where TON is the conduction time of the internal high-side switch and TOFF is the conduction
time of the external diode [in CCM, FSW = 1/(TON + TOFF)]. The maximum current ripple, at
fixed VOUT, is obtained at maximum TOFF, that is at minimum duty cycle (see Section 6.1 to
calculate minimum duty). So by fixing IL = 20% to 30% of the maximum output current, the
minimum inductance value can be calculated:
Equation 14
V OUT + V F 1 – D MIN
L MIN = ----------------------------  ----------------------I MAX
F SW
where FSW is the switching frequency, 1/(TON + TOFF).
For example, for VOUT = 5 V, VIN = 24 V, IO = 2 A and FSW = 250 kHz, the minimum
inductance value to have IL= 30% of IO is about 28 H.
The peak current through the inductor is given by:
Equation 15
I L
I L PK = I O + -------2
So if the inductor value decreases, then the peak current (that must be lower than the
minimum current limit of the device) increases. According to the maximum DC output
current for this product family (2 A), the higher the inductor value, the higher the average
output current that can be delivered, without triggering the overcurrent protection.
In Table 7 some inductor part numbers are listed.
Table 7. Inductors
Manufacturer
Coilcraft
Wurth
SUMIDA
Series
Inductor value (H)
Saturation current (A)
MSS1038
3.8 to 10
3.9 to 6.5
MSS1048
12 to 22
3.84 to 5.34
PD Type L
8.2 to 15
3.75 to 6.25
PD Type M
2.2 to 4.7
4 to 6
CDRH6D226/HP
1.5 to 3.3
3.6 to 5.2
CDR10D48MN
6.6 to 12
4.1 to 5.7
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Application information
6.3
R7985A
Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge or discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Equation 16
I MAX
V OUT = ESR  I MAX + ------------------------------------8  C OUT  f SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Section 6.4, how to consider its effect in the system stability is
illustrated.
For example, with VOUT = 5 V, VIN = 24 V, IL = 0.9 A (resulting by the inductor value), in
order to have a VOUT = 0.01 · VOUT, if the multi-layer ceramic capacitors are adopted,
10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In case
of not-negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value. So, in the case of 330 µF with ESR = 70 mthe resistive
component of the drop dominates and the voltage ripple is 43 mV
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application, the output capacitor and system bandwidth
must be chosen in order to sustain the load transient.
In Table 8 below some capacitor series are listed.
Table 8. Output capacitors
Manufacturer
Series
Cap value (F)
Rated voltage (V)
ESR (m)
GRM32
22 to 100
6.3 to 25
<5
GRM31
10 to 47
6.3 to 25
<5
ECJ
10 to 22
6.3
<5
EEFCD
10 to 68
6.3
15 to 55
SANYO
TPA/B/C
100 to 470
4 to 16
40 to 80
TDK
C3225
22 to 100
6.3
<5
muRata
PANASONIC
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6.4
Application information
Compensation network
The compensation network must assure stability and good dynamic performance. The loop
of the R7985A is based on the voltage mode control. The error amplifier is
a voltage operational amplifier with high bandwidth. So by selecting the compensation
network the E/A is considered as ideal, that is, its bandwidth is much larger than the system
one.
The transfer functions of the PWM modulator and the output LC filter are studied (see
Figure 10). The transfer function of the PWM modulator, from the error amplifier output
(COMP pin) to the OUT pin, results:
Equation 17
V IN
G PW0 = --------Vs
where VS is the sawtooth amplitude. As seen in Section 5.1 on page 11, the voltage feedforward generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 18
V S = K  V IN
In this way the PWM modulator gain results constant and equal to:
Equation 19
V IN
1
G PW0 = --------- = ---- = 18
Vs
K
The synchronization of the device with an external clock provided through the SYNCH pin
can modify the PWM modulator gain (see Section 5.1 on page 11 to understand how this
gain changes and how to keep it constant in spite of the external synchronization).
Figure 9. The error amplifier, the PWM modulator and the LC output filter
VCC
VS
VREF
FB
PWM
E/A
OUT
COMP
L
ESR
GPW0
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COUT
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Application information
R7985A
The transfer function on the LC filter is given by:
Equation 20
s
1 + -------------------------2  f zESR
G LC  s  = ------------------------------------------------------------------------2s
s
1 + ---------------------------- +  -------------------
2  f LC
2  Q  f LC
where:
Equation 21
1
f LC = ------------------------------------------------------------------------
ESR
2  L  C OUT  1 + --------------R OUT
1
f zESR = -------------------------------------------2  ESR  C OUT
Equation 22
R OUT  L  C OUT   R OUT + ESR 
Q = ------------------------------------------------------------------------------------------ ,
L + C OUT  R OUT  E SR
V OUT
R OUT = -------------I OUT
As seen in Section 5.3 on page 14, two different kinds of network can compensate the loop.
In the two following paragraphs the guidelines to select the Type II and Type III
compensation network are illustrated.
6.4.1
Type III compensation network
The methodology to stabilize the loop consists in placing two zeroes to compensate the
effect of the LC double pole, thereby increasing phase margin; then to place one pole in the
origin to minimize the DC error on the regulated output voltage; finally to place other poles
far from the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency higher than the desired bandwidth (that is: 2ESR COUT < 1 / BW), the Type
III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (< 1 m), with very high frequency zero, so a Type III network is adopted to
compensate the loop.
In Figure 10, the Type III compensation network is shown. This network introduces two
zeroes (fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:
Equation 23
1
f Z1 = ------------------------------------------------
2  C 3   R 1 + R 3 
1
f Z2 = -----------------------------2  R 4  C 4
Equation 24
f P0 = 0
22/41
1
f P1 = ------------------------------
2  R 3  C 3
DocID026995 Rev 1
1
f P2 = -------------------------------------------C4  C5
2  R 4  -------------------C4 + C5
R7985A
Application information
Figure 10. Type III compensation network
In Figure 11 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]
and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)] are drawn.
Figure 11. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1.
Choose a value for R1, usually between 1 k and 5 k.
2.
Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 25
BW
R 4 = ----------  K  R 1
f LC
where K is the feed-forward constant and 1/K is equal to 18.
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Application information
3.
R7985A
Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC):
Equation 26
1
C 4 = --------------------------  R 4  f LC
4.
Calculate C5 by placing the second pole at four times the system bandwidth (BW):
Equation 27
C4
C 5 = -------------------------------------------------------------2  R 4  C 4  4  BW – 1
5.
Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:
Equation 28
R1
R 3 = ---------------------------
4  BW
----------------- – 1
f LC
1
C 3 = ----------------------------------------2  R 3  4  BW
The suggested maximum system bandwidth is equal to the switching frequency divided by
3.5 (FSW/3.5), so lower than 100 kHz if the FSW is set higher than 500 kHz.
For example, with VOUT = 5 V, VIN = 24 V, IO = 2 A, L = 22 H, COUT = 22 F, and
ESR < 1 m, the Type III compensation network is:
Equation 29
R 1 = 4.99k
R 2 = 680 R 3 = 270 R 4 = 1.1k
C 3 = 4.7nF
C 4 = 47nF
C 5 = 1pF
In Figure 12 the module and phase of the open loop gain is shown. The bandwidth is about
32 kHz and the phase margin is 51°.
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R7985A
Application information
Figure 12. Open loop gain Bode diagram with ceramic output capacitor
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Application information
6.4.2
R7985A
Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency lower than the desired bandwidth (that is: 2ESR COUT > 1 / BW), this zero
helps stabilize the loop. Electrolytic capacitors show not-negligible ESR (> 30 m), so with
this kind of output capacitor the Type II network combined with the zero of the ESR allows
the stabilizing of the loop.
In Figure 13 the Type II network is shown.
Figure 13. Type II compensation network
The singularities of the network are:
Equation 30
1
f Z1 = ------------------------------
2  R 4  C 4
26/41
f P0 = 0
DocID026995 Rev 1
1
f P1 = -------------------------------------------C4  C5
2  R 4  -------------------C4 + C5
R7985A
Application information
In Figure 14 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]
and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)] are drawn.
Figure 14. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1.
Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2.
Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 31
f ESR 2 BW V S
R 4 =  ------------  ------------  ---------  R 1
 f LC  f ESR V IN
where fESR is the ESR zero:
Equation 32
1
f ESR = -------------------------------------------2  ESR  C OUT
and VS is the sawtooth amplitude. The voltage feed-forward keeps the ratio VS/VIN constant.
3.
Calculate C4 by placing the zero one decade below the output filter double pole:
Equation 33
10
C 4 = ------------------------------2  R 4  f LC
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41
Application information
4.
R7985A
Then calculate C3 in order to place the second pole at four times the system bandwidth
(BW):
Equation 34
C4
C 5 = -------------------------------------------------------------2  R 4  C 4  4  BW – 1
For example, with VOUT = 5 V, VIN = 24 V, IO = 2 A, L = 22 H, COUT = 330 F, and
ESR = 70 m the Type II compensation network is:
Equation 35
R 1 = 1.1k
28/41
R 2 = 150
R 4 = 4.99k
DocID026995 Rev 1
C 4 = 180nF
C 5 = 180pF
R7985A
Application information
In Figure 15 the module and phase of the open loop gain is shown. The bandwidth is about
36 kHz and the phase margin is 53 °.
Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor
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Application information
6.5
R7985A
Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if the junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a)
conduction losses due to the not-negligible RDS(on) of the power switch; these are
equal to:
Equation 36
2
P ON = R DS  on    I OUT   D
where D is the duty cycle of the application and the maximum RDS(on) overtemperature is
220 m. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN,
but actually it is quite higher to compensate the losses of the regulator. So the conduction
losses increase compared with the ideal case.
b)
switching losses due to power MOSFET turn-on and turn-off; these can be
calculated as:
Equation 37
 T RISE + T FALL 
P SW = V IN  I OUT  -------------------------------------------  Fsw = V IN  I OUT  T SW  F SW
2
where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS)
and the current flowing into it during turn-on and turn-off phases, as shown in Figure 16.
TSW is the equivalent switching time. For this device the typical value for the equivalent
switching time is 40 ns.
c)
Quiescent current losses, calculated as:
Equation 38
P Q = V IN  I Q
where IQ is the quiescent current (IQ = 2.4 mA).
The junction temperature TJ can be calculated as:
Equation 39
T J = T A + Rth JA  P TOT
where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
Rth(JA) is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The Rth(JA) measured on the demonstration board described in the following
paragraph is about 40 °C/W for the HSOP8 package.
30/41
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Application information
Figure 16. Switching losses
6.6
Layout considerations
The PC board layout of the switching DC/DC regulator is very important to minimize the
noise injected in high impedance nodes and interference generated by the high switching
current loops.
In a step-down converter, the input loop (including the input capacitor, the power MOSFET
and the freewheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current is flowing through it. In order to minimize the EMI, this loop must be as
short as possible.
The feedback pin (FB) connection to the external resistor divider is a high impedance node,
so the interference can be minimized by placing the routing of the feedback node as far as
possible from the high current paths. To reduce the pick-up noise, the resistor divider must
be placed very close to the device.
To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as
close as possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.
DocID026995 Rev 1
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41
Application information
R7985A
In Figure 17 a layout example is shown.
Figure 17. Layout example
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Application ideas
7
Application ideas
7.1
Positive buck-boost
The R7985A can implement the step-up/down converter with a positive output voltage.
Figure 18 shows the schematic: one power MOSFET and one Schottky diode are added to
the standard buck topology to provide a 12 V output voltage with input voltage from 4.5 V to
38 V.
Figure 18. Positive buck-boost regulator
The relationship between input and output voltage is:
Equation 40
D
V OUT = V IN  ------------1–D
so the duty cycle is:
Equation 41
V OUT
D = -----------------------------V OUT + V IN
The output voltage isn’t limited by the maximum operating voltage of the device (38 V),
because the output voltage is sensed only through the resistor divider. The external power
MOSFET maximum drain to source voltage, must be higher than output voltage; the
maximum gate to source voltage must be higher than the input voltage (in Figure 18, if VIN is
higher than 16 V, the gate must be protected through a Zener diode and resistor).
The current flowing through the internal power MOSFET is transferred to the load only
during the OFF time, so according to the maximum DC switch current (2.0 A), the maximum
output current for the buck boost topology can be calculated from Equation 42.
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41
Application ideas
R7985A
Equation 42
I OUT
I SW = -------------  2 A
1–D
where ISW is the average current in the embedded power MOSFET in the ON time.
To chose the right value of the inductor and to manage transient output current, which, for
a short time, can exceed the maximum output current calculated by Equation 42, also the
peak current in the power MOSFET must be calculated. The peak current, shown in
Equation 43, must be lower than the minimum current limit (2.5 A).
Equation 43
I OUT
r
I SW,PK = -------------  1 + ---  3.7A
1–D
2
where r is defined as the ratio between the inductor current ripple and the inductor DC
current.
Therefore, in the buck boost topology the maximum output current depends on the
application conditions (firstly input and output voltage, secondly switching frequency and
inductor value).
In Figure 19 the maximum output current for the above configuration is depicted, varying the
input voltage from 4.5 V to 38 V.
The dashed line considers a more accurate estimation of the duty cycles given Equation 44,
where power losses across diodes, the external power MOSFET, and the internal power
MOSFET are taken into account.
Figure 19. Maximum output current according to max. DC switch current (2.0 A):
VO = 12 V
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Application ideas
Equation 44
V OUT + 2  V D
D = -------------------------------------------------------------------------------------------V IN – V SW – V SWE + V OUT + 2  V D
where VD is the voltage drop across the diodes, VSW and VSWE across the internal and
external power MOSFET.
7.2
Inverting buck-boost
The R7985A device can implement the step-up/down converter with a negative output
voltage.
Figure 18 shows the schematic to regulate -5 V: no further external components are added
to the standard buck topology.
The relationship between input and output voltage is:
Equation 45
D
V OUT = – V IN  ------------1–D
so the duty cycle is:
Equation 46
V OUT
D = -----------------------------V OUT – V IN
As in the positive one, in the inverting buck-boost the current flowing through the power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (2.0 A), the maximum output current can be calculated from Equation 42,
where the duty cycle is given by Equation 46.
Figure 20. Inverting buck-boost regulator
The GND pin of the device is connected to the output voltage so, given the output voltage,
the input voltage range is limited by the maximum voltage the device can withstand across
VCC and GND (38 V). Therefore, if the output is -5 V, the input voltage can range from 4.5 V
to 33 V.
DocID026995 Rev 1
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41
Application ideas
R7985A
As in the positive buck-boost, the maximum output current according to application
conditions is shown in Figure 21. The dashed line considers a more accurate estimation of
the duty cycles given by Equation 47, where power losses across diodes and the internal
power MOSFET are taken into account.
Equation 47
V OUT – V D
D = ----------------------------------------------------------------– V IN – V SW + V OUT – V D
Figure 21. Maximum output current according to switch max. peak current (2.0 A):
VO = -5 V
36/41
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8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 22. HSOP8 package outline
' PP7\S
( PP7\S
$0Y
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41
Package information
R7985A
Table 9. HSOP8 package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
A
1.70
A1
0.00
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
4.80
4.90
5.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
0.150
1.27
h
0.25
0.50
L
0.40
1.27
k
0.00
8.00
ccc
38/41
Max.
0.10
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Ordering information
Ordering information
Table 10. Ordering information
Order code
Package
Packaging
R7985A
HSOP8
Tube
R7985ATR
HSOP8
Tape and reel
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Revision history
10
R7985A
Revision history
Table 11. Document revision history
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Date
Revision
06-Oct-2014
1
Changes
Initial release.
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