ST1S40 3 A DC step-down switching regulator Features ■ 3 A DC output current ■ 4.0 V to 18 V input voltage ■ Output voltage adjustable from 0.8 V ■ 850 kHz switching frequency ■ Internal soft-start ■ Integrated 95 mΩ and 69 mΩ Power MOSFETs ■ All ceramic capacitor ■ Enable ■ Cycle-by-cycle current limiting ■ Current fold back short-circuit protection ■ VFQFPN4x4-8L, HSOP-8, and SO-8 and packages SO8 Description Applications ■ μP/ASIC/DSP/FPGA core and I/O supplies ■ Point of load for: STB, TVs, DVD ■ Optical storage, hard disk drive, printers, audio/graphic cards Figure 1. VFQFPN 4x4 The ST1S40 is an internally compensated 850 kHz fixed-frequency PWM synchronous stepdown regulator. ST1S40 operates from 4.0 V to 18 V input, while it regulates an output voltage as low as 0.8 V and up to VIN. The ST1S40 integrates a 95 mΩ high side switch and 69 mΩ synchronous rectifier allowing very high efficiency with very low output voltages. The peak current mode control with internal compensation delivers a very compact solution with a minimum component count. The ST1S40 is available in VFQFPN 4 mm x 4 mm 8 lead package, HSOP-8 and standard SO-8. Application circuit / + 9,1 9 9,16: 92879 6: 9,1$ &LQBD (13* 5 676, ± ) )% &LQBVZ &RXW 3*1'$*1'H3DG ) March 2012 Doc ID 17928 Rev 4 5 ) 1/30 www.st.com 30 Contents ST1S40 Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 5.1 Internal soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5 Layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/30 Doc ID 17928 Rev 4 ST1S40 Pin settings 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) VINA 1 8 PGND EN 2 7 FB 3 GND 4 9 1 VINA 1 8 PGND SW EN 2 7 SW 6 VINSW FB 3 6 VINSW 5 NC GND 4 5 NC VFQFPN 9 HSOP8 1.2 Pin description Table 1. Pin description 8 SW VINSW PGND GND VINA EN AGND 4 5 FB SO8-BW No. VFQFPN S08-BW and HSOP8 Type Description 1 3 VINA 2 4 EN Enable input. With EN higher than 1.2 V the device in ON and with EN lower than 0.4 V the device is OFF (ST1S40Ixx). 3 5 FB Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.8 V. To have higher regulated voltages an external resistor divider is required from Vout to the FB pin. 4 6 5 - 6 8 7 1 8 2 - 7 9 - Unregulated DC input voltage AGND Ground NC It can be connected to ground VINSW Power input voltage SW Regulator output switching pin PGND Power ground Ground ePad Exposed pad mandatory connected to ground Doc ID 17928 Rev 4 3/30 Maximum ratings 2 ST1S40 Maximum ratings Table 2. Absolute maximum ratings Symbol VINSW 3 Parameter Power input voltage -0.3 to 20 VINA Input voltage -0.3 to 20 VEN Enable voltage VSW Output switching voltage VFB Feedback voltage IFB FB current -0.3 to VINA Unit V -1 to VIN -0.3 to 2.5 -1 to +1 mA 2.25 (HSOP8/DFN4x4); 1.6 SO8-BW W PTOT Power dissipation at TA < 60 °C TOP Operating junction temperature range -40 to 150 °C Tstg Storage temperature range -55 to 150 °C Thermal data Table 3. Symbol RthJA Thermal data Parameter Maximum thermal resistance junction-ambient 1. Package mounted on demonstration board. 4/30 Value Doc ID 17928 Rev 4 Value (1) VFQFPN 40 HSOP8 40 SO8-BW 55 Unit °C/W ST1S40 4 Electrical characteristics Electrical characteristics TJ=25 °C, VCC=12 V, unless otherwise specified. Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min. Typ. VIN Operating input voltage range (1) VINON Turn-on VCC threshold (1) 2.9 VINHYS Threshold hysteresis (1) 0.250 RDSON-P High side switch ON resistance ISW=750 mA 95 RDSON-N Low side switch ON resistance ISW=750 mA 69 4 Maximum limiting current (2) 4.0 FSW Switching frequency 0.7 DMAX Maximum duty cycle ILIM Max. 18 V mΩ mΩ 6.0 A 1 MHz Oscillator (2) 0.85 100 % Dynamic characteristics VFB Feedback voltage (1) 0.784 0.8 0.816 0.776 0.8 0.824 V %VOUT/ ΔIOUT Reference load regulation Isw=10 mA to ILIM (2) 0.5 % %VOUT/ ΔVIN Reference line regulation VIN= 4.0 V to 18 V (2) 0.4 % DC characteristics IQ IQST-BY IFB Quiescent current Duty cycle=0, no load VFB=1.2 V Total standby quiescent current OFF FB bias current 1.5 2.5 mA 2 15 μA 50 Enable Device ON level VEN EN threshold voltage IEN EN current 1.2 V Device OFF level 0.4 2 Doc ID 17928 Rev 4 μA 5/30 Electrical characteristics Table 4. ST1S40 Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min. Typ. Max. Soft start TSS Soft-start duration 1 Thermal shutdown 150 Hysteresis 15 ms Protection TSHDN °C 1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design. 6/30 Doc ID 17928 Rev 4 ST1S40 5 Functional description Functional description The ST1S40 is based on a “peak current mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.8 V) providing an error signal that, compared to the output of the current sense amplifier, controls the ON and OFF time of the power switch. The main internal blocks are shown in the block diagram in Figure 3. They are: ● A fully integrated oscillator that provides the internal clock and the ramp for the slope compensation avoiding sub-harmonic instability ● The soft-start circuitry to limit inrush current during the startup phase ● The transconductance error amplifier with integrated compensation network ● The pulse width modulator and the relative logic circuitry necessary to drive the internal power switches ● The drivers for embedded P-channel and N-channel Power MOSFET switches ● The high side current sensing block ● The low side current sense to implement diode emulation ● A voltage monitor circuitry (UVLO) that checks the input and internal voltages ● A thermal shutdown block, to prevent thermal run-away. Figure 3. Block diagram VINA VINSW OCP REF OSC I2V COMP I_SENSE RSENSE REGULATOR UVLO OCP Vdrv_p MOSFET CONTROL LOGIC Vsum COMP DRIVER Vdrv_n Vc SW OTP DMD E/A SHUT-DOWN DRIVER SOFTSTART 0.8V FB 5.1 EN GNDA GNDP Internal soft-start The soft-start is essential to assure correct and safe startup of the step-down converter. It avoids inrush current surge and causes the output voltage to increase monothonically. Doc ID 17928 Rev 4 7/30 Functional description ST1S40 The soft-start is performed by ramping the non-inverting input (VREF) of the error amplifier from 0 V to 0.8 V in around 1 ms. 5.2 Error amplifier and control loop stability The error amplifier compares the FB pin voltage with the internal 0.8 V reference and it provides the error signal to be compared with the output of the current sense circuitry, that is the high side Power MOSFET current. Comparing the output of the error amplifier and the peak inductor current implements the peak current mode control loop. The error amplifier is a transconductance amplifier (OTA). The uncompensated characteristics are listed inTable 5. Table 5. Error amplifier characteristics DC Gain 95 dB Gm 251 µA/V Ro 240 MΩ The ST1S40 embeds the compensation network that assures the stability of the loop in the whole operating range. All the tools needed to check the loop stability are shown below. Figure 4. shows the simple small signal model for the peak current mode control loop. Figure 4. Block diagram of the loop for the small signal analysis VIN GCO(s) Slope Compensation High side Switch L Current sense Logic And Driver VOUT GDIV (s) Cout Low side Switch PWM comparator 0.8V R1 VC Rc VFB Error Amp R2 Cc G EA(s) 8/30 Doc ID 17928 Rev 4 ST1S40 Functional description Three main terms can be identified to obtain the loop transfer function: 1. from control (output of E/A) to output, GCO(s) 2. from output (Vout) to the FB pin, GDIV(s) 3. from the FB pin to control (output of E/A), GEA(s). The transfer function from control to output GCO(s) results: Equation 1 s 1 + ---- ω z R LOAD 1 G CO ( s ) = ------------------ ⋅ --------------------------------------------------------------------------------------------- ⋅ ---------------------- ⋅ F H ( s ) R out ⋅ T SW Ri s ------ 1 + ---------------------------- ⋅ [ m C ⋅ ( 1 – D ) – 0,5 ] 1 + ω L p where RLOAD represents the load resistance, Ri (0.3 Ω) the equivalent sensing resistor of the current sense circuitry, ωp the single pole introduced by the LC filter and ωz the zero given by the ESR of the output capacitor. FH(s) accounts for the sampling effect performed by the PWM comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. Equation 2 1 ω Z = ------------------------------ESR ⋅ C OUT Equation 3 m C ⋅ ( 1 – D ) – 0,5 1 ω p = -------------------------------------- + --------------------------------------------L ⋅ C OUT ⋅ f SW R LOAD ⋅ C OUT where: Equation 4 Se m C = 1 + -----Sn S = V ⋅ f pp SW e V IN – V OUT S = ----------------------------- ⋅ Ri n L Sn represents the ON time slope of the sensed inductor current, Se the slope of the external ramp (VPP peak-to-peak amplitude 1.25 V) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%. The sampling effect contribution FH(s) is: Equation 5 1 F H ( s ) = -----------------------------------------2 s s 1 + ------------------- + ------2 ωn ⋅ QP ω n where: Doc ID 17928 Rev 4 9/30 Functional description ST1S40 Equation 6 1 Q P = ---------------------------------------------------------π ⋅ [ m C ⋅ ( 1 – D ) – 0,5 ] and Equation 7 ω n = π ⋅ f SW The resistor to adjust the output voltage gives the term from output voltage to the FB pin. GDIV(s) is: R2 G DIV ( s ) = -------------------R1 + R2 The transfer function from FB to Vcc (output of E/A) introduces the singularities (poles and zeroes) to stabilize the loop. Figure 5 shows the small signal model of the error amplifier with the internal compensation network. Figure 5. Small signal model for the error amplifier 9 )% 5R 9G *P9G 95() &R 5F &S &F RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability and can be neglected. So GEA(s) results: Equation 8 G EA0 ⋅ ( 1 + s ⋅ R c ⋅ C c ) G EA ( s ) = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s ⋅ R0 ⋅ ( C0 + Cp ) ⋅ Rc ⋅ Cc + s ⋅ ( R0 ⋅ Cc + R0 ⋅ ( C0 + Cp ) + Rc ⋅ Cc ) + 1 where GEA= Gm · Ro The poles of this transfer function are (if Cc >> C0+CP): 10/30 Doc ID 17928 Rev 4 ST1S40 Functional description Equation 9 1 f P LF = ---------------------------------2 ⋅ π ⋅ R0 ⋅ Cc Equation 10 1 f P HF = ---------------------------------------------------2 ⋅ π ⋅ Rc ⋅ ( C0 + Cp ) whereas the zero is defined as: Equation 11 1 f Z = --------------------------------2 ⋅ π ⋅ Rc ⋅ Cc The embedded compensation network is RC=70 kΩ, CC=195 pF while CP and CO can be considered as negligible. The error amplifier output resistance is 240 MΩ so the relevant singularities are: Equation 12 f Z = 11, 6 kHz f P LF = 3, 4 Hz so by closing the loop, the loop gain GLOOP(s) is: Equation 13 G LOOP ( s ) = G CO ( s ) ⋅ G DIV ( s ) ⋅ G EA ( s ) Example: VIN=12 V, VOUT=1.2 V, Iomax=3 A, L=1.5 µH, Cout=47 µF (MLCC), R1=10 kΩ, R2=20 kΩ (see Section 6.2 and Section 6.3 for inductor and output capacitor selection guidelines). The module and phase Bode plot are reported in Figure 6. The bandwidth is 100 kHz and the phase margin is 45 degrees. Doc ID 17928 Rev 4 11/30 Functional description Figure 6. 5.3 ST1S40 Module and phase Bode plot Overcurrent protection The ST1S40 implements the pulse-by-pulse overcurrent protection. The peak current is sensed through the high side Power MOSFET and when it exceeds the first overcurrent threshold (OCP1) the high side is immediately turned off and the low side conducts the inductor current for the rest of the clock period. During overload condition, since the duty cycle is not set by the control loop but is limited by the overcurrent threshold, the output voltage drops out of regulation. If the feedback falls below 0.3 V the switching frequency is reduced to one fourth and the current limit threshold is folded back to around 2 A. Thanks to the current and frequency fold back the stress on the device and on the external power components is reduced in case of severe overload or dead-short to ground of the output. The current fold back is disabled during the startup, in order to allow the Vout to rise up properly in case of the big output capacitor requiring high extra current to be charged. 12/30 Doc ID 17928 Rev 4 ST1S40 Functional description An additional mechanism is protecting the device in case of short-circuit on the output and high input voltage. A further threshold (OCP2, 1A higher than OCP1) is compared to the inductor current. If the inductor current exceeds OCP2, the device stops switching and restarts with a soft-start cycle. 5.4 Enable function The enable feature allows the device to be put into standby mode. With the EN pin lower than 0.4 V, the device is disabled and the power consumption is reduced to less than 15 µA. With the EN pin higher than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VIN compatible. 5.5 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation. Doc ID 17928 Rev 4 13/30 Application information ST1S40 6 Application information 6.1 Input capacitor selection The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 14 2 2 2⋅D D I RMS = I O ⋅ D – --------------- + ------2η η where Io is the maximum DC output current, D is the duty cycle, η is the efficiency. Considering η=1, this function has a maximum at D=0.5 and is equal to Io/2. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 15 IO D D V PP = ------------------------- ⋅ 1 – ---- ⋅ D + ---- ⋅ ( 1 – D ) + ESR ⋅ I O C IN ⋅ F SW η η where ESR is the equivalent series resistance of the capacitor. Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this case the equation of CIN as a function of the target peak-to-peak voltage ripple (VPP) can be written as follows: Equation 16 IO D D C IN = --------------------------- ⋅ 1 – ---- ⋅ D + ---- ⋅ ( 1 – D ) V PP ⋅ F SW η η neglecting the small ESR of ceramic capacitors. Considering η=1, this function has its maximum in D=0.5, therefore, given the maximum peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is: 14/30 Doc ID 17928 Rev 4 ST1S40 Application information Equation 17 IO C IN_MIN = -----------------------------------------------2 ⋅ V PP_MAX ⋅ F SW Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order of 1% of VINMAX. In Table 6 some multi layer ceramic capacitors suitable for this device are reported. Table 6. Input MLCC capacitors Manufacturer Series Cap value (μF) Rated voltage (V) GRM31 10 25 GRM55 10 25 C3225 10 25 Murata TDK A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1 µF. 6.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20% to 40% of the output current. In continuous current mode (CCM), the inductance value can be calculated by the following equation: Equation 18 V IN – V OUT V OUT ΔI L = ------------------------------ ⋅ T ON = -------------- ⋅ T OFF L L where TON is the conduction time of the high side switch and TOFF is the conduction time of the low side switch (in CCM, FSW=1/(TON + TOFF)). The maximum current ripple, given the Vout, is obtained at maximum TOFF, that is at minimum duty cycle. So by fixing ΔIL=20% to 30% of the maximum output current, the minimum inductance value can be calculated: Equation 19 V OUT 1 – D MIN L MIN = ---------------- ⋅ ----------------------ΔI MAX F SWMIN where FSWMIN is the minimum switching frequency, according to Table 4 The peak current through the inductor is given by: Doc ID 17928 Rev 4 15/30 Application information ST1S40 Equation 20 ΔI L I L, PK = I O + -------2 so if the inductor value decreases, the peak current (that must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. In Table 7 below some inductor part numbers are listed. Table 7. Inductors Manufacturer Coilcraft Wurth TDK 6.3 Series Inductor value (μH) Saturation current (A) XPL7030 2.2 to 4.7 6.8 to 10.5 MSS1048 2.2 to 6.8 4.14 to 6.62 MSS1260 10 5.5 WE-HC/HCA 3.3 to 4.7 7 to 11 WE-TPC typ XLH 3.6 to 6.2 4.5 to 6.4 WE-PD type L 10 5.6 RLF7030T 2.2 to 4.7 4 to 6 Output capacitor selection The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 21 ΔI MAX ΔV OUT = ESR ⋅ ΔI MAX + ------------------------------------8 ⋅ C OUT ⋅ f SW For ceramic (MLCC) capacitors the capacitive component of the ripple dominates the resistive one. Whilst for electrolytic capacitors the opposite is true. Since the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. The equations of Chapter 5.2 help to check loop stability given the application conditions, the value of the inductor, and of the output capacitor. In Table 8 below some capacitor series are listed. 16/30 Doc ID 17928 Rev 4 ST1S40 Application information Table 8. Output capacitors Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ) GRM32 22 to 100 6.3 to 25 <5 GRM31 10 to 47 6.3 to 25 <5 ECJ 10 to 22 6.3 <5 EEFCD 10 to 68 6.3 15 to 55 SANYO TPA/B/C 100 to 470 4 to 16 40 to 80 TDK C3225 22 to 100 6.3 <5 MURATA PANASONIC 6.4 Thermal dissipation The thermal design is important in order to prevent thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the ON resistance of high side switch (RHS) and low side switch (RLS); these are equal to: Equation 22 2 2 P COND = R HS ⋅ I OUT ⋅ D + R LS ⋅ I OUT ⋅ ( 1 – D ) where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but is actually slightly higher to compensate the losses of the regulator. b) switching losses due to high side Power MOSFET turn ON and OFF; these can be calculated as: Equation 23 ( T RISE + T FALL ) P SW = V IN ⋅ I OUT ⋅ ------------------------------------------- ⋅ Fsw = V IN ⋅ I OUT ⋅ T SW ⋅ F SW 2 where TRISE and TFALL are the overlap times of the voltage across the high side power switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 7. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 20 ns. c) Quiescent current losses, calculated as: Equation 24 P Q = V IN ⋅ I Q Doc ID 17928 Rev 4 17/30 Application information ST1S40 where IQ is the quiescent current (IQ=2.5 mA maximum). The junction temperature TJ can be calculated as: Equation 25 T J = T A + Rth JA ⋅ P TOT where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA measured on the demonstration board described in the following paragraph is about 40 °C/W for the VFQFPN and HSOP packages and about 55 °C/W for the SO8-BW package. Figure 7. Switching losses VIN VSW ISW,HS VDS,HS PSW PCOND,HS PCOND,LS TFALL 6.5 TRISE Layout consideration The PC board layout of switching DC-DC regulator is very important in order to minimize the noise injected in high impedance nodes, to reduce interferences generated by the high switching current loops, and to optimize the reliability of the device. In order to avoid EMC problems, the high switching current loops must be as short as possible. In the buck converter there are two high switching current loops: during the ON time, the pulsed current flows through the input capacitor, the high side power switch, the inductor and the output capacitor; during the OFF time, through the low side power switch, the inductor and the output capacitor. The input capacitor connected to VINSW must be placed as close as possible to the device, to avoid spikes on VINSW due to the stray inductance and the pulsed input current. 18/30 Doc ID 17928 Rev 4 ST1S40 Application information In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the VINA pin to the input must be derived from VINSW. The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interferences can be minimized through the routing of the feedback node with a very short trace and as far as possible from the high current paths. A single point connection from signal ground to power ground is suggested. Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane, soldered to the exposed pad, enhances the thermal performance of the converter allowing high power conversion. Figure 8. PCB layout guidelines Via to connect the thermal pad To bottom or inner ground plane Star center for common ground Short high switching current loop Input cap as close as possible to VINSW pin Short FB trace VINA derived from Cin To avoid dynamic voltage drop Between VINA and VINSW Doc ID 17928 Rev 4 19/30 Demonstration board 7 20/30 ST1S40 Demonstration board Figure 9. Demonstration boards schematic Table 9. Component list Reference Part number Description Manufacturer U1 ST1S40 L1 DRA74 3R3 3.3 µH, Isat=5.4 A Coiltronics C1 C3225X7RE106K 10 µF 25 V X7R TDK C2 C3225X7R1C226M 22 µF 16 V X7R TDK STM C3 1 µF 25 V X7R C4 NC R1 62.5 kΩ R2 20 kΩ R3 10 kΩ Doc ID 17928 Rev 4 ST1S40 Demonstration board Figure 10. Demonstration board PCB top and bottom: HSOP8 package Figure 11. Demonstration board PCB top and bottom: VFQFPN package Figure 12. Demonstration board PCB top and bottom: SO8-BW package Doc ID 17928 Rev 4 21/30 Typical characteristics 8 ST1S40 Typical characteristics Figure 13. Efficiency vs. IOUT Figure 14. Efficiency vs. IOUT 90 100 85 90 80 75 Efficiency [%] Efficiency [%] 80 70 Vin=5V 60 65 60 Vin=12V 55 Vo=1.8V Vo=3.3V 50 70 50 Vo=1.2V Vo=1.8V 45 Vo=1.2V 40 40 0.00 0.50 1.00 1.50 2.00 2.50 3.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 Iout [A] Iout [A] Figure 15. Efficiency vs. IOUT Figure 16. Overcurrent protection 100 90 Efficiency [%] 80 70 Vin=12V Vo=5V 60 Vo=3.3V 50 40 0.00 0.50 1.00 1.50 2.00 2.50 3.00 Iout [A] Figure 17. Short-circuit protection Figure 18. SO8-BW maximum IOUT Maximum IOUT according to 1.6W power dissipation Limit with SO8-BW package Tamb=60degC Tjmax=150degC 22/30 Doc ID 17928 Rev 4 ST1S40 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 17928 Rev 4 23/30 Package mechanical data Table 10. ST1S40 VFQFPN8 (4x4x1.0 mm) mechanical data mm inch Dim. Min. Typ. Max. Min. Typ. Max. 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.02 0.05 0.0008 0.0020 A3 0.20 A 0.0079 b 0.23 0.30 0.38 0.009 0.0117 0.0149 D 3.90 4.00 4.10 0.153 0.157 0.161 D2 2.82 3.00 3.23 0.111 0.118 0.127 E 3.90 4.00 4.10 0.153 0.157 0.161 E2 2.05 2.20 2.30 0.081 0.087 0.091 e L 0.80 0.40 0.50 0.031 0.60 0.016 0.020 0.024 Figure 19. VFQFPN8 (4x4x1.0 mm) package dimensions % 24/30 Doc ID 17928 Rev 4 ST1S40 Package mechanical data Table 11. SO8-BW mechanical data mm inch Dim Min. Typ. Max. Min. Typ. Max. A 135 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.001 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.01 (1) 4.80 5.00 0.1890 E 3.80 4.00 0.15 D e 1.27 0.1929 0.1969 0.157 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.0098 0.0197 L 0.40 1.27 0.0157 0.0500 k 0°(min.), 8° (max.) ddd 0.10 0.0039 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs must not exceed 0.15 mm (.006 inch) in total (both sides). Figure 20. SO8-BW package dimensions & 6HDWLQJ 3ODQH GGG& $ PP *DJH3ODQH $ $ H % K[ N / ' ( + & Doc ID 17928 Rev 4 25/30 Package mechanical data Table 12. ST1S40 HSOP8 mechanical data mm inch Dim Min. Typ. A Min. Typ. 1.70 Max. 0.0669 A1 0.00 A2 1.25 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 D 4.80 4.90 5.00 0.1890 0.1929 0.1969 E 5.80 6.00 6.20 0.2283 0.2362 0.2441 E1 3.80 3.90 4.00 0.1496 0.1535 0.1575 e 0.150 0.00 0.0059 0.0492 1.27 0.0500 h 0.25 0.50 0.0098 0.0197 L 0.40 1.27 0.0157 0.0500 k 0.00 8.00 0.3150 0.10 0.0039 ccc 26/30 Max. Doc ID 17928 Rev 4 ST1S40 Package mechanical data Figure 21. HSOP8 package dimensions ' PP7\S ( PP7\S $0Y Doc ID 17928 Rev 4 27/30 Order codes 10 ST1S40 Order codes Table 13. 28/30 Ordering information Order codes Package ST1S40IPUR VFQFPN 4x4 8L ST1S40IPHR HSOP8 ST1S40IDR SO8-BW Doc ID 17928 Rev 4 Function Enable ST1S40 11 Revision history Revision history Table 14. Document revision history Date Revision Changes 15-Dec-2010 1 First release 04-Mar-2011 2 Updated: Table 1, Table 2, Table 3 and Table 13. 20-Dec-2011 3 Updated cover page: Table 1, Table 2, Section 5 Added Section 6, Section 7 and Section 8 01-Mar-2012 4 HSOP8 mechanical data and package dimensions have been updated. Doc ID 17928 Rev 4 29/30 ST1S40 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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