Data Sheet - Bel Fuse Inc.

Power System Sequencer
TRKF- 10DC4ER
On Board Power System Controller
RoHS Compliant
•
Digital Signal Processor (DSP) Based with Bel Firmware
•
Provides Power Up and Power Down Sequencing Logic
•
Stand Alone or Command Based Feature Set
•
Fault Detection and Reporting
•
100 Pin 12mm x 12mm TQFP package
•
I2C, SMBus, or PMBus compatible serial interface options
•
Configurable through serial interface, Customizable through software
•
3V3 logic levels
•
•
•
Voltage Margining via Closed Loop Trim
Programmed parameters saved in non volatile memory
Intelligent configuration capability
Description
This on board power system controller provides a cost effective high performance solution for controlling,
monitoring, and sequencing multiple Point of Load (POL) converters and VRM’s on a system board. The
sequencer uses a digital signal processor (DSP) engine and Bel’s firmware to implement a portfolio of board
level control features typically required in a multiple voltage configuration. The solution can control and monitor
PoL converters and VRM’s. The 100 pin TRKF-10DC4ER is derived from bel’s 64 pin TRKF-64D82ER platform
with expanded I/O and functionality.
Optional Feature Sets
SDA
I2C
SCL
Digital
Commands
EE^2 Data Logging
Input Inrush Control
Communication
and
Command Interface
Vin Monitor
A
B
C/Optional SS for SPI
Vout ADC Input
Vin
Vin
Digital Output
Enable
PoL 1 of n
Trim PWM
Vout
Vout 1of n
Trim
Rfilter
Rlimit
GND
Cfilter
Control Grouping 1 of n
Figure 1
Functional Block Diagram
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
I/O Definitions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16
AN17
AN18
AN19
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/RE8
AN21/RE9
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN4/RB2
AN2/SS1/CN4/RB2
AN1/RB1
AN0/RBO
PGC1/AN6/RB6
PGD1/AN7/RB7
VREFVREF+
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
RA1
RF13
RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/RB15
VSS
VDD
CN20/RD14
CN21/RD15
CN17/RF4
CN18/RF5
Note
Note
Note
Note
1
2
3
4
Analog z Comp Out/Enable (see Note 2)
3V3 VDD
I2C_ALERT
PoL 12 PWM Trim
Manufacturing Mode
VRM 1 Vout Monitor
VRM 2 Vout Monitor
VRM 3 Vout Monitor
VRM 4 Vout Monitor
Board ID 0
Board ID 1
Board ID 2
CMD Reset/Vpp
Un-linked Enable Output (Note 3)
Logic Ground
3V3 VDD
Enable/Board Seated
Low Power Shutdown
Board ID Analog (Note 4)
PoL 5 Vout Monitor
PoL 4 Vout Monitor
PoL 3 Vout Monitor
PoL 2 Vout Monitor
PoL 1 Vout Monitor
Vin Monitor
PoL 6 Vout Monitor
PoL 7 Vout Monitor
Analog Ground
3V00 External Reference
FILTERED VDD (Analog VDD)
Analog Ground
PoL 8 Vout Monitor
PoL 9 Vout Monitor
PoL 10 Vout Monitor
PoL 11 Vout Monitor
Logic Ground
3V3 VDD
Pol 1 Enable
VID 6
VID 5
Pol 12 Monitor
Analog x Monitor
Analog y Monitor
Analog z Monitor
Logic Ground
3V3 VDD
Thermal Trip (see Note 1)
Power Good
VID 0
VID 1
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
RF3
RF2
SDO1/RF8
SDI1/RF7
SCK1/RF6
SDA1/RG3
SCL1/RG2
RA2
RA3
RA4
RA5
VDD
RC12
RC15
VSS
RA14
RA15
RD8
RD9
RD10
RD11
OC1/RD0
PGD2
PGC2
VSS
OC2/RD1
OC3/RD2
OC4/RD3
RD12
CN19/RD13
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
0C8/CN16/RD7
VDD_CORE
VDD
RF0
RF1
RG1
RG0
AN22/CN22/RA6
AN23/CN23/RA7
PWM1L/RE0
PWM1H/RE3
RG14
RG12
RG13
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
VRM D Enable
VRM C Enable
VID 4
VID 3
VID 2
I2C Data
I2C Clock
PoL 2 Enable
PoL 3 Enable
PoL 4 Enable
PoL 5 Enable
3V3 VDD
Reset B Out
Reset C Out
Logic Ground
Reset In
Reset A Out
PoL 8 Enable
PoL 9 Enable
PoL 10 Enable
PoL 11 Enable
PoL 1 PWM Trim
Program Data
Program Clock
Logic Ground
PoL 2 PWM Trim
PoL 3 PWM Trim
PoL 4 PWM Trim
PoL 12 Enable
IO PIF Enable/OV Trip
PoL 5 PWM Trim
PoL 6 PWM Trim
PoL 7 PWM Trim
PoL 8 PWM Trim
Core Decoupling Capacitor
3V3 VDD
VRM A Enable
VRM B Enable
VID MUX 1
VID MUX 0
PoL 6 Enable
PoL 7 Enable
PoL 9 PWM Trim
Margin High
Analog y Comp Out/Enable (see Note 2)
VR Hot (See Note 1)
Analog x Comp Out/Enable (see Note 2)
PoL 10 PWM Trim
Margin Low
PoL 11 PWM Trim
Thermal Trip and VR_Hot Signals for A,B,C,D mapped to same MUX as VID's
These signals triggered by defined voltage levels on corresponding Analog Monitor or used like POL enable
Controlled in a selected power up sequence but not tied to a specific output
Use ADC to allow ID of additional boards with resistor divider
Figure 2
I/O Definitions
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
I/O Grouping
A
13 MCLR
73 PGD2
74 PGC2
CMD Reset/Vpp
Program Data
Program Clock
B
85
29
30
86
2
16
37
46
62
65
45
36
15
75
28
31
VDD_CORE
VREF+
AVDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VREFAVSS
Core Decoupling Capacitor
3V00 External Reference
FILTERED VDD (Analog VDD)
3V3 VDD
3V3 VDD
3V3 VDD
3V3 VDD
3V3 VDD
3V3 VDD
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Logic Ground
Analog Ground
Analog Ground
C
10
11
12
19
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
AN21/RE9
Board ID 0
Board ID 1
Board ID 2
Board ID Analog (Note 5)
D
56 SDA1/RG3
57 SCL1/RG2
3 PWM3H/RE5
I2C Data
I2C Clock
I2C_ALERT
F
99
94
5
48
66
67
63
64
17
18
Margin Low (Note 4)
Margin High (Note 4)
Manufacturing Mode (Note 4)
Power Good
Reset In
Reset A Out
Reset B Out
Reset C Out
Enable/Board Seated
Low Power Shutdown
G1
G2
6
7
8
9
AN16
AN17
AN18
AN19
VRM 1 Vout Monitor
VRM 2 Vout Monitor
VRM 3 Vout Monitor
VRM 4 Vout Monitor
87
88
52
51
RF0
RF1
RF2
RF3
VRM A Enable
VRM B Enable
VRM C Enable
VRM D Enable
89
90
49
50
55
54
53
40
39
96
47
RG1
RG0
CN17/RF4
CN18/RF5
SCK1/RF6
SDI1/RF7
SDO1/RF8
RF12
RF13
RG12
CN20/RD14
VID MUX 1
VID MUX 0
VID 0
VID 1
VID 2
VID 3
VID 4
VID 5
VID 6
VR Hot (See Note 1)
Thermal Trip (see Note 1)
42 AN13/RB13 Analog x Monitor
43 AN14/RB14 Analog y Monitor
44 AN15/RB15 Analog z Monitor
J
24
23
22
21
20
26
27
32
33
34
35
41
AN1/RB1
AN2/SS1/CN4/RB2
AN3/CN4/RB2
AN4/CN6/RB4
AN5/CN7/RB5
PGC1/AN6/RB6
PGD1/AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
PoL 1 Vout Monitor
PoL 2 Vout Monitor
PoL 3 Vout Monitor
PoL 4 Vout Monitor
PoL 5 Vout Monitor
PoL 6 Vout Monitor
PoL 7 Vout Monitor
PoL 8 Vout Monitor
PoL 9 Vout Monitor
PoL 10 Vout Monitor
PoL 11 Vout Monitor
PoL 12 Vout Monitor
72
76
77
78
81
82
83
84
93
98
100
4
OC1/RD0
OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
0C8/CN16/RD7
PWM1L/RE0
PWM2L/RE2
PWM3L/RE4
PWM4L/RE6
PoL 1 PWM Trim
PoL 2 PWM Trim
PoL 3 PWM Trim
PoL 4 PWM Trim
PoL 5 PWM Trim
PoL 6 PWM Trim
PoL 7 PWM Trim
PoL 8 PWM Trim
PoL 9 PWM Trim
PoL 10 PWM Trim
PoL 11 PWM Trim
PoL 12 PWM Trim
38
58
59
60
61
91
92
68
69
70
71
79
RA1
RA2
RA3
RA4
RA5
AN22/CN22/RA6
AN23/CN23/RA7
RD8
RD9
RD10
RD11
RD12
PoL 1 Enable
PoL 2 Enable
PoL 3 Enable
PoL 4 Enable
PoL 5 Enable
PoL 6 Enable
PoL 7 Enable
PoL 8 Enable
PoL 9 Enable
PoL 10 Enable
PoL 11 Enable
PoL 12 Enable
H
A
B
C
D
E
F
G1
G2
H
I
J
PWM2H/RE3
PWM1H/RE3
PWM4H/RE7
CN21/RD15
RA14
RA15
RC12
RC15
TMS/RA0
AN20/RE8
I
97 RG13
95 RG14
1 RG15
Analog x Comp Out/Enable (see Note 2)
Analog y Comp Out/Enable (see Note 2)
Analog z Comp Out/Enable (see Note 2)
25 AN0/RBO
Vin Monitor
80 CN19/RD13 IO PIF Enable/OV Trip
14 SS2/CN11/R Un-linked Enable Output (Note 3)
Comments
These signals are required for the part to be ICSP and ICD.
All power related pins
Board ID pins to define various configurations.
I2C interface.
Spare pins for assignment
Misc CMD I/O for on/off, and fault reporting
VRM outputs and enables. Should be about to sequence these and define them to be tied to the MUX'd info. If not used with VRM, they are sequencable/monitored voltages
MUX'd signals for use with VRMs. VID bits double as ID bits if necessary to support more board configs without 4 VRMs.
Sequencable analog monitors. The Comp Out/Enable signal is dual purpose to either act as a comparator output or work like a sequencable/monitored voltage.
Vin Monitor should be sequencable and tied to IO PIF Enable/OV Trip.
PoL control works like TRKF-64D82ER device
Figure 3
I/O Grouping
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
Powering the Sequencer
VDD Core
C8
2.2 uF
10v
X5R
D1
BAT54
+12Vin
In
R1
20 Ohm
1206
+12Vin Return
C1
1000uF
25V
C2
1uF
16v
X5R
Microchip P/N
MCP1702T-3302I/MB
or Equivalent
VDD
Out
3V3 Output LDO
C4
1uF
16v
X5R
GND
R2
4.64 Ohm
C5
1uF
16v
X5R
C6
1uF
16v
X5R
C7
1uF
16v
X5R
VSS
AVDD
C3
2.2 uF
10v
X5R
AVSS
R3
1 Ohm
FIGURE 4
VDD Interface
Figure 4 is a schematic of the typical VDD interface to the sequencer IC. A Microchip LDO, P/N MCP1702T3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most
applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V
source. Capacitors C4, C5, C6, and C7 are the decoupling capacitors for the DSP and they should be located
directly across each pair of VDD and VSS pins on the DSP IC. The 64 pin device has a VDD core pin which is
used to decouple the internally generated core voltage. Capacitor C8 is the decoupling capacitor for the VDD
core which is not required with the 44 pin device. This decoupling capacitor should be a low ESR ceramic
capacitor and can be as large as 10uF. Capacitor C3 is the decoupling capacitor for the analog VDD (AVDD) and
it should be located directly across the AVDD and AVSS pins on the DSP IC. Resistor R2 in combination with C3
provides a filter for the analog VDD. Resistor R3 is intended to separate AVSS from VSS. Capacitor C2 is the
input decoupling capacitor for the LDO and it should be connected directly across the LDO’s input and ground
pins. Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage to the LDO and
maintain a stable VDD for the DSP for a short period after the +12Vin source is removed. This would be desired if
a short communication stream is required during power down or if storing system data to EE memory is required
during power down. The Schottky diode D1 prevents C1 from being discharged after +12Vin is removed.
Resistor R1 is used to protect D1 during the inrush event associated with the application of the +12Vin. The
single pulse peak current rating for a typical BAT54 diode is approximately 600mA. If the rise time of the +12V
source is slow enough to limit the peak charging current into C1 it is possible to eliminate R1. Assuming a
40mA current draw by the DSP C1 will provide approximately 188 uS of hold up time per uF of capacitance.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
Using the PWM Trim Outputs
+Sense
+Vin
Zf
Ry
TRIM
-
Zi
Rx
+Vout
Rz
PWM
E/A
+
Reference
Figure 5A.
+Sense
+Vin
Zf
-
Zi
+Vout
PWM
E/A
+
TRIM
Rx
Ry
Reference
Figure 5B.
+Sense
+Vin
Zf
-
Zi
+Vout
E/A
Reference
TRIM
PWM
+
uController
or Equivalent
Figure 5C.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
The drawings in figure 5 show the three most common trim methods used in PoL converters. In all of these
schemes a power conversion stage contains a PWM device that receives a control voltage from an error
amplifier. The error amplifier (E/A) compares a scaled version of the output voltage to a reference. The output
voltage of the converter module is simply the reciprocal of the scaling factor multiplied by the reference value.
The output voltage can be adjusted by changing this scaling factor (Figure 5A) or by modifying the reference
(Figures 5B, C).
The most common trim method is shown in figure 5A. The popularity of this method stems from the fact that
most highly integrated PWM control IC’s have an internal reference that is not accessible and cannot be
controlled externally. In this scheme the output is scaled by adding a resistor from the trim pin to ground. This
modifies the feedback divider and moves the output voltage to a higher value. The output can also be modified
by superimposing an offset voltage on the feedback divider by connecting a voltage source to the trim pin
through a resistor. Either of these two approaches will move the output voltage to a new value. The common
characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher
output voltage or a larger voltage superimposed on the trim pin will cause Vout to decrease.
Some PoL converters incorporate the trim scheme shown in figure 5B. With this method the feedback ratio is
kept constant and the reference value is modified to move the output voltage. The common characteristic of
modules with this trim scheme is that a lower value trim resistor to ground will cause a lower output voltage and
a larger voltage superimposed on the trim pin will cause Vout to increase.
The method shown in figure 5C is occasionally used. This is similar to the method in figure 5B except the
modification of the reference is mapped through a device such as a microcontroller. This is the least common
of the 3 methods and requires the vendor’s data sheet to determine the trim characteristic because the micro
controller can map the reference in many different ways.
PoL Vout
or
VDD
VTrim Ripple
VTrim Average
Margin PWM
PoL Trim Pin
Ra
3V3
Ca
Rb
Ca
0
Margin PWM
PoL Trim Pin
Ra
Rb
3V3
VTrim Average
0
Figure 6A
VTrim Ripple
Figure 6B
The power sequencer has the ability to do independent closed loop trim and closed loop margining of the output
voltage for each PoL controlled by the device. Each PoL’s output voltage is monitored and by an analog to
digital converter (ADC) in a continuous loop. In firmware the most recent measured output voltage is compared
against the desired value and the PoL’s output is adjusted by delivering a trim value to the corresponding PoL’s
trim pin. This trim voltage is created from a digital PWM output and an external low pass filter. Each digital
PWM is labeled <PoL “n” Margin PWM> where n indicates a specific converter which corresponds to the
monitoring channel labeled with the same “n” value. The external low pass filter creates a DC value from the
PWM signal which is then delivered to each PoL converter through a range limiting resistor.
Figure 6 shows the typical circuits used to interface the sequencers Margin PWM signals to PoL converters. In
each of the circuits shown Ra and Ca construct a low pass filter while Rb is used to limit the trim range. The
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
effective trim voltage is equal to the Margin PWM duty cycle multiplied by VDD and is controllable in 1024 steps
from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are chosen to reduce the trim
voltage ripple. Typical values for Ra and Ca are 1K for Ra and 0.22uF to 1uF for Ca. Rb is used to limit the
control range and should be selected based on the desired control range and the trim equation for the PoL.
This trim equation is usually available from the PoL manufactures data sheet. The sequencer learns the trim
direction by making a minor adjustment to the Margin PWM and then determining the direction that Vout moves
based on this stimulus. Once the trim direction is known it knows whether increment or decrement the TRIM
PWM value until the desired Vout is achieved. The accuracy of the active trim is a function of the ADC accuracy
which is mostly controlled by accuracy of the applied reference to the sequencers Vref pins.
Either circuit in Figure 6 will work with any of the trim methods shown in Figure 5. When interfacing to PoL
modules that use the trim method in Figure 5A the circuit in Figure 6B is the optimum interface configuration. By
connecting the filter capacitor Ca to the PoL’s Vout or to a positive voltage reference the effective of filtering the
Margin PWM signal remains intact. With this method there will not be a discharged capacitor connected to
ground that could cause the PoL’s output to overshoot during power up as this capacitor becomes charged. In
the case that the circuit in figure 6A is used with the trim configuration in Figure 5B the sequencer will precharge the capacitor before enabling the PoL converter and then decrement the Margin PWM to achieve the
desired Vout. This requires additional start up time during system initialization. When interfacing to PoL
converters of the type shown in Figure 5B the interface circuit in figure 6A is optimum.
Monitoring Via ADC Channels
The imbedded ADC channels are converted as 10 bit results with full scale equal to a chosen reference. The
device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC
reference or to use an externally provided reference. Closed loop margining and set point adjustments always
use the entire 10 bit result to trim the output voltages to loaded values. Monitored voltages are reported via I2C
communication using PMBus data formats as defined in the separate communication manual. The voltage
range reported is determined by the entered set points. Any monitored output that is greater than the ADC
reference or that can be margined above this reference should have a voltage divider to limit the maximum input
to the corresponding ADC channel to a value equal or less than the ADC reference. Monitored voltages below
the chosen ADC reference do not require this voltage divider. A four sample moving average is used to filter the
ADC results. In most cases this will eliminate the need for external filtering.
The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value
less than the maximum value of the ADC reference.
Connecting the Control and Monitoring
The three primary control interface signals to the attached PoL converters are an enable signal, a voltage
monitoring signal, and trim control signal. The enable signals are labeled <PoL “n” Enable>. The Monitoring
signals are labeled <PoL Monitor “n”>. The trim signals are labeled <PoL “n” Margin PWM>. Each n’th PoL
converter is required to share the corresponding enable, monitor, and trim signals. For example the first PoL
converter attached to the controller is PoL 1. PoL 1 should use <PoL 1 Enable>, <PoL Monitor 1>, and PoL 1
Margin PWM, etc... The installed firmware assumes that the connections are made this way when controlling
system.
Communicating to the Device
Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus
command set and is defined in a separate communications manual. The communications manual also defines
the protocol for device programming via embedded boot loader software.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
Page 0
Not USed
Hard Coded
I2C Address
Page 1
PoL1
Set Point Control
Scaling
Margin Limits
PGD/Warning Limits
Voltage Readss
Page 10
PoL10
Set Point Control
Scaling
Margin Limits
PGD/Warning Limits
Voltage Readss
Page 2
PoL 2
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 11
PoL11
Set Point Control
Scaling
Margin Limits
PGD/Warning Limits
Voltage Readss
Page3
PoL 3
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 12
PoL12
Set Point Control
Scaling
Margin Limits
PGD/Warning Limits
Voltage Readss
Page 4
PoL 4
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
I2C Engine
I2C Bus
&
Page
Switch
Page 5
PoL 5
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 6
PoL 6
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 7
PoL 7
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 8
PoL 8
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 9
PoL 9
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page_A
VRM A
No Set Point Control
Scaling
PGD/Warning Limits
Voltage Reads
Page_C
VRM C
No Set Point Control
Scaling
PGD/Warning Limits
Voltage Reads
Page_B
VRM B
No Set Point Control
Margin Limits
PGD/Warning Limits
Voltage Reads
Page_D
VRM D
No Set Point Control
Margin Limits
PGD/Warning Limits
Voltage Reads
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V
Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ................................................................................................... ..........................250 mA
Maximum output current sunk by any I/O pin............................................................................................................4 mA
Maximum output current sourced by any I/O pin ......................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ...................................... ...........................................................................200 mA
Electrical Specifications
Parameter
Input Voltage Range
Symbol
VDD
Min
Typ
Max
3.0
3.30
3.6
Units
VDC
Notes
mA
+85C
Input Current
IDD
Logic Low Input Level
VIL
VSS
0.2*VDD
VDC
Logic High Input Level
VIH
0.8*VDD
VDD
VDC
Logic Low Output Level
VOL
0.4
VDC
VDD = 3.3V
Logic High Output Level
VDD Rise Rate
58
VOH
2.4
VDC
VDD = 3.3V, IOH = -3.0mA
SVDD
0.05
V/uS
0 to 3.3V in 100mS
Capacitance I/O Pin to GND
CIO
50
pF
I2C Bus Capacitance
CB
400
pF
SCl and SDA
PWM Series Resistor
RPWM
KΩ
External Series Resistor
Margin PWM Frequency
FPWM
Reference Input
Vref
1
KHz
10
AVSS + 1.7
AVDD
VDC
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
Mechanical Outline
Figure 8A
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
Power System Sequencer
TRKF- 10DC4ER
100-Lead Plastic Thin-Quad Flatpack, 12 x 12 x 1 mm Body
Units
Dimension Limits
Number of Pins
N
Pitch
p
Leasds per Side
n1
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Foot Length
L
Footprint
F
Foot Angle
G
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
Lead Thickness
c
Lead Width
B
Molded Draft Angle Top
H
Molded Draft Angle Bottom
J
* Controlling Parameter
Min.
0.037
0.002
0.018
0
0.004
0.005
11
11
Inches
Nom.
100
0.0157
25
0.039
0.024
0.039 REF
3.5
0.551
0.551
0.472
0.472.
0.007
12
12
Max.
Min.
0.047
0.041
0.006
0.030
0.95
0.05
0.45
7
0
0.008
0.009
13
13
0.09
0.13
11
11
Millimeters*
Nom.
Max.
100
0.40
BSC
25
1.20
1.00
1.05
0.15
0.60
0.75
1.00 REF
3.5
7
14.00 BSC
14.00 BSC
12.00 BSC
12.00 BSC
0.20
0.18
0.23
12
13
12
13
Notes:
1. Dimensions D1 and E1 do not include mold flash or protrusions (not to exceed .010" (0.254mm) per side).
2. Chamfers at corners are optional; size may vary.
3. REF: Reference Dimension, usually without tolerance , for information purposes only.
4. Dimensioning and tolerancing per ASME Y14.5m. BSC = Basic Dimension
Figure 8B
RoHS Compliance
Complies with the European Directive 2002/95/EC, calling for the elimination of lead and
other hazardous substances from electronic products.
©2007 Bel Fuse Inc. Specifications subject to change without notice. 100507
CORPORATE
FAR EAST
EUROPE
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel 201-432-0463
Fax 201-432-9542
www.belfuse.com
Bel Fuse Ltd.
8F/ 8 Luk Hop Street
San Po Kong
Kowloon, Hong Kong
Tel 852-2328-5515
Fax 852-2352-3706
www.belfuse.com
Bel Fuse Europe Ltd.
Preston Technology Management Centre
Marsh Lane, Suite G7, Preston
Lancashire, PR1 8UD, U.K.
Tel 44-1772-556601
Fax 44-1772-888366
www.belfuse.com