Enpirion® Power Datasheet

Enpirion® Power Datasheet
EN2392QI 9A PowerSoC
Voltage Mode Synchronous Buck
With Integrated Inductor
Not Recommended for New Designs
Description
Features
The EN2392QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal control circuits, compensation
and an integrated inductor in an advanced
11x10x3mm QFN module. It offers high efficiency,
excellent line and load regulation over temperature.
The EN2392QI operates over a wide input voltage
range and is specifically designed to meet the precise
voltage and fast transient requirements of highperformance products. The EN2392QI features
frequency synchronization to an external clock, power
OK output voltage monitor, programmable soft-start
along with thermal and over current protection. The
device’s advanced circuit design, ultra high switching
frequency and proprietary integrated inductor
technology delivers high-quality, ultra compact, nonisolated DC-DC conversion.
•
•
•
•
Integrated Inductor, MOSFETS, Controller
Total Solution Size Estimate: 235mm2
Wide Input Voltage Range: 4.5V – 13.2V
1% Initial Output Voltage Accuracy
•
•
•
•
•
•
•
•
•
•
Master/Slave Parallel Operation (up to 4 devices)
Frequency Synchronization (External Clock)
Output Enable Pin and Power OK Signal
Programmable Soft-Start Time
Pin Compatible with EN2390QI
Under Voltage Lockout Protection (UVLO)
Over Current and Short Circuit Protection
Pre-Bias Startup Protection
Thermal Soft-Shutdown Protection
RoHS Compliant, MSL Level 3, 260oC Reflow
Applications
The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Altera Enpirion
solution.
•
•
•
•
•
All Altera Enpirion products are RoHS compliant,
halogen free and are compatible with lead-free
manufacturing environments.
Space Constrained Applications
Distributed Power Architectures
Output Voltage Ripple Sensitive Applications
Beat Frequency Sensitive Applications
Servers, Embedded Computing Systems,
LAN/SAN Adapter Cards, RAID Storage Systems,
Industrial Automation, Test and Measurement,
and Telecommunications
Efficiency vs. Output Current
0.22µF
47nF
100
BTMP VDDB
PVIN
EN2392QI
4.75k
ON
OFF
2x
22µF
1206
VOUT
BGND
VOUT
80
SW
CA
4.7Ω
EAIN
ENABLE
REA
680pF
COUT
CBULK
RA
R CA
AVINO
1µF
AVIN
1µF
47nF
VFB
SS
M/S
EN_PB
PGND
FQADJ
RFS
PGND
AGND
RCLX
RB
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
VOUT = 1.0V
10
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
0
RCLX
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
9
Figure 2. Highest Efficiency in Smallest Solution
Size
Figure 1. Simplified Application Circuit
10107
90
Optional
EFFICIENCY (%)
PG
VIN
June 2, 2015
Rev C
EN2392QI
Ordering Information
Part Number
EN2392QI
EVB-EN2392QI
Package Markings
EN2392QI
EN2392QI
TAMBIENT Rating (°C)
-40 to +85
Package Description
76-pin (11mm x 10mm x 3mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
FQADJ
RCLX
SS
EAIN
VFB
66
65
64
63
62
POK
NC
67
57
EN_PB
68
ENABLE
NC(SW)
69
58
NC(SW)
70
AVIN
NC(SW)
71
59
NC
72
AGND
NC
73
60
NC
74
M/S
NC
75
61
NC
76
Pin Assignments (Top View)
56
S_OUT
2
55
S_IN
NC
3
54
BGND
NC
4
53
VDDB
NC
5
52
BTMP
NC
6
51
PG
NC
7
50
AVINO
NC
8
49
PVIN
NC
9
48
PVIN
NC
10
47
PVIN
NC
11
46
PVIN
NC
12
45
PVIN
NC
13
44
PVIN
NC
14
43
PVIN
NC
15
42
PVIN
NC
16
41
PVIN
NC
17
40
PVIN
NC
18
39
PVIN
KEEP OUT
38
35
PGND
PGND
34
PGND
37
33
PGND
PGND
32
NC(SW)
36
31
NC(SW)
PGND
30
NC
26
VOUT
29
25
VOUT
NC
24
VOUT
28
23
VOUT
77
PGND
VOUT
22
VOUT
27
21
VOUT
VOUT
20
KEEP OUT
VOUT
NC
KEEP OUT
19
1
NC
NC
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. All pins
including NC pins must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 16 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
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EN2392QI
Pin Description
I/O Legend:
P=Power
PIN
1-19, 29,
30, 67, 7276
NAME
I/O
NC
NC
20-28
VOUT
O
31, 32, 6971
NC(SW)
NC
33-38
PGND
G
39-49
PVIN
P
50
AVINO
O
51
52
PG
BTMP
I/O
I/O
53
VDDB
O
54
BGND
G
55
S_IN
I
56
S_OUT
O
57
POK
O
58
ENABLE
I
59
AVIN
P
60
AGND
G
61
M/S
62
VFB
I/O
63
EAIN
I
64
SS
I/O
65
RCLX
I/O
66
FQADJ
I/O
68
EN_PB
I
77
PGND
G
G=Ground
NC=No Connect
I=Input O=Output
I/O=Input/Output
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them to each other or to
any other electrical signal. Failure to follow this guideline may result in device damage.
Regulated converter output. Connect these pins to the load and place output capacitor betw een
these pins and PGND pins 33-35.
Sw itching node – These pins are internally connected to the common sw itching node of the internal
MOSFETs. In applications w here the total output capacitance exceeds 50% of the maximum allow ed,
a “snubber” circuit consisting of a series 4.7Ω resistor and a 680pF capacitor should be connected
from the NC(SW) pin to the PGND. See Output Capacitor Selection for details.
Input/output pow er ground. Connect these pins to the ground electrode of the input and output filter
capacitors. See VOUT and PVIN pin descriptions for more details.
Input pow er supply. Connect to input pow er supply. Decouple w ith input capacitor to PGND pins 3638.
Internal 3.4V linear regulator output. Connect this pin to AVIN for applications w here operation from
a single input voltage (PVIN) is required. If AVINO is being used, place a 1µF, X5R, capacitor
betw een AVINO and AGND as close as possible to AVINO.
PMOS gate. Place a 47nF, X5R, capacitor betw een this pin and BTMP.
Bottom plate ground. See pin 51 description.
Internal regulated voltage used for the internal control circuitry. Place a 0.22µF, X5R, capacitor
betw een this pin and BGND.
Ground for VDDB. Do not connect BGND to any other ground. See pin 53 description.
Digital synchronization input. This pin accepts either an input clock to phase lock the internal
sw itching frequency or a S_OUT signal from another EN2392QI. Leave this pin floating if not used.
Digital synchronization output. PWM signal is output on this pin. Leave this pin floating if not used.
Pow er OK is an open drain transistor (pulled up to AVIN or similar voltage) used for pow er system
state indication. POK is logic high w hen VOUT is w ithin -10% to +20% of VOUT nominal. Leave this
pin floating if not used.
Output enable. Applying a logic high to this pin enables the output and initiates a soft-start. Applying
a logic low disables the output. ENABLE logic cannot be higher than AVIN (refer to Absolute
Maximum Ratings). Do not leave floating. See Pow er Up/Dow n Sequencing section for details.
3.3V Input pow er supply for the controller. Place a 1µF, X5R, capacitor betw een AVIN and AGND
Analog ground. This is the ground return for the controller. All AGND pins need to be connected to a
quiet ground.
A logic level low configures the device as Master and a logic level high configures the device as a
Slave. Connect to ground in standalone mode.
External feedback input. The feedback loop is closed through this pin. A voltage divider at VOUT is
used to set the output voltage. The mid-point of the divider is connected to VFB. A phase lead
netw ork from this pin to VOUT is also required to stabilize the loop.
Optional error amplifier input. Allow s for customization of the control loop for performance
optimization. Leave this pin floating if not used.
Soft-start node. The soft-start capacitor is connected betw een this pin and AGND. The value of this
capacitor determines the startup time. See Soft-Start Operation in the Functional Description section
for details.
Over-current protection setting. Placement of a resistor on this pin w ill adjust the over-current
protection threshold. See Table 2 for the recommended RCLX Value to set OCP at the nominal
value specified in the Electrical Characteristics table. Do not leave this pin floating.
Adding a resistor (RFS) to this pin w ill adjust the sw itching frequency of the EN2392QI. See Table 1
for suggested resistor values on RFS for various PVIN/VOUT combinations to maximize efficiency. Do
not leave this pin floating.
Enable pre-bias protection. Connect EN_PB directly to AVIN to enable the Pre-Bias Protection
feature. Pull EN_PB directly to ground to disable the feature. Do not leave this pin floating. See PreBias Operation for details.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-sinking
purposes.
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June 2, 2015
Rev C
EN2392QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
MIN
MAX
UNITS
Pin Voltages – PVIN, VOUT, PG
PARAMETER
SYMBOL
-0.5
15
V
Pin Voltages – ENABLE, S_IN, M/S, POK, EN_PB
-0.5
AVIN + 0.3
V
Pin Voltages – AVINO, AVIN, ENABLE, S_IN, S_OUT, M/S
-0.5
6.0
V
Pin Voltages – VFB, SS, EAIN, RCLX, FQADJ, VDDB, BTMP
-0.5
2.75
V
Dual Supply PVIN Rising and Falling Slew Rate (Note 1)
25
V/ms
Single Supply PVIN Rising and Falling Slew Rate (Note 1, 2)
10
V/ms
150
°C
150
°C
260
°C
2000
V
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
-65
TJ-ABS Max
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
Recommended Operating Conditions
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
PARAMETER
PVIN
4.5
13.2
V
AVIN: Controller Supply Voltage
AVIN
2.5
5.5
V
Output Voltage Range (Note 3)
VOUT
0.75
3.3
V
Output Current
IOUT
0
9
A
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 4)
θJA
15
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
1.5
°C/W
Thermal Shutdown
TSD
150
°C
Thermal Shutdown Hysteresis
TSDH
35
°C
Note 1: PVIN rising and falling slew rates cannot be outside of specification. PVIN should rise monotonically into
regulation. Filter PVIN with proper input bulk capacitance so that the input AC ripple in regulation is less than ±1V of the
regulation voltage. See Input Capacitor Selection for details.
Note 2: For accurate power up sequencing, use a fast ENABLE logic (>3V/100µs) after both AVIN and PVIN are high.
Tying ENABLE to AVIN may result in a startup delay due to a slow ENABLE logic.
Note 3: Dropout: Maximum VOUT ≤ VIN - 2.5V
Note 4: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
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10107
June 2, 2015
Rev C
EN2392QI
Electrical Characteristics
NOTE: VIN=12V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
Operating Input
Voltage
PVIN
Controller Input
Voltage
AVIN
TEST CONDITIONS
MIN
TYP
MAX
UNITS
4.5
13.2
V
3
5.5
V
AVIN Under Voltage
Lock-out rising
AVINUVLOR
Voltage above which UVLO is not
asserted
2.5
2.75
3
V
AVIN Under Voltage
Lock-out falling
AVINOVLOF
Voltage below which UVLO is
asserted
2.1
2.35
2.6
V
AVIN pin Input Current
Internal Linear
Regulator Output
Voltage
IAVIN
11
mA
AVINO
3.4
V
IPVINS
PVIN=12V, AVIN=3.4V, ENABLE=0V
2
mA
IAVINS
PVIN=12V, AVIN=3.4V, ENABLE=0V
300
µA
Feedback Pin Voltage
VFB
Feedback Pin Voltage
VFB
Feedback pin Input
Leakage Current
IFB
Feedback node voltage at:
VIN = 12V, ILOAD = 0, TA = 25°C Only
Feedback node voltage at:
4.5V ≤ VIN ≤ 13.2V
0A ≤ ILOAD ≤ 9A, TA = -40 to 85°C
VFB pin input leakage current
(Note 5)
Shut-Down Supply
Current
VOUT Rise Time
Soft Start Capacitor
Range
Output Capacitance
Range
Continuous Output
Current
Over Current Trip
Level
tRISE
CSS = 47nF (Note 5, Note 6, Note 7)
IOUT_MAX_CONT
IOCP
0.60
0.606
V
0.588
0.60
0.612
V
5
nA
-5
1.96
2.8
3.64
ms
10
47
68
nF
VIN = 12V
VOUT = 3.3V; RFS = 22kΩ
See Table 3 for other output voltages
(Note 5)
80
200
800
µF
VIN = 12V
VOUT ≤ 1.0V; RFS = 3.01kΩ
See Table 3 for other output voltages
(Note 5)
80
200
2200
µF
9
A
CSS_RANGE
COUT
0.594
Subject to thermal de-rating
VIN = 12V
0
9.2
12
Short Circuit Average
Input Current
IIN_OCP
ENABLE Logic High
VENABLE_HIGH
4.5V ≤ VIN ≤ 13.2V; (Note 2)
ENABLE Logic Low
VENABLE_LOW
4.5V ≤ VIN ≤ 13.2V;
ENABLE Hysteresis
ENHYS
200
mV
TENLOCKOUT
8
ms
ENABLE Lockout
Time
Short = 10mΩ (Note 8)
100
mA
1.25
AVIN
V
0
0.95
V
www.altera.com/enpirion Page 5
10107
June 2, 2015
Rev C
EN2392QI
PARAMETER
ENABLE pin Input
Current
SYMBOL
IENABLE
TEST CONDITIONS
TYP
MAX
UNITS
AVIN = 5.5V
ENABLE = 1.8V;
ENABLE = 3.3V;
ENABLE = 5.5V;
5
11
23
8
18
32
µA
RFS = 3.01kΩ
1.0
Switching Frequency
FSW
External SYNC Clock
Frequency Lock
Range
FPLL_LOCK
Range of SYNC clock frequency (See
Table 1)
S_IN Threshold – Low
VS_IN_LO
S_IN Clock Logic Low Level (Note 5)
S_IN Threshold – High
VS_IN_HI
S_IN Clock Logic High Level (Note 5)
S_OUT Threshold –
Low
VS_OUT_LO
S_OUT Clock Logic Low Level
(Note 5)
S_OUT Threshold –
High
VS_OUT_HI
S_OUT Clock Logic High Level
(Note 5)
POKLT
Percentage of Nominal Output
Voltage for POK to be Low
POK Lower Threshold
MIN
0.9
1.8
1.8
MHz
1.8
MHz
0.8
V
2.5
V
0.8
V
2.5
V
90
%
POK Output low
Voltage
VPOKL
With 4mA Current Sink into POK
0.4
V
POK Output Hi
Voltage
VPOKH
PVIN Range: 4.5V ≤ VIN ≤ 13.2V
AVIN
V
1
µA
0.8
V
POK pin VOH leakage
current
IPOKL
POK High (Note 5)
M/S Pin Logic Low
VT-LOW
Tie Pin to GND
M/S Pin Logic High
VT-HIGH
Pull up to AVIN Through an External
Resistor REXT
M/S Pin Input Current
Note
Note
Note
Note
5:
6:
7:
8:
IM/S
REXT = 15kΩ;
AVIN = 3.4V;
AVIN = 5.5V;
1.8
V
65
175
µA
Parameter not production tested but is guaranteed by design.
Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.
VOUT Rise Time Accuracy does not include soft-start capacitor tolerance.
Output short circuit condition was performed with load impedance that is greater than or equal to 10mΩ.
www.altera.com/enpirion Page 6
10107
June 2, 2015
Rev C
EN2392QI
Typical Performance Curves
Efficiency vs. Output Current
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
100
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
10
VOUT = 1.0V
CONDITIONS
VIN = 12.0V
Single Supply
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
0
0
0
1
5
2
3
4
6
OUTPUT CURRENT (A)
7
8
9
0
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
9
8
7
6
4
3
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 15°C/W
11x10x3mm QFN
No Air Flow
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
8
7
3
9
8
7
6
5
4
3
VOUT = 1.0V
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 12.5°C/W
11x10x3mm QFN
Air Flow (200fpm)
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
9
4
8
Output Current De-rating
with Heat Sink
10
5
7
9
Output Current De-rating
with Air Flow (400fpm)
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 11°C/W
11x10x3mm QFN
Air Flow (400fpm)
2
3
4
5
6
OUTPUT CURRENT (A)
10
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
6
1
Output Current De-rating
with Air Flow (200fpm)
Output Current De-rating
10
5
VOUT = 1.0V
10
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
10
9
8
7
6
5
4
3
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 14°C/W
11x10x3mm QFN
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
www.altera.com/enpirion Page 7
10107
June 2, 2015
Rev C
EN2392QI
Typical Performance Curves
Output Current De-rating
w/ Heat Sink and Air Flow (400fpm)
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
Output Current De-rating
w/ Heat Sink and Air Flow (200fpm)
10
9
8
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 11.5°C/W
11x10x3mm QFN
7
6
Air Flow (200fpm)
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
5
4
3
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
10
9
8
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 10°C/W
11x10x3mm QFN
7
6
5
Air Flow (400fpm)
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
4
3
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.005
1.205
1.004
VIN = 8V
1.003
VIN = 10V
1.002
VIN = 12V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 1.2V
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
1.001
1.000
0.999
0.998
0.997
1.204
VIN = 8V
1.203
VIN = 10V
1.202
VIN = 12V
1.201
1.200
1.199
1.198
1.197
CONDITIONS
VOUT_NOM = 1.0V
0.996
CONDITIONS
VOUT_NOM = 1.2V
1.196
0.995
1.195
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
Output Voltage vs. Output Current
Output Voltage vs. Output Current
2.505
1.805
VIN = 8V
1.804
1.803
VIN = 10V
1.802
VIN = 12V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 1.0V
1.801
1.800
1.799
1.798
1.797
VIN = 8V
2.503
VIN = 10V
2.502
VIN = 12V
2.501
2.500
2.499
2.498
2.497
CONDITIONS
VOUT_NOM = 1.8V
1.796
2.504
CONDITIONS
VOUT_NOM = 2.5V
2.496
2.495
1.795
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
www.altera.com/enpirion Page 8
10107
June 2, 2015
Rev C
EN2392QI
Typical Performance Curves
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.204
CONDITIONS
VIN = 14V
VOUT_NOM = 1.2V
1.203
1.202
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.204
1.201
1.200
LOAD = 0A
1.199
LOAD = 2A
LOAD = 4A
1.198
LOAD = 6A
1.197
CONDITIONS
VIN = 12V
VOUT_NOM = 1.2V
1.203
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 2A
LOAD = 4A
1.198
LOAD = 6A
1.197
LOAD = 9A
LOAD = 9A
1.196
1.196
-40
35
60
-15
10
AMBIENT TEMPERATURE ( C)
-40
85
85
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.204
1.204
CONDITIONS
VIN = 10V
VOUT_NOM = 1.2V
1.203
1.202
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
-15
10
35
60
AMBIENT TEMPERATURE ( C)
1.201
1.200
LOAD = 0A
1.199
LOAD = 1A
LOAD = 2A
1.198
LOAD = 3A
1.197
CONDITIONS
VIN = 8V
VOUT_NOM = 1.2V
1.203
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 1A
LOAD = 2A
1.198
LOAD = 3A
1.197
LOAD = 4A
LOAD = 4A
1.196
1.196
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
INDIVIDUAL OUTPUT CURRENT (A)
Parallel Current Share Breakdown
10
9
8
MASTER
7
SLAVE
6
IDEAL
5
4
CONDITIONS
EN2390QI
VIN = 12V
VOUT = 1.2V
3
2
1
0
2
4
6
8
10
12
14
TOTAL OUTPUT CURRENT (A)
16
www.altera.com/enpirion Page 9
10107
June 2, 2015
Rev C
EN2392QI
Typical Performance Characteristics
Enable Startup/Shutdown Waveform (0A)
Enable Startup/Shutdown Waveform (3A)
ENABLE
ENABLE
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 0A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 3A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
Enable Startup/Shutdown Waveform (6A)
Enable Startup/Shutdown Waveform (9A)
ENABLE
ENABLE
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 6A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
Power Up Waveform (0A)
Power Up Waveform (4.5A)
PVIN
PVIN
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 4.5A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
www.altera.com/enpirion Page 10
10107
June 2, 2015
Rev C
EN2392QI
Typical Performance Characteristics
Power Up Waveform (6A)
Power Up Waveform (9A)
PVIN
PVIN
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 6A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
Output Ripple at 20MHz Bandwidth
VOUT = 1V
(AC Coupled)
Output Ripple at 20MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 0A
VOUT = 1.8V
(AC Coupled)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
20mV / DIV
20mV / DIV
CONDITIONS
VIN = 12V, CIN = 2x22µF (1206), COUT = 2x47µF + 100µF (1206)
CONDITIONS
VIN = 12V, CIN = 2x22µF (1206), COUT = 2x47µF + 100µF (1206)
Output Ripple at 500MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 9A
Output Ripple at 500MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 0A
VOUT = 1.8V
(AC Coupled)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
20mV / DIV
20mV / DIV
CONDITIONS
VIN = 12V, CIN = 2x22µF (1206), COUT = 2x47µF + 100µF (1206)
LOAD = 9A
CONDITIONS
VIN = 12V, CIN = 2x22µF (1206), COUT = 2x47µF + 100µF (1206)
www.altera.com/enpirion Page 11
10107
June 2, 2015
Rev C
EN2392QI
Typical Performance Characteristics
Load Transient from 0 to 3A (VOUT =1V)
Load Transient from 0 to 4.5A (VOUT =1V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
LOAD
Load Transient from 0 to 6A (VOUT =1V)
Load Transient from 0 to 9A (VOUT =1V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
Load Transient from 0 to 3A (VOUT =3.3V)
Load Transient from 0 to 4.5A (VOUT =3.3V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
LOAD
www.altera.com/enpirion Page 12
10107
June 2, 2015
Rev C
EN2392QI
Typical Performance Characteristics
Load Transient from 0 to 6A (VOUT =3.3V)
Load Transient from 0 to 9A (VOUT =3.3V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
Pre-Bias Shutdown Waveform
Pre-Bias Startup Waveform
PVIN = 12V
PVIN = 12V
ENABLE
ENABLE
VOUT
VOUT
Max Pre-Bias
<100% of Nominal
VOUT is held low
CONDITIONS
VIN = 12V (Single Supply Only)
VOUT = 1.0V, Load = 0A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
for another ~6ms
CONDITIONS
VIN = 12V (Single Supply Only)
VOUT = 1.0V, Load = 0A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
www.altera.com/enpirion Page 13
10107
June 2, 2015
Rev C
EN2392QI
Functional Block Diagram
M/S S_OUT S_IN
UVLO
Digital I/O
BTMP
PVIN
PG
Linear
Regulator
To PLL
AVINO
Thermal Limit
Current Limit
NC(SW)
Gate Drive
VOUT
7.5k
BGND
(-)
PWM
Comp
(+)
PGND
PLL/Sawtooth
Generator
FQADJ
VDDB
Compensation
Network
EAIN
Compensation
Network
(-)
Error
Amp
(+)
Power
Good
Logic
ENABLE
POK
300k
180k
SS
Soft Start
VFB
Voltage Reference Generator
Band Gap
Reference
EN2392QI
AVIN
EN_PB
AGND
Figure 4: Functional Block Diagram
Functional Description
small size input and output filter capacitors, as well
as a wide loop bandwidth within a small foot print.
Synchronous Buck Converter
The EN2392QI is a highly integrated synchronous,
buck converter with integrated controller, power
MOSFET switches and integrated inductor. The
nominal input voltage (PVIN) range is 4.5V to 13.2V
and can support up to 9A of continuous output
current. The output voltage is programmed using
an external resistor divider network. The control
loop utilizes a Type IV Voltage-Mode compensation
network and maximizes on a low-noise PWM
topology. Much of the compensation circuitry is
internal to the device. However, a phase lead
capacitor is required along with the output voltage
feedback resistor divider to complete the Type IV
compensation network.. The high switching
frequency of the EN2392QI enables the use of
Protection Features:
The power supply has the following protection
features:
• Over Current and Short Circuit Protection
• Thermal Soft-Shutdown with Hysteresis
• AVIN Under-Voltage Lockout Protection
• Pre-Bias Protection
Additional Features:
•
•
•
Switching Frequency Synchronization.
Programmable Soft-Start
Power OK Output Monitoring
www.altera.com/enpirion Page 14
10107
June 2, 2015
Rev C
EN2392QI
Modes of Operation
ENABLE Operation
The EN2392QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. The
EN2392QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Time (8ms) in order for the device to be reenabled. To ensure accurate startup sequencing
the ENABLE/DISABLE signal should be faster than
3V/100µs. A slower ENABLE/DISABLE signal may
result in a delayed startup and shutdown response.
Do not leave ENABLE floating.
Single Input Supply Application (PVIN Only):
0.22µF
47nF
PG
VIN
BTMP VDDB
PVIN
EN2392QI
10k
4.75k
C OUT
EAIN
ENABLE
2x
22µF
1206
VOUT
BGND
VOUT
RA
CA
2.26k
AVINO
1µF
REA
AVIN
1µF
47nF
RCA
VFB
SS
M/S
EN_PB
PGND
Pre-Bias Operation
PGND
FADJ
RFS
RB
RCLX
AGND
RCLX
Figure 5: Single Input Supply Schematic
In single input supply mode, the EN2392QI only
requires one input voltage rail (typically 12V). The
EN2392QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN. Also, in this single supply application, place a
resistor (RVB) between VDDB and AVIN, as shown
in Figure 5. Altera recommends RVB=4.75kΩ.
Dual Input Supply Application (PVIN and AVIN):
0.22µF
47nF
PG
VIN
BTMP VDDB
PVIN
VOUT
BGND
VOUT
EN2392QI
ON
2x
22µF
1206
OFF
VAVIN
COUT
EAIN
ENABLE
AVINO
RA
AVIN
1µF
47nF
CA
REA
RCA
VFB
SS
M/S
EN_PB
PGND
FQADJ
RFS
PGND
AGND
RCLX
RB
RCLX
Figure 6: Dual Input Supply Schematic
In dual input supply mode, two input voltage rails
are required (typically 12V for PVIN and 3.3V for
AVIN). Refer to Figure 6 for the recommended
schematic for a dual input supply application.
Since AVINO is not used, it can be left open.
The EN2392QI has a Pre-Bias feature which will
allow the regulator to startup into a pre-charged
output. The pre-biased output voltage must be
below the nominal regulation voltage; otherwise,
damage may occur during startup and shutdown.
To use this feature, the EN2392QI must be
configured to Single Supply mode, set to
standalone operation (no parallel operation) and
follow the instructions below:
• The EN_PB pin must be pulled high to AVIN
• A resistor divider must be connected from
PVIN to ENABLE to Ground (10k on top,
2.26k on the bottom) to ensure proper
shutdown. The resistor divider will disable
the device when PVIN falls below
approximately 6.8V. The resistor divider
values may be adjusted accordingly to meet
PVIN requirements. See Figure X.
• PVIN rail should be in regulation (>4.5V)
prior to being enabled.
• Since the ENABLE pin is tied to the resistor
divider to PVIN, an open drain (such as the
POK signal of another regulator or
Sequencer) should be tied to ENABLE in
order to keep the device disabled while the
PVIN rail rises into regulation.
• Once the PVIN rail is in regulation, the
ENABLE may be pulled high through the
resistor divider.
• The ENABLE rise time must be faster than
3V/100us.
The output will start up from the Pre-Bias voltage
into regulation monotonically if the instructions are
followed; otherwise, the Pre-Bias Protection feature
may not function properly and the device will
startup into a Pre-Bias output voltage. Starting up
www.altera.com/enpirion Page 15
10107
June 2, 2015
Rev C
EN2392QI
47nF
Need Fast
ENABLE Logic
(>3V/100us)
VIN
PG
0.22µF
BTMP VDDB
PVIN
10k
EN2392QI
4.75k
2x
22µF
1206
VOUT
BGND
VOUT
COUT
EAIN
ENABLE
RA
2.26k
AVINO
1µF
1.600
1.400
1.200
1.000
0.600
0
VFB
SS
2
4
6
8 10 12 14 16 18 20 22
RFS RESISTOR VALUE (kΩ)
Figure 9. RFS versus Switching Frequency
M/S
PGND
PGND
FQADJ AGND
RFS
CONDITIONS
VIN = 6V to 12V
VOUT = 0.8V to 3.3V
0.800
RCA
EN_PB
47nF
Rfs vs. SW Frequency
1.800
REA
AVIN
1µF
CA
resistor values are allowed. Do not use lower RFS
values than recommendations as that may set the
frequency too low and cause inductor saturation.
When synchronizing multiple devices, use the
highest recommended switching frequency of the
devices.
SWITCHING FREQUENCY (MHz)
into a Pre-Bias voltage without the Pre-Bias
Protection feature enabled can lead to device
damage. When using the Pre-Bias feature, the
device must be disabled using the ENABLE pin
prior to PVIN falling out of regulation (<4.5V),
otherwise damage may occur during shutdown. To
disable the Pre-Bias feature pull the EN_PB pin
directly to ground. Do not leave the EN_PB pin
floating. See Typical Performance Characteristics
for an example of Pre-Bias Protection. See Figure
X for a typical schematic with Pre-Bias Protection
enabled.
RCLX
RB
PVIN
RCLX
Figure X. Pre-Bias Application Circuit
12V
Frequency Synchronization
The switching frequency of the EN2392QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2392QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phaselocks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.9MHz to 1.8MHz. The
external clock frequency must be within ±10% of
the nominal switching frequency set by the RFS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the RFS
resistor.
The efficiency performance of the EN2392QI for
various PVIN/VOUT combinations can be optimized
by adjusting the switching frequency. Table 1
shows recommended RFS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN2392QI. Using higher RFS
VOUT
3.3V
2.5V
1.8V
1.5V
1.2V
≤1.0V
RFS
22k
10k
4.87k
3.01k
3.01k
3.01k
Typical fsw
1.42 MHz
1.3 MHz
1.15 MHz
1.0 MHz
1.0 MHz
1.0 MHz
Table 1: Recommended RFS Values.
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin and
the AGND pin. During start-up of the converter, the
reference voltage to the error amplifier is linearly
increased to its final level by an internal current
source of approximately 10µA. The soft-start time is
measured from when VIN > VUVLOR and ENABLE pin
voltage crosses its logic high threshold to when
VOUT reaches its programmed value. The total softstart time can be calculated by:
Soft Start Time (ms): TSS ≈ Css [nF] x 0.06
Typical soft-start time is approximately 2.8ms with
SS capacitor value of 47nF.
www.altera.com/enpirion Page 16
10107
June 2, 2015
Rev C
EN2392QI
POK Operation
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Over Current Protection
4.5V to
13.2V
VOUT
3.3V
2.5V
1.8V
1.5V
1.2V
≤1.0V
RCLX
31.6k
34.8k
35.7k
34.8k
39.2k
40.2k
AVIN Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start switching until the AVIN input voltage is above
the specified minimum voltage. Hysteresis, input
de-glitch and output leading edge blanking ensures
high noise immunity and prevents false UVLO
triggers.
Master / Slave (Parallel) Operation:
RFS
22k
10k
4.87k
3.01k
3.01k
3.01k
Table 2: Recommended RCLX Values
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temperature exceeds
approximately 150°C. The device will go through a
soft-shutdown and allow the output to discharge in
a controlled manner. This prevents excessive
Parallel Current Share Breakdown
INDIVIDUAL OUTPUT CURRENT (A)
The current limit function is achieved by sensing
the current flowing through a high-side sense
PFET. If the current exceeds the OCP threshold,
the switching cycle is terminated and an OCP
counter is incremented. If the counter value
reaches 32 OCP cycles, the device will shut down
as described below. If there are 8 consecutive
cycles that do not exceed the OCP threshold, the
counter will reset. Once the OCP counter has
reached 32 cycles, the MOSFET switches will tristate and the soft start capacitor will be discharged.
After approximately 32ms the device will attempt a
restart. If the OCP condition persists, the device
will enter a hiccup mode until the OCP condition is
removed. The OCP trip point depends on PVIN,
VOUT, RCLX, RFS and is meant to protect the
device from damage. OCP is not an adjustable
threshold. Follow Table 2 for recommended RCLX
and RFS values to set the current limit above 9A
under normal operating conditions. Not following
Table 2 may result in current limit being too low or
too high.
Note: Do not leave RCLX pin floating.
PVIN
output ringing in the event of a thermal fault
condition. After a thermal shutdown event, when
the junction temperature drops by approximately
35°C, the converter will re-start with a normal softstart.
10
9
8
MASTER
7
SLAVE
6
IDEAL
5
4
CONDITIONS
EN2390QI
VIN = 12V
VOUT = 1.2V
3
2
1
0
2
4
6
8
10
12
14
TOTAL OUTPUT CURRENT (A)
16
Figure 10. Parallel Current Matching
Up to four EN2392QI devices may be connected in
a Master/Slave configuration to handle larger load
currents. The maximum output current for each
parallel device will need to be de-rated by 20
percent so that no devices will over current due to
current mis-match. The Master device’s switching
clock may be phase-locked to an external clock
source via the S_IN pin or left open and use its
default switching frequency. The device is placed in
Master mode by pulling the M/S pin low or in Slave
mode by pulling M/S pin high. Note that the M/S pin
is also pulled low for standalone mode. In Master
mode, the internal PWM signal is output on the
S_OUT pin. This PWM signal from the Master is
fed to the Slave device at its S_IN input. The Slave
device acts like an extension of the power FETs in
the Master. The inductor in the Slave prevents
crow-bar currents from Master to Slave due to
timing delays. Parallel operation in dual supply
mode is shown in Figure 11. Single supply mode
operation may also be implemented similarly. Note
that only critical components are shown. The red
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10107
June 2, 2015
Rev C
EN2392QI
text and red lines indicate the important parallel
operation connections and care should be taken in
layout to ensure low impedance between those
paths. The parallel current matching is illustrated in
Figure 10.
Note 2:
The Master and Slave VOUTs should be
connected with very low impedance as
shown by the double red line connections
in parallel.
Note 1:
The Master and Slave VINs should be connected
with very low impedance as shown by the double
red line connections in parallel.
VIN
ENA
22µF
1206
AVIN
AVIN
2x
47µF
1206
EN2392QI
(MASTER)
RA CA
VFB
SS
47nF
VOUT
VOUT
PVIN
R1
M/S
PGND
PGND
S_OUT AGND
RB
FQADJ
S_IN
VOUT
PVIN
AVIN
22µF
1206
ENA
2x
47µF
1206
EN2392QI
(SLAVE)
AVIN
VFB
M/S
open
SS
PGND
PGND
FQADJ
AGND
47nF
Slave #1
Note 4:
Up to 3 Slaves may
be used in parallel
with the Master
Note 3:
The Master and Slave PGNDs should be
connected with very low impedance as shown by
the double red line connections in parallel.
Figure 11. Parallel Operation Illustration
www.altera.com/enpirion Page 18
10107
June 2, 2015
Rev C
EN2392QI
Application Information
Output Voltage Programming and Loop
Compensation
The EN2392QI uses a Type IV Voltage Mode
compensation network. Type IV Voltage Mode
control is a proprietary Altera Enpirion control
scheme that maximizes control loop bandwidth to
deliver excellent load transient responses and
maintain output regulation with pin point accuracy.
For ease of use, most of this network has been
customized and is integrated within the device
package.
The EN2392QI output voltage is programmed using
a simple resistor divider network (RA and RB). The
feedback voltage at VFB is nominally 0.6V. RA is
predetermined based on Table 5 and RB can be
calculated based on Figure 12. The values
recommended for COUT, CA, RCA and REA make up
the external compensation of the EN2392QI. It will
vary with each PVIN and VOUT combination to
optimize on performance. The EN2392QI solution
can be optimized for either smallest size or highest
performance. Please see Table 5 for a list of
recommended RA, CA, RCA, REA and COUT values for
each solution. Since VFB is a sensitive node, do
not touch the VFB node while the device is in
operation as doing so may introduce parasitic
capacitance into the control loop that causes the
device to behave abnormally and damage may
occur.
VOUT
VOUT
COUT
EAIN
RA
CA
REA
RCA
VFB
VFB = 0.6V
PGND
RB =
EN2392QI
VFB x RA
VOUT - VFB
Figure 12: VOUT Resistor Divider & Compensation
Components. See Table 5 for details.
should be used as input capacitors for this
converter. The dielectric must be X5R or X7R
rated. Y5V or equivalent dielectric formulations
must not be used as these lose too much
capacitance with frequency, temperature and
bias voltage. In some applications, lower value
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling. Distance from the input power source
to the input of the device creates parasitic
inductance which can increase input ripple during
startup or in steady state operation. Be sure the
input is properly filtered with additional bulk
capacitance so that the input AC ripple on PVIN is
less than 1V peak-to-peak. Placing capacitors in
parallel reduces the impedance and will result in
lower ripple voltage. Table 2 contains a list of
recommended input capacitors.
Recommended Input Capacitors
Description
MFG
P/N
22µF, 16V, X5R,
10%, 1206
Murata
GRM31CR61C226ME15
22µF, 16V, X5R,
20%, 1206
Taiyo
Yuden
EMK316ABJ226ML- T
Table 2: Recommended Input Capacitors
Output Capacitor Selection
As seen from Table 5, the EN2392QI has been
optimized for use with one 100µF/1206 plus two
47µF/1206 output capacitors for best performance.
For smallest solution size, various combinations of
output capacitance may be used. See Table 5 for
details. Low ESR ceramic capacitors are required
with X5R or X7R rated dielectric formulation. Y5V
or equivalent dielectric formulations must not be
used as these lose too much capacitance with
frequency, temperature and bias voltage. Table 4
contains a list of recommended output capacitors.
Extra bulk capacitors may be used to improve load
transient response at the load. The maximum
output capacitance allowed on the EN2392QI
depends on the output voltage. Table 3 shows the
maximum output capacitance based on output
voltage. The maximum output capacitance includes
all capacitors connected from the output power
plain to ground.
Input Capacitor Selection
The EN2392QI requires two 22µF/1206 input
capacitors. Low-cost, low-ESR ceramic capacitors
www.altera.com/enpirion Page 19
10107
June 2, 2015
Rev C
EN2392QI
1
VOUT
RFS
COUT_MAX
Snubber
3.3V
22k
800µF
4.7Ω + 680pF
2.5V
10k
1200µF
4.7Ω + 680pF
1.8V
4.87k
1600µF
4.7Ω + 680pF
1.5V
3.01k
1800µF
4.7Ω + 680pF
1.2V
3.01k
2000µF
4.7Ω + 680pF
≤1.0V
3.01k
2200µF
4.7Ω + 680pF
Table 3: Maximum Output Capacitance
If the maximum output capacitance in the
application exceeds 50% of the COUT_MAX value
in Table 3, then a “snubber” circuit is required (See
Figure 1). The “snubber” circuit is a series resistor
and capacitor from the NC(SW) pin to PGND. The
“snubber” values are optimized for the EN2392QI
and should be followed to within 10% of the
recommendations. Due to the added power
dissipation, using the “snubber” will decrease the
converter efficiency by around 1 percent. It is
recommended to use at least a ¼W resistor at
1206 case size or greater due to power dissipation.
The capacitor should be at least 0603 case size.
Z Total
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
Recommended Output Capacitors
Description
47µF, 6.3V, X5R,
20%, 1206
47µF, 10V, X5R,
20%, 1206
22µF, 10V, X5R,
20%, 0805
22µF, 10V, X5R,
20%, 0805
100µF, 6.3V, X5R,
20%, 1206
MFG
P/N
Murata
GRM31CR60J476ME19L
Taiyo
Yuden
LMK316BJ476ML- T
Panasonic
ECJ-2FB1A226M
Taiyo
Yuden
LMK212BJ226MG- T
Murata
GRM31CR60J107ME39L
Taiyo
Yuden
JMK316BJ107ML-T
Table 4: Recommended Output Capacitors
Since additional bulk capacitance changes the LC
double pole of the Voltage Mode Control
architecture, be sure to have at least 4mΩ of
separation between the feedback sense point and
the additional bulk capacitors. Be sure to follow the
Best
Performance
external
compensation
recommendations in Table 5.
The output capacitance can also influence the
output ripple. Output ripple voltage is determined by
the aggregate output capacitor impedance.
Capacitor impedance, denoted as Z, is comprised
of capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
www.altera.com/enpirion Page 20
10107
June 2, 2015
Rev C
EN2392QI
Best Performance
Smallest Solution Size
CIN = 2x22µF/1206
CIN = 2x22µF/1206
V OUT ≤ 1.8V, COUT = 2x47µF/0805
1.8V < V OUT ≤ 3.3V, COUT = 2x47µF/1206
COUT = 100µF/1206 + 2x47µF/1206
RA = 200 kΩ
PVIN
(V)
13.2V
12V
10V
8V
6.6V
5V
RA = 75k
RCA
REA
(kΩ
(kΩ)
)
8.2
Open
VOUT
(V)
CA
(pF)
RCA
(kΩ)
REA
(kΩ)
Ripple
(m V)
Deviation
(m V)
0.9V
15
18
0
5.83
44
0.9V
CA
(pF
)
18
1.2V
15
22
0
7.22
48
1.2V
18
8.2
Open
21
104
1.5V
18
22
0
8.63
38
1.5V
18
8.2
Open
27
110
1.8V
15
22
0
10.8
50
1.8V
18
8.2
Open
35
120
2.5V
27
5.1
33
14.6
72
2.5V
15
8.2
Open
54
150
3.3V
22
8.2
33
26.1
76
3.3V
10
8.2
Open
81
215
0.9V
27
18
0
5.21
40
0.9V
27
5.1
Open
15
96
1.2V
22
22
0
6.7
36
1.2V
27
5.1
Open
21
104
1.5V
18
22
0
8.98
44
1.5V
27
5.1
Open
27
112
1.8V
18
22
0
10
50
1.8V
27
5.1
Open
34
130
2.5V
27
5.1
33
12.6
76
2.5V
22
5.1
Open
52
162
3.3V
22
8.2
33
23.6
72
3.3V
15
5.1
Open
77
221
PVIN
(V)
13.2V
12V
VOU
T (V)
Rippl
e
(m V)
15
Deviatio
n (m V)
93
0.9V
27
18
0
5.01
44
0.9V
56
2
Open
15
99
1.2V
22
22
0
6.28
40
1.2V
56
2
Open
20
107
1.5V
18
22
0
8.57
54
1.5V
39
2
Open
26
122
10V
1.8V
18
22
0
9.44
60
1.8V
39
2
Open
33
126
2.5V
33
5.1
33
11
64
2.5V
33
2
Open
50
169
3.3V
27
8.2
33
21.6
68
3.3V
22
2
Open
71
241
0.9V
27
18
0
4.9
44
0.9V
100
0
Open
15
108
1.2V
22
22
0
5.82
48
1.2V
100
0
Open
20
113
1.5V
22
22
0
7.48
56
1.5V
82
0
Open
25
122
1.8V
22
22
0
8.01
54
1.8V
68
0
Open
31
136
2.5V
33
5.1
33
10.7
76
2.5V
47
0
Open
46
183
3.3V
27
8.2
33
20.5
84
3.3V
33
0
Open
62
253
0.9V
33
18
0
4.58
46
0.9V
100
0
Open
14
121
1.2V
27
22
0
5.28
54
1.2V
100
0
Open
19
128
1.5V
27
22
0
6.44
54
1.5V
100
0
Open
24
138
1.8V
22
22
0
7.2
58
1.8V
100
0
Open
29
149
2.5V
3.3V
0.9V
33
33
39
5.1
8.2
18
33
33
0
11.4
18.4
4.1
84
96
54
2.5V
3.3V
0.9V
68
47
100
0
0
0
Open
Open
Open
41
53
13
188
239
152
1.2V
33
22
0
5.1
62
1.2V
100
0
Open
18
161
8V
6.6V
5V
1.5V
27
22
0
6.2
66
1.5V
100
0
Open
22
177
1.8V
27
22
0
7.02
68
1.8V
100
0
Open
25
183
2.5V
39
5.1
33
9.84
104
2.5V
100
0
Open
33
216
Table 5: RA, CA, RCA and REA Values for Various PVIN/VOUT Combinations: Best Performance vs. Smallest Solution
Size. Use the equations in Figure 12 to calculate RB. Output Ripple is measured at no load and Nominal
Deviation is for a 9A load transient step in one direction. For a voltage in between the specified output voltages,
choose compensation values of the lower output voltage setting.
www.altera.com/enpirion Page 21
10107
June 2, 2015
Rev C
EN2392QI
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
The Altera Enpirion EN2392QI DC-DC converter is
packaged in a 10x11x3mm 76-pin QFN package.
The QFN package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
150°C.
The following example and calculations illustrate
the thermal performance of the EN2392QI.
Example:
VIN = 12V
VOUT = 1.2V
PIN ≈ 10.8W / 0.8 ≈ 13.17W
The power dissipation (PD ) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 13.17W – 10.8W ≈ 2.37W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN2392QI has
a θJA value of 15 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 2.37W x 15°C/W = 35.56°C ≈ 36°C
The junction temperature (T J ) of the device is
approximately the ambient temperature (T A) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
T J ≈ 25°C + 36°C ≈ 61°C
First calculate the output power.
POUT = 1.2V x 9A = 10.8W
Next, determine the input power based on the
efficiency (η) shown in Figure 13.
Efficiency vs. Output Current
100
80
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
VOUT = 1.0V
The maximum operating junction temperature
(T JMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (T AMAX) allowed can
be calculated.
T AMAX = T JMAX – PD x θJA
≈ 125°C – 36°C ≈ 89°C
The maximum ambient temperature the device can
reach is 89°C given the input and output conditions.
Note that the efficiency will be slightly lower at
higher temperatures and this calculation is an
estimate. Check De-rating Curves for guaranteed
maximum output current over temperature.
90
EFFICIENCY (%)
PIN = POUT / η
T J = T A + ΔT
IOUT = 9A
10
η = POUT / PIN = 82% = 0.82
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
0
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
9
Figure 13: Efficiency vs. Output Current
For VIN = 12V, VOUT = 1.2V at 9A, η ≈ 82%
www.altera.com/enpirion Page 22
10107
June 2, 2015
Rev C
EN2392QI
Engineering Schematic
Figure 14: Typical Engineering Schematic
www.altera.com/enpirion Page 23
10107
June 2, 2015
Rev C
EN2392QI
Layout Recommendation
Figure 15: Critical Component Layout for Minimum
Footprint (Top Layer). See Figure 14 for schematic.
This layout only shows the critical components and top
layer traces for minimum footprint in single-supply,
master mode. Alternate circuit configurations & other
low-power pins need to be connected and routed
according to customer application. Please see the
Gerber files at www.altera.com/enpirion for details on all
layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN2392QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EN2392QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The thermal pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops. If vias cannot
be placed under the capacitors, then place them on
both sides of the slit in the top layer PGND copper.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. AVINO powers
AVIN in single supply mode. AVIN and AVINO
should have a decoupling capacitor close to each
of their pins. Refer to Figure 15.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure13.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines underneath the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling
into the node. Contact Altera MySupport for any
remote sensing applications.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the VFB pin (Refer to Figure 15). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND instead
of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera provides schematic and layout
reviews for all customer designs. Contact Altera
MySupport
for
detailed
support
(www.altera.com/mysupport).
www.altera.com/enpirion Page 24
10107
June 2, 2015
Rev C
EN2392QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package as shown in Figure 16.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN2392QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 16 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult the
EN2392QI QFN Package Soldering Guidelines for more details and recommendations.
Figure 16: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
www.altera.com/enpirion Page 25
10107
June 2, 2015
Rev C
EN2392QI
Recommended PCB Footprint
Figure 17: EN2392QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad (shown in blue) is based on Altera’s manufacturing recommendations.
www.altera.com/enpirion Page 26
10107
June 2, 2015
Rev C
EN2392QI
Package and Mechanical
Figure 18: EN2392QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
www.altera.com/enpirion Page 27
10107
June 2, 2015
Rev C