HD74AC175 Quad D-Type Flip-Flop REJ03D0257–0200Z (Previous ADE-205-377 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the Low-to-High clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when Low. Features • Edge-Triggered D-Type Inputs • Buffered Positive Edge-Triggered Clock • Asynchronous Common Reset • True and Complement Output • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC175AFPEL SOP-16 pin (JEITA) FP-16DAV FP HD74AC175ARPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) HD74AC175TELL T ELL(2,000 pcs/reel) TSSOP-16 pin TTP-16DAV EL (2,000 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement MR 1 16 VCC Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 GND 8 9 CP (Top view) Rev.2.00, Jul.16.2004, page 1 of 7 HD74AC175 Logic Symbol D0 D1 D2 D3 CP MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Pin Names D0 to D3 CP MR Q0 to Q3 Q0 to Q 3 Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs Functional Description The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the Low-to-High clock (CP) transition, causing individual Q and Q outputs to follow. A Low input on the Master Reset (MR) will force all Q outputs Low and Q outputs High independent of Clock or Data inputs. The HD74AC175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Truth Table Inputs @ tn, MR = H Dn L H H : L : tn : tn + 1 High Voltage Level Low Voltage Level Bit Time before Clock Pulse : Bit Time after Clock Pulse Rev.2.00, Jul.16.2004, page 2 of 7 Outputs @ tn+1 Qn L Qn H H L HD74AC175 Logic Diagram MR CP D3 D2 D D1 Q D CP Q CD Q D CP Q CD Q3 Q3 D0 Q D CP Q CD Q2 Q2 Q CP Q CD Q1 Q1 Q0 Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Absolute Maximum Ratings Item Symbol Ratings –0.5 to 7 Unit V Supply voltage VCC DC input diode current IIK –20 20 mA mA DC input voltage DC output diode current VI IOK –0.5 to Vcc+0.5 –50 V mA DC output voltage VO 50 –0.5 to Vcc+0.5 mA V DC output source or sink current DC VCC or ground current per output pin IO ICC, IGND ±50 ±50 mA mA Storage temperature Tstg –65 to +150 °C Condition VI = –0.5V VI = Vcc+0.5V VO = –0.5V VO = Vcc+0.5V Recommended Operating Conditions Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Rev.2.00, Jul.16.2004, page 3 of 7 Symbol VCC 2 to 6 Ratings V Unit VI, VO Ta 0 to VCC –40 to +85 V °C tr, tf 8 ns/V Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V HD74AC175 DC Characteristics Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25°°C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.1 — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOL = 24 mA Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics Item Symbol VCC (V)*1 Ta = +25°C CL = 50 pF Min Typ Max Ta = –40°C to +85°C CL = 50 pF Min Max Unit Maximum clock frequency fmax 3.3 5.0 149 187 — — — — 139 187 — — MHz Propagation delay CP to Qn or Qn tPLH 3.3 5.0 1.0 1.0 9.5 7.0 12.0 9.0 1.0 1.0 13.5 9.5 ns Propagation delay CP to Qn or Qn tPHL 3.3 5.0 1.0 1.0 8.5 6.0 13.0 9.5 1.0 1.0 14.5 10.5 ns Propagation delay MR to Qn tPLH 3.3 5.0 1.0 1.0 7.5 5.5 12.5 9.0 1.0 1.0 13.5 10.0 ns Propagation delay MR to Qn tPHL 3.3 5.0 1.0 1.0 8.5 6.0 11.0 8.5 1.0 1.0 12.5 9.0 ns Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 4 of 7 HD74AC175 AC Operating Requirements Ta = +25°C CL = 50 pF Item Set-up time, HIGH or LOW Symbol VCC (V)*1 Typ tsu 3.3 2.0 Dn to CP Hold time, HIGH or LOW th 5.0 3.3 Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 4.5 4.5 ns 1.0 0 3.0 1.0 3.0 1.0 ns tw 5.0 3.3 0 2.5 1.0 4.5 1.0 4.5 ns MR pulse width, LOW tw 5.0 3.3 2.0 2.5 3.5 4.5 3.5 5.0 ns Recovery time MR to CP trec 5.0 3.3 2.0 –2.0 3.5 0.0 3.5 0.0 ns 5.0 –1.0 0.0 0.0 Dn to CP CP pulse width HIGH or LOW Note: Unit 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 5 of 7 Symbol CIN CPD Typ 4.5 45.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC175 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 6 of 7 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g HD74AC175 As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 *0.20 ± 0.05 1.0 0.13 M Rev.2.00, Jul.16.2004, page 7 of 7 *0.15 ± 0.05 1.10 Max *Ni/Pd/Au plating 0.10 0.07 +0.03 –0.04 6.40 ± 0.20 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. 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