HD74AC157 Quad 2-Input Multiplexer REJ03D0252–0200Z (Previous ADE-205-371 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC157 is a high-speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four outputs present the selected data in the true (noninverted) form. The HD74AC157 can also be used as a function generator. Features • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC157AFPEL SOP-16 pin (JEITA) FP-16DAV FP HD74AC157ARPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) HD74AC157TELL T ELL(2,000 pcs/reel) TSSOP-16 pin TTP-16DAV EL (2,000 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement 16 VCC S 1 I0a 2 15 E I1a 3 14 I0c Za 4 13 I1c I0b 5 12 Zc I1b 6 11 I0d Zb 7 10 I1d GND 8 9 Zd (Top view) Rev.2.00, Jul.16.2004, page 1 of 7 HD74AC157 Logic Symbol E I0a I1a I0b I1b I0c I1c Iod I1d S Za Zb Zc Zd Pin Names I0a to I0d I1a to I1d E S Za to Zd Source 0 Data Inputs Source 1 Data Inputs Enable Input Select Input Outputs Functional Description The HD74AC157 is a quad 2-input multiplexer. It selects four bits of data from two sources under the control of a common Select input (S). The Enable input (E) is active-Low. when E is High, all of the outputs (Z) are forced Low regardless of all other inputs. The HD74AC157 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Za = E•(I1a•S + I0a•S) Zb = E•(I1b•S + I0b•S) Zc = E•(I1c•S + I0c•S) Zd = E•(I1d•S + I0d•S) A common use of the HD74AC157 is the moving of data from two groups of register to four common output busses. The particular register from which the data comes is determined by the state of the Select input. A less obvious use is as a function generator. The HD74AC157 can generate any four of the sixteen different functions of two variables with one variable common. This is useful for implementing gating functions. Truth Table Inputs E H L L L L H : L : X : S X H H L L High Voltage Level Low Voltage Level Immaterial Rev.2.00, Jul.16.2004, page 2 of 7 Output I0 X X X L H I1 X L H X X Z L L H L H HD74AC157 Logic Diagram I0a I1a I0b Za I1b I0c Zb I1c I0d Zc E I1d S Zd Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Absolute Maximum Ratings Item Symbol Ratings –0.5 to 7 Unit V Supply voltage VCC DC input diode current IIK –20 20 mA mA DC input voltage DC output diode current VI IOK –0.5 to Vcc+0.5 –50 V mA DC output voltage VO 50 –0.5 to Vcc+0.5 mA V DC output source or sink current DC VCC or ground current per output pin IO ICC, IGND ±50 ±50 mA mA Storage temperature Tstg –65 to +150 °C Condition VI = –0.5V VI = Vcc+0.5V VO = –0.5V VO = Vcc+0.5V Recommended Operating Conditions Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Rev.2.00, Jul.16.2004, page 3 of 7 Symbol VCC 2 to 6 Ratings V Unit VI, VO Ta 0 to VCC –40 to +85 V °C tr, tf 8 ns/V Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V HD74AC157 DC Characteristics Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25°°C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.1 — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOL = 24 mA Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics: HD74AC157 Item Symbol VCC (V)*1 Ta = +25°C CL = 50 pF Min Typ Max Ta = –40°C to +85°C CL = 50 pF Min Max Unit Propagation delay S to Zn tPLH 3.3 5.0 1.0 1.0 7.0 5.5 11.5 9.0 1.0 1.0 13.0 10.0 ns Propagation delay S to Zn tPHL 3.3 5.0 1.0 1.0 6.5 5.0 11.0 8.5 1.0 1.0 12.0 9.5 ns Propagation delay E to Zn tPLH 3.3 5.0 1.0 1.0 7.0 5.5 11.5 9.0 1.0 1.0 13.0 10.0 ns Propagation delay E to Zn tPHL 3.3 5.0 1.0 1.0 6.5 5.5 11.0 9.0 1.0 1.0 12.0 9.5 ns Propagation delay In to Zn tPLH 3.3 5.0 1.0 1.0 5.0 4.0 8.5 6.5 1.0 1.0 9.0 7.0 ns Propagation delay In to Zn tPHL 3.3 5.0 1.0 1.0 5.0 4.0 8.0 6.5 1.0 1.0 9.0 7.0 ns Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 4 of 7 HD74AC157 Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 5 of 7 Symbol CIN CPD Typ 4.5 50.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC157 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 6 of 7 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g HD74AC157 As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 *0.20 ± 0.05 1.0 0.13 M Rev.2.00, Jul.16.2004, page 7 of 7 *0.15 ± 0.05 1.10 Max *Ni/Pd/Au plating 0.10 0.07 +0.03 –0.04 6.40 ± 0.20 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. 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