AT91SAM9261-EK Evaluation Board User Guide

AT91SAM9261-EK Evaluation Board
..............................................................................................
User Guide
AT91SAM9261-EK Evaluation Board User Guide
6198C–ATARM–15-Dec-06
Table of Contents
Section 1
Overview............................................................................................... 1-1
1.1
1.2
1.3
Scope........................................................................................................1-1
Deliverables ..............................................................................................1-1
The AT91SAM9261-EK Evaluation Board ................................................1-1
Section 2
Setting Up the AT91SAM9261-EK
Evaluation Board .................................................................................. 2-1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Electrostatic Warning ................................................................................2-1
Requirements............................................................................................2-1
Layout .......................................................................................................2-2
Powering Up the Board .............................................................................2-4
Backup Power Supply ...............................................................................2-4
Getting Started..........................................................................................2-4
AT91SAM9261-EK Block Diagram ...........................................................2-5
Section 3
Board Description ................................................................................. 3-1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
AT91SAM9261 Microcontroller .................................................................3-1
AT91SAM9261 Block Diagram .................................................................3-4
Memory .....................................................................................................3-5
Clock Circuitry ...........................................................................................3-5
Reset Circuitry ..........................................................................................3-5
Shutdown Controller .................................................................................3-5
Power Supply Circuitry..............................................................................3-5
Remote Communication ...........................................................................3-5
Audio Stereo Interface ..............................................................................3-5
User Interface ...........................................................................................3-5
Debug Interface ........................................................................................3-6
Expansion Slot ..........................................................................................3-6
PIO Usage ...............................................................................................3-7
Section 4
Configuration Straps ............................................................................. 4-1
4.1
Configuration Straps .................................................................................4-1
Section 5
Schematics ........................................................................................... 5-1
5.1
AT91SAM9261-EK Evaluation Board User Guide
Schematics ...............................................................................................5-1
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6198C–ATARM–15-Dec-06
Section 6
Errata .................................................................................................... 6-1
6.1
JTAGSEL S5 Footprint Selector ...............................................................6-1
Section 7
Revision History.................................................................................... 7-1
7.1
-ii
6198C–ATARM–15-Dec-06
Revision History ........................................................................................7-1
AT91SAM9261-EK Evaluation Board User Guide
Section 1
Overview
1.1
Scope
The AT91SAM9261-EK evaluation kit is an effective platform for evaluating chip performance and developing code for applications based on the AT91SAM9261.
This guide is a description of the hardware included in the AT91SAM9261-EK evaluation
kit. Software files are available on the DVD-ROM included in the kit and described in
“Deliverables” below.
1.2
Deliverables
The AT91SAM9261-EK package contains the following items:
! an AT91SAM9261-EK board
! one A/B-type USB cable
! one serial RS232 cable
! one RJ45 crossed Ethernet cable
! universal input AC/DC power supply with US and EU plug adapter
! one DVD-ROM containing summary and full datasheets, datasheets with electrical
and mechanical characteristics, application notes and getting started documents for
all development boards and AT91 microcontrollers. An AT91 software package with C
and assembly listings is also provided. This allows the user to begin evaluating the
AT91 ARM® Thumb® 32-bit microcontroller quickly.
1.3
The
AT91SAM9261EK Evaluation
Board
The board is equipped with an AT91SAM9261 (217-ball LFBGA package) together with
the following:
! 64 Mbytes of SDRAM memory
! 256 Mbytes of NAND Flash memory
! one Atmel® serial DataFlash®
! one USB device port interface
! two USB host port interfaces
! one DBGU serial communication port
! JTAG/ICE debug interface
AT91SAM9261-EK Evaluation Board User Guide
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6198C–ATARM–15-Dec-06
Overview
! one Ethernet 100-base TX with three status LEDs
! one Atmel AT73C213 Audio DAC
! one 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight
! one Power LED and two general-purpose LEDs
! four user input pushbuttons
! one wakeup input pushbutton
! one reset pushbutton
! one DataFlash SD/MMC card slot
! two expansion footprint connectors (solder side)
! one Lithium Coin Cell Battery Retainer for 12 mm cell size
! dual pitch prototyping area
1-2
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
Section 2
Setting Up the AT91SAM9261-EK
Evaluation Board
2.1
Electrostatic
Warning
The AT91SAM9261-EK evaluation board is shipped in a protective anti-static package.
The board must not be subjected to high electrostatic potentials. A grounding strap or
similar protective device should be worn when handling the board. Avoid touching the
component pins or any other metallic element.
2.2
Requirements
In order to set up the AT91SAM9261-EK evaluation board, the following items are
required:
! the AT91SAM9261-EK evaluation board itself
! AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm
AT91SAM9261-EK Evaluation Board User Guide
2-1
6198C–ATARM–15-Dec-06
Setting Up the AT91SAM9261-EK Evaluation Board
2.3
Layout
Figure 2-1. AT91SAM9261-EK Layout - Top View
2-2
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
Setting Up the AT91SAM9261-EK Evaluation Board
Figure 2-2. AT91SAM9261-EK Layout - Bottom View
AT91SAM9261-EK Evaluation Board User Guide
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6198C–ATARM–15-Dec-06
Setting Up the AT91SAM9261-EK Evaluation Board
2.4
Powering Up the
Board
AT91SAM9261-EK requires 5V DC (±5%). DC power is supplied to the board via the 2.1
mm by 5.5 mm socket (J1). The coaxial power plug center pin is positive polarity .
2.5
Backup Power
Supply
The user has the possibility to add a battery (3V Lithium Battery CR1225 or equivalent)
in order to permanently power the backup part of the device. In this case, J9 configuration must to be set in position 1, 2.
Refer to Table 4-1, “Configuration Jumpers and Straps”.
2.6
Getting Started
2-4
6198C–ATARM–15-Dec-06
The AT91SAM9261-EK evaluation board is delivered with one CD-ROM allowing the
user to begin evaluating the AT91 ARM Thumb 32-bit microcontroller quickly. Please
refer to the AT91 web site, www.atmel.com/products/AT91/, for the most up-to-date information on getting started with the AT91SAM9261-EK.
AT91SAM9261-EK Evaluation Board User Guide
Setting Up the AT91SAM9261-EK Evaluation Board
2.7
AT91SAM9261EK Block
Diagram
Figure 2-3. Block Diagram
AT91SAM9261-EK Evaluation Board User Guide
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6198C–ATARM–15-Dec-06
Setting Up the AT91SAM9261-EK Evaluation Board
2-6
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
Section 3
Board Description
3.1
AT91SAM9261
Microcontroller
! Incorporates the ARM926EJ-S™ ARM Thumb Processor
– DSP Instruction Extensions
– ARM Jazelle® Technology for Java® Acceleration
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
– Mid-level implementation Embedded Trace Macrocell™
! Additional Embedded Memories
– 32K Bytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
– 160K Bytes of Internal SRAM, Single-cycle Access at Maximum Processor or
Bus Speed
! External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash and CompactFlash®
! LCD Controller
– Supports Passive or Active Displays
– Up to 16-bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x
2048
! USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
Dual On-chip Transceivers
Integrated FIFOs and Dedicated DMA Channels
– USB 2.0 Full Speed (12 Mbits per second) Device Port
On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
! Bus Matrix
– Handles Five Masters and Five Slaves
– Boot Mode Select Option
AT91SAM9261-EK Evaluation Board User Guide
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6198C–ATARM–15-Dec-06
Board Description
– Remap Command
! Fully Featured System Controller (SYSC) for Efficient System Management, including
– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers
for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Three 32-bit PIO Controllers
! Reset Controller (RSTC)
– Based on Power-on Reset Cells, Reset Source Identification and Reset
Output Control
! Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
! Clock Generator (CKGR)
– 32.768 kHz Low-power Oscillator on Battery Backup Power Supply, Providing
a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator and two PLLs
! Power Management Controller (PMC)
– Very Slow Clock Operating
Optimization Capabilities
Mode,
Software
Programmable
Power
– Four Programmable External Clock Signals
! Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious
Interrupt Protected
! Debug Unit (DBGU)
– 2-wire USART and Support for
Programmable ICE Access Prevention
Debug
Communication
Channel,
! Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
! Watchdog Timer (WDT)
– Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running
at Slow Clock
! Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock
! Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous
Output
! Nineteen Peripheral DMA (PDC) Channels
3-2
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
Board Description
! Multimedia Card Interface (MCI)
– Compliant with Multimedia Cards and SDCards
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC,
MMC and SDCard Compliant
! Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and
Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
! Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1
Handshaking, RS485 Support
Smart
Card,
Hardware
and
Software
! Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
! One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
! Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel EEPROMs Supported
! IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
! Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC and for VDDPLL
– 2.7V to 3.6V for VDDIOP (Peripheral I/Os)
– 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os)
! Available in a 217-ball LFBGA RoHS-compliant Package
AT91SAM9261-EK Evaluation Board User Guide
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6198C–ATARM–15-Dec-06
Board Description
AT91SAM9261
Block Diagram
Figure 3-1. Block Diagram
ARM926EJ-S Core
ICE
Instruction Cache
16K bytes
TCM
Interface
System Controller
I
PIO
AIC
ITCM
DBGU
PLLA
PLLRCB
PLLB
XIN
XOUT
OSC
OSC
POR
VDDCORE
POR
EBI
CompactFlash
NAND Flash
SDRAM
Controller
PIT
Peripheral
Bridge
RTT
Static
Memory
Controller
Peripheral
DMA
Controller
SHDWC
VDDBU
GNDBU
DTCM
5-layer
Matrix
GPBREG
SHDN
WKUP
D
Fast ROM
32K bytes
PMC
WDT
XIN32
XOUT32
I
Fast SRAM
160K bytes
PDC
PLLRCA
D
DMA
FIFO
RSTC
USB Host
NRST
APB
PIOA
PIOB
TCLK
TPS0-TPS2
TPK0-TPK15
BIU
PIO
TST
FIQ
IRQ0-IRQ2
DRXD
DTXD
PCK0-PCK3
ETM
Data Cache
16K bytes
MMU
PIO
TSYNC
JTAG
Boundary Scan
FIFO
PIOC
USB Device
Transceiver
JTAGSEL
TDI
TDO
TMS
TCK
NTRST
RTCK
BMS
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15/A18-A21
A22/REG
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NCS2
NCS3/NANDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
SDCKE
RAS-CAS
SDWE
SDA10
NWAIT
A23-A24
A25/CFRNW
NCS4/CFCS0
NCS5/CFCS1
CFCE1
CFCE2
NCS6/NANDOE
NCS7/NANDWE
D16-D31
HDMA
HDPA
HDMB
HDPB
Transceiver
3.2
DDM
DDP
DMA
MCI
LUT
LCD Controller
PDC
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
RXD1
TXD1
SCK1
RTS1
CTS1
USART1
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI1_NPCS10
SPI1_NPCS1
SPI1_NPCS12
SPI1_NPCS3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
3-4
6198C–ATARM–15-Dec-06
PIO
PIO
PDC
SSC0
PDC
TF0
TK0
TD0
RD0
RK0
RF0
SSC1
PDC
TF1
TK1
TD1
RD1
RK1
RF1
PIO
MCCK
MCCDA
MCDA0-MCDA3
RXD2
TXD2
SCK2
RTS2
CTS2
LCDD0-LCDD23
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDCC
FIFO
PDC
USART2
SSC2
PDC
PDC
Timer Counter
SPI0
PDC
TC0
TC1
TC2
TF2
TK2
TD2
RD2
RK2
RF2
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
SPI1
TWI
PDC
TWD
TWCK
AT91SAM9261-EK Evaluation Board User Guide
Board Description
3.3
Memory
! 32 Kbytes of Internal ROM
! 160 Kbytes of Internal High-speed SRAM
! Atmel serial DataFlash
! 64 Mbytes of SDRAM memory
! 256 Mbytes of NAND Flash memory
3.4
Clock Circuitry
! 18.432 MHz standard crystal for the embedded oscillator
! 32.768 kHz standard crystal for the slow clock oscillator
3.5
Reset Circuitry
! Internal reset controller with a bi-directional reset pin
! External reset push button
3.6
3.7
Shutdown
Controller
! Programmable shutdown and Wake-Up
Power Supply
Circuitry
! For dynamic power consumption, the AT91SAM9261 consumes a maximum of 50 mA
on VDDCORE at maximum speed in typical conditions (1.2V, 25°C), processor
running full-performance algorithm
! Wake-up push button
! On-board 1.2V high efficiency step-down charge pump regulator with shutdown
control
! On-board 3.3V linear regulator with shutdown control
3.8
Remote
Communication
! One Serial interface (DBGU COM Port) via RS-232 DB9 male socket
! USB V2.0 Full-speed Compliant, 12 Mbits per second (UDP)
! Two USB Host port V2.0 Full-speed Compliant, 12 Mbits per second (UHP)
! One Ethernet 100-base TX with three status LEDs
3.9
3.10
Audio Stereo
Interface
! One Atmel stereo audio DAC AT73C213
User Interface
! Four user input pushbuttons
! One 32 Ohm/20 mW Stereo Headset output (J20) with Master Volume and Mute
Controls
! Two user green LEDs
! One yellow power LED (can be also software controlled)
AT91SAM9261-EK Evaluation Board User Guide
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Board Description
! One ¼ VGA display LCD with Touchscreen and white LED backlight
3.11
Debug Interface
! 20-pin JTAG/ICE interface connector
! DBGU COM Port
3.12
Expansion Slot
! One DataFlash, SD/MMC card slot
! All I/Os of the AT91SAM9261 are routed to peripheral extension footprint connectors
(J16 and J17). This allows the developer to check the integrity of the components and
to extend the features of the board by adding external hardware components or
boards.
3-6
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
Board Description
3.13
PIO Usage
Table 3-1. PIO Controller A
I/O Line
Peripheral A
Peripheral B
Comments
PA0
SPI0_MISO
MCDA0
SD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DAC
SPI0_MISO or
MCI0_DA0
PA1
SPI0_MOSI
MCCDA
SD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DAC
SPI0_MOSI or
MCI0_CDA
PA2
SPI0_SPCK
MCCK
SD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DAC
SPI0_SPCK or
MCCK
PA3
SPI0_NPCS0
DATAFLASH DEVICE or DATAFLASH SOCKET (J9)
SPI0_NPCS0
PA4
SPI0_NPCS1
MCDA1
SD/MMC/DATAFLASH SOCKET (J9)
MCDA1
PA5
SPI0_NPCS2
MCDA2
SD/MMC/DATAFLASH SOCKET (J9)
MCDA2
PA6
SPI0_NPCS3
MCDA3
SD/MMC/DATAFLASH SOCKET (J9)
SPI0_NPCS3 or
MCDA3
PA7
TWD
PCK0
PA8
TWCK
PCK1
PA9
DRXD
PCK2
SERIAL DEBUG PORT (J15)
DRXD
PA10
DTXD
PCK3
SERIAL DEBUG PORT (J15)
DTXD
PA11
TSYNC
SCK1
TOUCH SCREEN CONTROLLER (MN16) BUSY
PA11
PA12
TCLK
RTS1
TFT PANEL CONTROL (J23) POWER CONTROL IN
PA12
PA13
TPS0
CTS1
GREEN USER'S LED 1 (DS8)
PA13
PA14
TPS1
SCK2
GREEN USER'S LED 2 (DS7)
PA14
PA15
TPS2
RTS2
PA16
TPK0
CTS2
PA17
TPK1
TF1
I2S AUDIO DAC AT73C213 (MN15) LRFS
TF1
PA18
TPK2
TK1
I2S AUDIO DAC AT73C213 (MN15) BCLK
TK1
PA19
TPK3
TD1
I2S AUDIO DAC AT73C213 (MN15) SDIN
TD1
PA20
TPK4
RD1
PA21
TPK5
RK1
PA22
TPK6
RF1
PA23
TPK7
RTS0
YELLOW POWER LED CONTROL (DS1)
PA23
PA24
TPK8
SPI1_NPCS1
USER'S PUSH BUTTON INPUT (BP6)
PA24
PA25
TPK9
SPI1_NPCS2
USER'S PUSH BUTTON INPUT (BP5)
PA25
PA26
TPK10
SPI1_NPCS3
USER'S PUSH BUTTON INPUT (BP4)
PA26
PA27
TPK11
SPI0_NPCS1
USER'S PUSH BUTTON INPUT (BP3)
PA27
PA28
TPK12
SPI0_NPCS2
TOUCH SCREEN CONTROLLER (MN16)
SPI0_NPCS2
PA29
TPK13
SPI0_NPCS3
I2S AUDIO DAC AT73C213 (MN15)
SPI0_NPCS3
PA30
TPK14
A23
PA31
TPK15
A24
AT91SAM9261-EK Evaluation Board User Guide
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Board Description
Table 3-2. PIO Controller B
I/O Line
Peripheral A
Peripheral B
PB0
LCDVSYNC
PB1
LCDHSYNC
PB2
LCDDOTCK
PB3
LCDDEN
PB4
LCDCC
LCDD2
PB5
LCDD0
LCDD3
PCK0
Comments
TFT PANEL CONTROL (J23)
LCDHSYNC
TFT PANEL CONTROL (J23)
LCDDOTCK
TFT PANEL CONTROL (J23)
LCDDEN
TFT PANEL CONTROL (J23) BACKLIGHT
LCDCC
PB6
LCDD1
LCDD4
PB7
LCDD2
LCDD5
TFT PANEL CONTROL (J23)
LCDD2
RED
PB8
LCDD3
LCDD6
TFT PANEL CONTROL (J23)
LCDD3
RED
PB9
LCDD4
LCDD7
TFT PANEL CONTROL (J23)
LCDD4
RED
PB10
LCDD5
LCDD10
TFT PANEL CONTROL (J23)
LCDD5
RED
PB11
LCDD6
LCDD11
TFT PANEL CONTROL (J23)
LCDD6
RED
PB12
LCDD7
LCDD12
TFT PANEL CONTROL (J23)
LCDD7
RED
PB13
LCDD8
LCDD13
PB14
LCDD9
LCDD14
PB15
LCDD10
LCDD15
TFT PANEL CONTROL (J23)
LCDD10
GREEN
PB16
LCDD11
LCDD19
TFT PANEL CONTROL (J23)
LCDD11
GREEN
PB17
LCDD12
LCDD20
TFT PANEL CONTROL (J23)
LCDD12
GREEN
PB18
LCDD13
LCDD21
TFT PANEL CONTROL (J23)
LCDD13
GREEN
PB19
LCDD14
LCDD22
TFT PANEL CONTROL (J23)
LCDD14
GREEN
PB20
LCDD15
LCDD23
TFT PANEL CONTROL (J23)
LCDD15
GREEN
PB21
TF0
LCDD16
PB22
TK0
LCDD17
PB23
TD0
LCDD18
TFT PANEL CONTROL (J23)
LCDD18
BLUE
PB24
RD0
LCDD19
TFT PANEL CONTROL (J23)
LCDD19
BLUE
PB25
RK0
LCDD20
TFT PANEL CONTROL (J23)
LCDD20
BLUE
PB26
RF0
LCDD21
TFT PANEL CONTROL (J23)
LCDD21
BLUE
PB27
SPI1_NPCS1
LCDD22
TFT PANEL CONTROL (J23)
LCDD22
BLUE
PB28
SPI1_NPCS0
LCDD23
TFT PANEL CONTROL (J23)
LCDD23
BLUE
PB29
SPI1_SPCK
IRQ2
USB DEVICE INTERFACE (J19) USB_CNX
PB29
I2S AUDIO DAC AT73C213 (MN15) MCLK
PCK2
PB30
SPI1_MISO
IRQ1
PB31
SPI1_MOSI
PCK2
3-8
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AT91SAM9261-EK Evaluation Board User Guide
Board Description
Table 3-3. PIO Controller C
I/O Line
Peripheral A
Peripheral B
Comments
PC0
NANDOE
NCS6
NAND FLASH DEVICE (MN6x)
NANDOE
PC1
NANDWE
NCS7
NAND FLASH DEVICE (MN6x)
NANDWE
PC2
NWAIT
IRQ0
TOUCH SCREEN CONTROLLER (MN16) PENIRQ
IRQ0
PC3
A25/CFRNW
PC4
NCS4/CFCS0
PC5
NCS5/CFCS1
PC6
CFCE1
PC7
CFCE2
PC8
TXD0
PCK2
PC9
RXD0
PCK3
PC10
RTS0
SCK0
ETHERNET CONTROLLER (MN8) RST
PC10
ETHERNET CONTROLLER (MN8) IRQ
PC11
PC11
CTS0
FIQ
PC12
TXD1
NCS6
PC13
RXD1
NCS7
PC14
TXD2
SPI1_NPCS2
NAND FLASH DEVICE (MN6x) CHIP ENABLE (CE)
PC14
PC15
RXD2
SPI1_NPCS3
NAND FLASH DEVICE (MN6x) READY/BUSY (R/B)
PC15
PC16
D16
TCLK0
EBI DATA BUS D16
D16
PC17
D17
TCLK1
EBI DATA BUS D17
D17
PC18
D18
TCLK2
EBI DATA BUS D18
D18
PC19
D19
TIOA0
EBI DATA BUS D19
D19
PC20
D20
TIOB0
EBI DATA BUS D20
D20
PC21
D21
TIOA1
EBI DATA BUS D21
D21
PC22
D22
TIOB1
EBI DATA BUS D22
D22
PC23
D23
TIOA2
EBI DATA BUS D23
D23
PC24
D24
TIOB2
EBI DATA BUS D24
D24
PC25
D25
TF2
EBI DATA BUS D25
D25
PC26
D26
TK2
EBI DATA BUS D26
D26
PC27
D27
TD2
EBI DATA BUS D27
D27
PC28
D28
RD2
EBI DATA BUS D28
D28
PC29
D29
RK2
EBI DATA BUS D29
D29
PC30
D30
RF2
EBI DATA BUS D30
D30
PC31
D31
PCK1
EBI DATA BUS D31
D31
AT91SAM9261-EK Evaluation Board User Guide
3-9
6198C–ATARM–15-Dec-06
Board Description
3-10
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
Section 4
Configuration Straps
4.1
Configuration
Straps
Table 4-1 gives details on configuration straps on the AT91SAM9261-EK evaluation
board and their default settings.
Table 4-1. Configuration Jumpers and Straps
Designation
Default
Setting
J2
Closed
3.3V Jumper (1)
This jumper footprint is provided for 3.3V power consumption
measurement use. By default, it is closed. To use this feature,
the user has to open the strap by cutting it before soldering a
jumper.
J3
Closed
Forces power on. To use the software shutdown control, J3
must be opened.
J4
Opened
Enables Boot on the internal ROM
Closed
Enables Boot on the NCS0
J8
Closed
VDDPLL Jumper (1)
J9
2-3
J12
Closed
J21
1-2
S2
Opened
Disables the ICE NTRST input
S3
Closed
Enables the ICE RTCK return. S6 must be opened
S4
Closed
Enables the ICE NRST input
S5
Opened
Selects ICE mode or JTAG mode (See Section 6, Errata )
S6
Opened
Disables TCK <-> RTCK local loop. If S6 is closed, S3 must be
opened.
AT91SAM9261-EK Evaluation Board User Guide
Feature
VDDBU Jumper select (1)
1-2 : Lithium 3V Battery
2-3 : 1.2V from VDDCORE
VDDCORE Jumper (1)
NPCS0 select
1-2: DataFlash device (MN7)
2-3: DataFlash card interface (J22)
Warning: In this case NPCS03 must be configured as
input.
4-1
6198C–ATARM–15-Dec-06
Configuration Straps
Table 4-1. Configuration Jumpers and Straps
Designation
6198C–ATARM–15-Dec-06
Closed
Feature
Enables the use of 18.432 MHz crystal. If external clock used,
S7-S8 must be opened and S9 closed.
S7-S8
S9
Opened
S10
Closed
Enables the use of SDRAM (NCS1_SDCS)
S12
Opened
Disables Serial DataFlash write protect.
S13
Closed
Disables NAND FLASH write protect.
S14
Closed
Enables the use of interrupt ETHERNET MAC (PC11_FIQ).
S15
Closed
Enables the use of ETHERNET MAC (NCS2).
S16
Opened
Disables the use of NWAIT ETHERNET MAC signal
(PC2_NWAIT)
S19
Closed
Enables the use of the User LED DS7 (PA14)
S20
Closed
Enables the use of the User LED DS8 (PA13)
S21
Closed
Enables the use of the DBGU RXD signal (PA9)
S22
Closed
Enables the use of the USB CNX detection (PB29)
S23
Closed
Enables the use of AUDIO DAC INTERFACE (NPCS03)
S24
Closed
Enables the use of TOUCH SCEEN CONTROLLER (NPCS02)
S25
Closed
Enables the use of TOUCH SCEEN CONTROLLER BUSY
signal (PA11)
S26
Closed
Enables the use of TOUCH SCEEN CONTROLLER PENIRQ
(PC2_IRQ0)
TP1
N.A
3.3V Test point.
TP2
N.A
GND Test point.
TP3
N.A
1.2V Test point.
TP4
N.A
GND Test point.
TP63
N.A
0 to 3.3V analog user's input
TP64
N.A
0 to 3.3V analog user's input
TP65
N.A
AGND of TP63
TP66
N.A
AGND of TP64
Note:
4-2
Default
Setting
1. These jumpers are provided for measuring power consumption. By default, they are
closed. To use this feature, the user has to open the strap and insert an ammeter.
AT91SAM9261-EK Evaluation Board User Guide
Section 5
Schematics
5.1
Schematics
This section contains the following schematics:
! Power Supply and Audio
! AT91SAM9261
! SDRAM and NAND Flash
! Ethernet
! LCD and User Interface
! Serial and I/O Expansion
AT91SAM9261-EK Evaluation Board User Guide
5-1
6198C–ATARM–15-Dec-06
8
7
6
5
4
3
2
1
D
D
3V3
AUDIO DAC INTERFACE
10 SQUARE CM COPPER AREA FOR HEAT SINKING
WITH NO SOLDER MASK
REGULATED
5V ONLY
J1
5V
C2
10µF
10V
2
R2
100K
1
2
+
3
VIN
CR1
5V
J2
VOUT
GND
3
1
3V3
POWER LED
3V3
GND
SD
C1
330µF
R1
120R
LT1963AEQ-3.3
6
MN1
4
R67
100K
TP1
3.3V
DS1
YELLOW
FB
MN15
PA[0..31]
C3
10µF
5
C4
10µF
3
Q1
IRLML2402
TP2
GND
PA23
1
M5V
2
C5
1µF
C6
1µF
C
Q2
6
Si1563EDH
4
8
5V
C1M
5
J3
6
3
4
1
11
10
HPN
LPHN
16
PAINP
30
MONOP
29
MONON
C1P C2M
VIN
C7
R3
22µF 100K
C2P
VOUT
2
6
7
TP3
1.2V
J20
TPS60500
3
C10
4.7µF
R5
10K
R6
10K
FB
1
EN
GND
9
SHDN
PG
3.5 PHONEJACK STEREO
3
1
4
2
10
2
R4
200K
C112
C113
TP4
GND
100µF
6V3
+
MN2
11.1
11.1
Z7
Z8
11.1
11.1
SMODE
RSTB
22
21
VDIG
24
3V3
AVDD
2
VCC_DAC
AVDDHS
5
VCM
9
VREF
1
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS3
PA0
PA1
PA2
PA29
S23
NRST
C
31
AUXP
32
AUXN
4
HSR
3
HSL
MCLK
SDIN
LRFS
BCLK
C107 10µF
C110
100NF
C111 10µF
20
17
19
18
R68
47R
C108 C109
100NF 100NF
GND_DAC
PCK2
PB31
PA19
TD1
PA17
TF1
PA18
TK1
PB[0..31]
100µF
6V3
INGND
ADHESIVE FEET
Z4
25
26
27
28
LINEL
8
Z3
DOUT
DIN
CLK
CS
LINER
+
C9
15PF
PAINN
VBAT
CBP
HPP
1V2
C8
10PF
FORCE
POWER
ON
15
12
14
13
7
5
PA[0..31]
AT73C213
GNDB
GNDD
33
PA[0..31]
23
GND_DAC
VCC_DAC
L4
4.7µH
3V3
B
B
C114
10µF
10V
R69 0R
GND_DAC
A
A
D
C
B
A INIT EDIT
REV
AT91SAM9261-EK
MODIF.
SCALE
JPG
JPG
JPG
JPG
01/18/06
14/09/05
04/20/05
02/23/05
XXX
DES.
DATE
VER.
DATE
REV.
SHEET
D
1
6
1/1
POWER SUPPLY & AUDIO
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
XX/XX/05
8
7
6
5
4
3
2
1
PC[0..15]
ETM
TRACE PORT
DDP
DDM
A12
B12
DDP
DDM
HDPA
HDMA
C12
B14
HDPA
HDMA
HDPB
HDMB
A13
A14
HDPB
HDMB
E17
C17
D17
U17
F16
B10
TDI
TMS
TCK
RTCK
TDO
JTAGSEL
F17
NTRST
J5
C
NOT POPULATED
RR1
100K
ICE INTERFACE
4
3
2
1
S2
S3
NRST
S6
C12
4.7NF
R11
C14
4.7NF
R12
C15
PLLRCA
S7
U12
XOUT
S8
S9
4
R15
1K
1
3
C126
100NF
OUT
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
RAS
CAS
F2
J4
RAS
CAS
SDWE
SDA10
SDCKE
SDCK
G3
E4
F1
H4
SDWE
SDA10
SDCKE
SDCK
NCS0
SDCS/NCS1
NCS2
NANDCS/NCS3
CFOE/NRD
F4
D2
D1
G4
E3
NCS0
SDCS_NCS1
NCS2
SMCS_NCS3
CFOE_NOE_NRD
CFWE/NWE/NWR0
CFIOR/NBS1/NWR1
CFIOW/NBS3/NWR3
E2
E1
F3
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
A10
XOUT32
A11
XIN32
F15
J9
B
NRST
R13
1K
VDDIOP
VDDIOP
VDDIOP
VDDIOP
TST
C10
NC
NC
NC
A9
C14
D10
VDDIOP
U6
T5
P15
P11
VDDIOP
VDDIOP
J14
D11
C15
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
N4
L4
H3
D4
C8
C5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C3
R16
NOT POPULATED
A16
C7
C11
D3
H8
H9
H10
J3
J8
J9
J10
K8
K9
K10
R3
R16
U4
U7
1V2
3
2
1
C
3V3
VDDCORE
MN10
R1100D121C
GND
3
2
2
CR2
MMBD1704A
J10
VDD
3V3
D8
B8
A8
A7
B7
D7
A6
B6
C6
A5
D6
B5
A4
B4
A3
B3
A2
C4
B2
A1
B1
C2
C1
R14
1K
BP1
RESET
3V3
C43
10µF
10V
A
1
+
NBS0/A0
NWR2/NBS2/A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BA0/A16
BA1/A17
A18
A19
A20
A21
A22
NRST
R10 VDDPLL
C21
100NF
P9 GNDPLL
VDDOSC + VDDPLL
CURRENT MEASURE
CR1225
A
XIN
VDDCORE
1
J8
3V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
32.768 kHz
Y2
C20
10PF
3V3
U11
G1
G2
H1
H2
J1
J2
K1
K4
K2
L1
K3
L2
L3
M1
N1
M2
T10 VDDOSC
C18
100NF
T11 GNDOSC
C19
10PF
SMB MALE
U10
470pF
1
C17
10PF
1
3
5
2
4
1,5K
1%
Y1
18.4320MHz
NOT POPULATED
J7
PLLRCB
2
C16
10PF
U9
P12
B
1,96K
1%
470pF
C13
Z14
S5
3V3
VDDCORE
ICE_NTRST
TDI
TMS
TCK
ICE_RTCK
TDO
S4
M4
1
3
5
7
9
11
13
15 ICE_NRST
17
19
VDDCORE
2
4
6
8
10
12
14
16
18
20
D
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
AT91SAM9261
K14
J6
D5
5
6
7
8
3V3
GNDBU
G1
G2
G3
G4
G5
C11
100NF
R10
10K
VDDBU
R9
0R
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
TRACEPKT[8]
TRACEPKT[9]
TRACEPKT[10]
TRACEPKT[11]
TRACEPKT[12]
TRACEPKT[13]
TRACEPKT[14]
TRACEPKT[15]
ICE_NTRST
TDI
TMS
TCK
ICE_RTCK
TDO
ICE_NRST
DBGRQ
GND
B9
TRACECLK
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
SHDN
PA12
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
PA0/SPI0_MISO/MCDA0
PA1/SPI0_MOSI/MCCDA
PA2/SPI0_SPCK/MCCK
PA3/SPI0_NPCS0
PA4/SPI0_NPCS1/MCDA1
PA5/SPI0_NPCS2/MCDA2
PA6/SPI0_NPCS3/MCDA3
PA7/TWD/PCK0
PA8/TWCK/PCK1
PA9/DRXD/PCK2
PA10/DTXD/PCK3
PA11/TSYNK/SCK1
PA12/TCLK/RTS1
PA13/TPS0/CTS1
PA14/TPS1/SCK2
PA15/TPS2/RTS2
PA16/TPK0/CTS2
PA17/TPK1/TF1
PA18/TPK2/TK1
PA19/TPK3/TD1
PA20/TPK4/RD1
PA21/TPK5/RK1
PA22/TPK6/RF1
PA23/TPK7/RTS0
PA24/TPK8/SPI1_NPCS1
PA25/TPK9/SPI1_NPCS2
PA26/TPK10/SPI1_NPCS3
PA27/TPK11/SPI0_NPCS1
PA28/TPK12/SPI0_NPCS2
PA29/TPK13/SPI0_NPCS3
PA30/TPK14/A23
PA31/TPK15/A24
WKUP
3V3
R8
10K
PIPESTAT[0]
PIPESTAT[1]
PIPESTAT[2]
TRACESYNC
TRACEPKT[0]
TRACEPKT[1]
TRACEPKT[2]
TRACEPKT[3]
TRACEPKT[4]
TRACEPKT[5]
TRACEPKT[6]
TRACEPKT[7]
VSUPPLY
EXTTRIG
R11
T12
U13
P10
T13
U14
T14
R12
T15
U16
R13
T16
U15
R14
T17
P13
P14
R15
R17
P16
P17
N15
N14
N16
N17
M14
M15
L15
M16
M17
L14
L16
D9
PA13
PA14
PA15
PA11
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
B11
D
U2
P6
T4
U3
R6
T6
U5
P7
R7
T7
T8
P8
R8
U8
R9
T9
P1
N2
M3
R1
T1
R2
P3
T2
P4
U1
T3
R4
P5
R5
P2
N3
MN3
PA[0..31]
A[0..22]
NANDOE/NCS6/PC0
NANDWE/NCS7/PC1
NWAIT/IRQ0/PC2
A25/CFRNW/PC3
NCS4/CFCS0/PC4
NCS5/CFCS1/PC5
CFCE1/PC6
CFCE2/PC7
TXD0/PCK2/PC8
RXD0/PCK3/PC9
RTS0/SCK0/PC10
CTS0/FIQ/PC11
TXD1/NCS6/PC12
RXD1/NCS7/PC13
TXD2/SPI1_NPCS2/PC14
RXD2/SPI1_NPCS3/PC15
D16/TCLK0/PC16
D17/TCLK1/PC17
D18/TCLK2/PC18
D19/TIOA0/PC19
D20/TIOB0/PC20
D21/TIOA1/PC21
D22/TIOB1/PC22
D23/TIOA2/PC23
D24/TIOB2/PC24
D25/TF2/PC25
D26/TK2/PC26
D27/TD2/PC27
D28/RD2/PC28
D29/RK2/PC29
D30/RF2/PC30
D31/PCK1/PC31
R7 1K
J4
LCDVSYNC/PB0
LCDHSYNK/PB1
LCDDOTCK/PCK0/PB2
BMS/LCDDEN/PB3
LCDCC/LCDD2/PB4
LCDD0/LCDD3/PB5
LCDD1/LCDD4/PB6
LCDD2/LCDD5/PB7
LCDD3/LCDD6/PB8
LCDD4/LCDD7/PB9
LCDD5/LCDD10/PB10
LCDD6/LCDD11/PB11
LCDD7/LCDD12/PB12
LCDD8/LCDD13/PB13
LCDD9/LCDD14/PB14
LCDD10/LCDD15/PB15
LCDD11/LCDD19/PB16
LCDD12/LCDD20/PB17
LCDD13/LCDD21/PB18
LCDD14/LCDD22/PB19
LCDD15/LCDD23/PB20
TF0/LCDD16/PB21
TK0/LCDD17/PB22
TD0/LCDD18/PB23
RD0/LCDD19/PB24
RK0/LCDD20/PB25
RF0/LCDD21/PB26
SPI1_NPCS1/LCDD22/PB27
SPI1_NPCS0/LCDD23/PB28
SPI1_SPCK/IRQ2/PB29
SPI1_MISO/IRQ1/PB30
SPI1_MOSI/PCK2/PB31
BMS
C9
PB3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
D[0..31]
L17
K16
K17
K15
J17
H17
J16
H16
G17
J15
H14
G16
G15
H15
G14
E16
F14
D16
E15
B17
D15
C16
E14
D14
A17
B16
B15
A15
D13
D12
C13
B13
PB[0..31]
BOOT MODE SELECT
R17
100K
WAKE UP
C28
10µF
10V
C22
100NF
BP2
VDDBU
SHDN
WKUP
C24
C26
100NF 100NF
C23
C25
C27
J12
10µF
100NF 100NF
1V2
10V
VDDCORE CURRENT MEASURE
C29
C31
C33
C35
100NF 100NF 100NF 100NF
C30
C32
C34
100NF 100NF 100NF
C36
C38
C40
C42
100NF 100NF 100NF 100NF
C37
C39
C41
100NF 100NF 100NF
D
C
B
A INIT EDIT
REV
AT91SAM9261-EK
MODIF.
SCALE
JPG
JPG
JPG
JPG
01/18/06
14/09/05
04/20/05
02/23/05
XXX
DES.
DATE
VER.
DATE
REV.
SHEET
D
2
6
1/1
AT91SAM9261
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
XX/XX/05
8
7
6
5
4
3
2
1
EBI SDRAM INTERFACE
A[0..22]
D[0..31]
RAS
CAS
SDWE
SDA10
SDCKE
SDCK
D
D
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
MN4
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDCS_NCS1
SDA10
A13
A16
A17
BA0
BA1
23
24
25
26
29
30
31
32
33
34
22
35
20
21
A14
36
40
SDCKE
SDCK
37
38
C
NBS0
A0
15
CFIOR_NBS1_NWR1 39
3V3
CAS
RAS
SDWE
R18
100K
17
18
16
19
MN5
A0 MT48LC16M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDA10
A13
A16
A17
BA0
BA1
20
21
A14
3V3
1
14
27
3
9
43
49
23
24
25
26
29
30
31
32
33
34
22
35
36
40
SDCKE
37
SDCK
38
NBS2
A1
15
CFIOW_NBS3_NWR3 39
28
41
54
6
12
46
52
CAS
RAS
C50
C51
C52
C53
100NF 100NF
100NF 100NF
C44
C45
C46
100NF 100NF 100NF
17
18
SDWE
16
19
256 Mbits
S10
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
A0 MT48LC16M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
1
14
27
3
9
43
49
28
41
54
6
12
46
52
3V3
C
C54
C55
C56
C57
100NF 100NF
100NF 100NF
C47
C48
C49
100NF 100NF
100NF
256 Mbits
PA[0..31]
DUAL FOOTPRINT
D[0..31]
3V3
PC[0..15]
3V3
B
MN6A
R19
100K
A21
A22
PC0
PC1
PC14
16
17
8
18
9
PC15
7
WP
19
S13
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
34
35
CLE
ALE
RE
WE
CE
R/B
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
16-bit bus width
MN6B
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
26
28
30
32
40
42
44
46
27
29
31
33
41
43
45
47
N.C
PRE
N.C
39
38
36
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A21
A22
PC0
PC1
PC14
PC15
WP
3V3
VCC
VCC
37
12
VSS
VSS
VSS
48
25
13
C60
100NF
C59
100NF
16
17
8
18
9
R/B
19
WP
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
8-bit bus width
CLE
ALE
RE
WE
CE
7
MN7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
29
30
31
32
41
42
43
44
N.C
N.C
N.C
N.C
N.C
N.C
PRE
N.C
N.C
N.C
N.C
N.C
48
47
46
45
40
39
38
35
34
33
28
27
VCC
VCC
37
12
VSS
VSS
PA0
PA1
PA2
D0
D1
D2
D3
D4
D5
D6
D7
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
8
1
2
4
SO
SI
SCK
CS
3
RESET
VCC
6
GND
7
WP
5
C58
100NF
B
3V3
R20
100K
WRITE PROTECT
NORMALLY OPEN
S12
NRST
PA3
1
2
3
3V3
J21
SD CARD / MMC CARD
DATAFLASH CARD
INTERFACE
R72
10K
J22
3V3
PA4
PA0
MCDA1
SPI0_MISO MCDA0
PA2
SPI0_SPCK MCCK
PA1
PA6
PA5
SPI0_MOSI MCCDA
SPI0_NPCS3 MCDA3
MCDA2
8
7
6
5
4
3
2
1
9
3V3
36
13
FPS009
C115
100NF
NOT POPULATED
A
A
D
C
B
A INIT EDIT
REV MODIF.
AT91SAM9261-EK
SCALE
JPG
JPG
JPG
JPG
01/18/06
14/09/05
04/20/05
02/23/05
XXX
DES.
DATE
VER.
DATE
REV.
SHEET
D
3
6
1/1
SDRAM & NANDFLASH
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
XX/XX/05
8
7
6
5
4
3
2
1
3V3
D
3V3
R23
4,7K
DS2
GREEN
DS3
YELLOW FULL DUPLEX
DS4
GREEN SPEED 100
LINK&ACT
Note1: 8/16 bit DataBus
selection; Removed R27
when using 16-bit mode;
otherwise is 8-bit mode.
A[0..22]
C
NRST
D15
D14
D13
D12
D11
D10
D9
D8
3V3
A2
R28
4,7K
PC11 FIQ
1K
L1
742792093
TXD0
TX_CLK
TEST5
RX_CLK
RX_ER
RX_DV
COL
CRS
DGND
RXD3
RXD2
RXD1
RXD0
LINK_I
DVDD
AVDD
TXOTXO+
AGND
AGND
RXIRXI+
AVDD
AVDD
BGRES
DM9000
3V3
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
J13
16
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
DVDD
IO16
CMD
SA4
SA5
SA6
SA7
SA8
SA9
DGND
INT
R26
49R9
1%
15
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
R25
49R9
1%
J0026D21
TX+
1
1 TD+
C62
3V3
100NF
3 CT
VCCA
2 TD-
TX-
2
7 RD+
RX+
3
RX-
6
C
6 CT
8 RDC63
100NF
75
R29
49R9
1%
R30
49R9
1%
75
75
4
4
5
1nF
75
5
7
8
C64
100NF
R31
6,80K
1%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
3V3
R24
C61
100NF
IOR#
IOW#
AEN
IOWAIT
DVDD
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
RST
DGND
TEST1
TEST2
TEST3
TEST4
DVDD
X2_25M
X1_25M
DGND
SD
AGND
S14
1K
NC
NC
DVDD
DVDD
GPIO3
GPIO2
GPIO1
GPIO0
EECS/LED
EECK
EEDO
EEDI
DGND
LINKACT#
DUP#
SPEED#
CLK20MO
DGND
MDC
MDIO
DVDD
TX_EN
TXD3
TXD2
TXD1
NOT POPULATED
PC[0..15]
R22
D
VCCA
MN8
D[0..15]
1K
3V3
3V3
R27
4,7K
R21
R32
100K
B
B
Y3
1
CFOE_NOE_NRD
CFWE_NWE_NWR0
NCS2
S15
2
C66
22PF
D0
D1
D2
D3
D4
D5
D6
D7
PC10 RST
25MHz
C67
22PF
3V3
C76
10µF
10V
VCCA
L2
4.7µH
C77
100NF
3V3
C79
100NF
C78
10µF
10V
3V3
C68
100NF
3V3
C69
100NF
3V3
C70
100NF
3V3
C71
100NF
3V3
C72
100NF
VCCA
C73
100NF
VCCA
C74
100NF
C75
100NF
3V3
R70 0R
R71 0R
R34
4,7K
PC2
S16
NWAIT
NOT USED
A
A
D
C
B
A INIT EDIT
REV MODIF.
AT91SAM9261-EK
SCALE
JPG
JPG
JPG
JPG
01/18/06
14/09/05
04/20/05
02/23/05
XXX
DES.
DATE
VER.
DATE
REV.
SHEET
D
4
6
1/1
ETHERNET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
XX/XX/05
8
7
6
5
4
3
2
1
3V3
3V3
TOUCH SCREEN CONTROLLER
54132-4097
D
Z17 TX09D71VM1CCA
C
B3
B4
B5
LCDD21
LCDD22
LCDD23
PB26
PB27
PB28
G0
G1
G2
LCDD10
LCDD11
LCDD12
PB15
PB16
PB17
G3
G4
G5
LCDD13
LCDD14
LCDD15
PB18
PB19
PB20
R0
R1
R2
LCDD2
LCDD3
LCDD4
PB7
PB8
PB9
R3
R4
R5
LCDD5
LCDD6
LCDD7
PB10
PB11
PB12
DTMG LCDDEN
PB3
HSYNCLCDHSYNC
PB1
R75
10K
X_LEFT
Y_UP
X_RIGHT
Y_LOW
M5V
R73
R76
R77
R78
0R
0R
0R
0R
2
3
4
5
MN11
1
2
3
4
C87
4.7NF
RST
IN
N.C
GND
N.C
N.C
N.C
N.C
8
7
6
5
C116
10NF
NOT POPULATED
MC34064D
3
C117 C118
10NF 10NF
R80
100K
R81
100K
TP63
7
8
16
14
12
15
BUSY
PENIRQ
13
11
VREF
VCC
VCC
9
1
10
GND
6
IN3
IN4
ADS7843E
AGND
Q6
IRLML2402
TP65
S24
PA2
PA1
PA0
PA28
SPI0_SPCK
SPI0_MOSI
SPI0_MISO
SPI0_NPCS2
S25
S26
PA11
PC2
BUSY
IRQ0
R79 0R
TP66
PC[0..15]
D
3V3
L5
C120
10µF
10V
TP64
PA12 POWER CONTROL IN
1
2
DCLK
DIN
DOUT
CS
XP
YP
XM
YM
C119
10NF
PA12
R74 47R
MN16
X_RIGHT
Y_LOW
X_LEFT
Y_UP
VCTRL
Vctrl
PCI
PB23
B0
LCDD18
PB24
B1
LCDD19
PB25
B2
LCDD20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PA[0..31]
R84
100K
4.7µH
R82 0R
C122
100NF
C121 C123
100NF 100NF
TWO USER'S ANALOG INPUTS
Full-Scale Input Span 0 to VREF
R83 10K
PB4
LCDCC
VCTRL
C84
100NF
C
DCLK LCDDDOTCK PB2
3V3
PB[0..31]
J23
C124
100NF
C125
10V
10µF
PA[0..31]
B
B
PA27
BP3
PA14
PA26
BP4
PA13
PA25
BP5
PA24
BP6
3V3
GREEN
R50
S19
220R
DS7
GREEN
R51
S20
220R
DS8
A
A
USER INTERFACE
D
C
B
A INIT EDIT
REV MODIF.
AT91SAM9261-EK
SCALE
JPG
JPG
JPG
JPG
01/18/06
14/09/05
04/20/05
02/23/05
XXX
DES.
DATE
VER.
DATE
REV.
SHEET
D
5
6
1/1
LCD & USER'S INTERFACE
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
XX/XX/05
5
4
3
3 C14 C2+
C94
100NF
EXPANSION CONNECTORS
11
NOT POPULATED
C
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
A[0..22]
B
PB[0..31]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
J16
PC[0..15]
PB0
PB2
PB4
PB6
PB8
PB10
PB12
PB14
PB16
PB18
PB20
PB22
PB24
PB26
PB28
PB30
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PA16
PA18
PA20
PA22
PA24
PA26
PA28
PA30
PC0
PC2
PC4
PC6
PC8
PC10
PC12
PC14
D16
D18
D20
D22
D24
D26
D28
D30
D[0..31]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
NRST
VDDBU
3V3
5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
PB1
PB3
PB5
PB7
PB9
PB11
PB13
PB15
PB17
PB19
PB21
PB23
PB25
PB27
PB29
PB31
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PA17
PA19
PA21
PA23
PA25
PA27
PA29
PA31
A1
A4
A7
A11
A13
A15
A18
A0
A10
A17
A21
A22
SDCS_NCS1
CFIOR_NBS1_NWR1
CFOE_NOE_NRD
CFIOW_NBS3_NWR3
RAS
SDWE
CAS
D2
D3
D10
D8
D12
D11
D6
D9
PC1
PC3
PC5
PC7
PC9
PC11
PC13
PC15
D17
D19
D21
D23
D25
D27
D29
D31
3V3
3V3
5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
GND
15
DBGU_TXD 10
V+
2
V-
6
C92
100NF
C93
100NF
MALE RIGHT ANGLED
J15
C95
100NF
SERIAL DEBUG PORT
1
6
2
7
3
8
4
9
5
RXD
14
T
TXD
7
T
S21
J17
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
16
PA9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
DBGU_RXD 12
R
13
9
R
8
R53 0R
A2
A3
A6
A9
A12
A14
A16
A19
A5
A8
A20
D
ADM3202ARN
SDCKE
NCS2
CFWE_NWE_NWR0
SDA10
NCS0
5V
F1
500 mA
SDCK
CCUSBA-32002-30X
C
USB HOST INTERFACE
SMCS_NCS3
D1
D0
D5
D7
D4
D15
D13
D14
F2
500 mA
J18
HDMA
HDPA
R54
39R
R55
39R
R56
15K
A1
A2
A3
A4
C96
47pF
R57
15K
C97
47pF
B1
B2
B3
B4
A
B
1 2
3 4
C98
100NF
3V3
HDMB
HDPB
3V3
R58
39R
R59
39R
5V
R60
15K
S22
PB29
R61
15K
C99
100NF
C101
47pF
C100
47pF
R62 15K
USB_CNX
USER'S GRID AERA
B
R63
22K
WKUP
SHDN
NOT POPULATED
3V3
3V3
3V3
VCC
5V
Q5
IRLML6302
MN14
5V
PB30
1.27 PITCH
5
2
PA[0..31]
PA10
NOT POPULATED
VCC
5 C2-
R52 0R
D
1
3V3
MN13
1 C1+
C91
100NF
2
11
6
10
7
USB_DP_PUP
1
4
2
NRST
1
C102
100NF
3 GND
3
8
SN74LVC1G00DBV
3V3
5V
R64
1,5K
2.54 PITCH
J19
USB DEVICE INTERFACE
DDM
DDP
C105
15PF
R65
39R
R66
39R
C103
33PF
2
1
3
4
C106
15PF
5
C104
100NF
6
A
A
D
C
B
A INIT EDIT
REV
AT91SAM9261-EK
MODIF.
SCALE
JPG
JPG
JPG
JPG
01/18/06
14/09/05
04/20/05
02/23/05
XXX
DES.
DATE
VER.
DATE
REV.
SHEET
D
6
6
1/1
SERIAL & I/O EXPANSION
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
XX/XX/05
Schematics
5-2
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
Section 6
Errata
6.1
JTAGSEL S5
Footprint
Selector
For JTAG selection, the S5 footprint must never be soldered, else the chip can be
damaged.
By default, the JTAGSEL input pin integrates a pull-down resistor (ICE mode).
To select JTAG mode, the designer should connect the JTAGSEL input pin to VDDBU
power.
AT91SAM9261-EK Evaluation Board User Guide
6-1
6198C–ATARM–15-Dec-06
Errata
6-2
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
Section 7
Revision History
7.1
Revision History
Table 7-1.
Document
Comments
6198A
First issue.
6198B
Removed DataFlash card from list in Section 1.2 ”Deliverables”.
Removed references to 32-bit serial DataFlash, ref. AT45DB321C in Section 1.3 ”The
AT91SAM9261-EK Evaluation Board”, Figure 2-3 on page 5 “Block Diagram”, Section
3.3 ”Memory”, Table 4-1 “Configuration Jumpers and Straps” and in schematic 3/6
Change Request
Ref.
2733
“SDRAM and NANDFLASH”.
In Figure 2-3 on page 5 “Block Diagram” changed size of NANDFlash to 2 Gb.
6198C
Specified TRACE PORT as NOT POPULATED in Figure 2-3 on page 5 “Block Diagram”.
Changed all instances of DNP to NOT POPULATED in Schematics 2/6 “AT91SAM9261”, 4/6
“Ethernet” and 5/6 “LCD and User Interface”.
2736
New Figure 2-1 “AT91SAM9261-EK Layout - Top View” and new Figure 2-2
“AT91SAM9261-EK Layout - Bottom View”
3542
Updated Section 2.6 ”Getting Started”.
In Section 2.3 ”Layout”, updated Figure 2-3, “Block Diagram”.
Added Section 3.13 ”PIO Usage”.
In Section 4.1 ”Configuration Straps”, updated Table 4-1, S5, with reference to Errata
section.
Updated all schematics in Section 5.1 ”Schematics”.
Added Section 6, Errata.
AT91SAM9261-EK Evaluation Board User Guide
7-1
6198C–ATARM–15-Dec-06
Revision History
7-2
6198C–ATARM–15-Dec-06
AT91SAM9261-EK Evaluation Board User Guide
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6198C–ATARM–15-Dec-06