AT91SAM9G10-EK Evaluation Board
....................................................................................................................
User Guide
6479A–ATARM–26-May-09
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6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
AT91SAM9G10-EK Evaluation Board
User Guide
Section 1
Overview.....................................................................................................................1-1
1.1
Scope ................................................................................................................................. 1-1
1.2
Deliverables ....................................................................................................................... 1-1
1.3
The AT91SAM9G10-EK Evaluation Board ........................................................................ 1-1
Section 2
Setting Up the AT91SAM9G10-EK
Evaluation Board ........................................................................................................2-1
2.1
Electrostatic Warning ......................................................................................................... 2-1
2.2
Requirements..................................................................................................................... 2-1
2.3
Layout ................................................................................................................................ 2-2
2.4
Powering Up the Board ...................................................................................................... 2-4
2.5
Backup Power Supply ........................................................................................................ 2-4
2.6
Getting Started ................................................................................................................... 2-4
2.7
AT91SAM9G10-EK Block Diagram.................................................................................... 2-5
Section 3
Board Description .......................................................................................................3-1
3.1
AT91SAM9G10 Microcontroller ......................................................................................... 3-1
3.2
AT91SAM9G10 Block Diagram.......................................................................................... 3-4
3.3
Memory .............................................................................................................................. 3-5
3.4
Clock Circuitry .................................................................................................................... 3-5
3.5
Reset Circuitry.................................................................................................................... 3-5
3.6
Shutdown Controller........................................................................................................... 3-5
3.7
Power Supply Circuitry....................................................................................................... 3-5
3.8
Remote Communication..................................................................................................... 3-5
3.9
Audio Stereo Interface ....................................................................................................... 3-5
3.10 User Interface..................................................................................................................... 3-6
3.11 Debug Interface.................................................................................................................. 3-6
3.12 Expansion Slot ................................................................................................................... 3-6
3.13 PIO Usage ......................................................................................................................... 3-7
Section 4
Configuration Straps ...................................................................................................4-1
4.1
Configuration Straps .......................................................................................................... 4-1
Section 5
Schematics .................................................................................................................5-1
5.1
Schematics......................................................................................................................... 5-1
AT91SAM9G10-EK Evaluation Board User Guide
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6479A–ATARM–26-May-09
Section 6
Errata ..........................................................................................................................6-1
6.1
JTAGSEL S5 Footprint Selector ........................................................................................ 6-1
6.2
External Capacitor Values on XIN and XOUT.................................................................... 6-1
Section 7
Revision History..........................................................................................................7-1
7.1
Revision History ................................................................................................................. 7-1
2-2
6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
Section 1
Overview
1.1
Scope
The AT91SAM9G10-EK evaluation kit is an effective platform for evaluating chip performance and
developing code for applications based on the AT91SAM9G10.
This guide is a description of the hardware included in the AT91SAM9G10-EK evaluation kit. Software
files are available embedded into the board’s memory upon delivery.
1.2
Deliverables
The AT91SAM9G10-EK package contains the following items:
1.3
an AT91SAM9G10-EK board
one A/B-type USB cable
one serial RS232 cable
one RJ45 crossed Ethernet cable
universal input AC/DC power supply with US and EU plug adapter
The AT91SAM9G10-EK Evaluation Board
The board is equipped with an AT91SAM9G10 (217-ball LFBGA package) together with the following:
64 Mbytes of SDRAM memory
256 Mbytes of NAND Flash memory
one Atmel® serial DataFlash®
one USB device port interface
two USB host port interfaces
one DBGU serial communication port
JTAG/ICE debug interface
one Ethernet 100-base TX with three status LEDs
one Atmel AT73C213 Audio DAC
one 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight
one Power LED and two general-purpose LEDs
four user input pushbuttons
one wakeup input pushbutton
one reset pushbutton
one DataFlash SD/MMC card slot
AT91SAM9G10-EK Evaluation Board User Guide
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6479A–ATARM–26-May-09
two expansion footprint connectors (solder side)
one Lithium Coin Cell Battery Retainer for 12 mm cell size
dual pitch prototyping area
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6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
Section 2
Setting Up the AT91SAM9G10-EK
Evaluation Board
2.1
Electrostatic Warning
The AT91SAM9G10-EK evaluation board is shipped in a protective anti-static package. The board must
not be subjected to high electrostatic potentials. In risky ESD environments (e.g. offices with carpet) a
grounding strap or similar protective device should be worn when handling the board. Also, generally
avoid touching the component pins or any other metallic element of the board.
2.2
Requirements
In order to set up the AT91SAM9G10-EK evaluation board, the following items are required:
the AT91SAM9G10-EK evaluation board itself
AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm
AT91SAM9G10-EK Evaluation Board User Guide
2-1
6479A–ATARM–26-May-09
1
J2
GND
C4
J10
1
GND
C2
1
MN1
R6
C3
C9
Q2
k
GND
3.3V
3.3V
TP1
Q1
J3
1
POWER
LED
DS1
5V
C91 C94 C95
1
SERIAL
DEBUG
PORT
5V
GND
GND
3.3V
GND
GND
VDDBU
GND
WKUP
NRST
NC
NC
GND GND
30
31
28
29
26
27
24
25
23
22
21
20
19
18
16
17
15
14
13
12
11
10
8
9
7
6
4
5
2
3
0
1
GND
GND
30
31
29
28
26
27
25
24
22
23
21
20
18
19
17
16
14
15
13
12
10
11
9
8
6
7
5
4
2
3
J24 0
1
GND
GND
1
31
30
28
29
27
26
24
25
23
22
20
21
19
18
16
17
15
14
12
13
11
10
8
9
7
6
5
4
3
2
0
1
GND
GND
J21
1
MN7
DATAFLASH
S9
1
J9
C126
MN10
BP2
BP1
1.2V
VDDBU
BB
GND
SHDN
3.3V
5V
A4
B4
WAKE
UP
1
R54
A1
1.2V
J5
B1
J4
1
MN6B
R19
C59
1
STUDIEL
1
WWW.STUDIEL.FR
MN3
A1
TP3
USB DEVICE INTERFACE
C48
C52
C46
VDDCORE
MN4
C10
R62
MN2
R63
MN5
1
R4
R65
MN6A
NANDFLASH
C51
C45
C53
C56
R18
C49
C55
J8
C57
1
VDDOSC+VDDPLL
BOOT MODE
SELECT
RESET
Y2
ETM TRACE PORT 1
Y1
J18
C17
WARNING
5V ONLY
3.3V
TP2
C93
C92
5V
FORCE
POWERON
S7
R64
DS7
DS8
C68
R32
R28
C44
R27
C50
C60
1
FULL DS2 k
DUPLEX
DS3 k
SPEED
DS4
k
k
k
MN14
LINK & ACT
C47
C54
C7
Q5
J19
C8
R66
R3
USB HOST INTERFACE
R12
R2
R5
J12
R55
R9
CR1
3.3V
PORT C
PORT A
PORT B
C102
R23
C1
S8
C20
C11
R11
C19
J7
R68
BP3
C66
MN8
C110
C67
C111
MN15
J6
C70
EXT. CLOCK
C69
MN13
R20
C72
R34
C16
TP4
C73
R81
R80
R78
R77
R76
R73
Y3
RR1
1
JTAG/ICE
C87
Q6
C113
C112
C74
C75
1
R74
BP4
R84
R79
L5
R72
1
C124
C115
C84
R83
C125
J13
BP5
J20
AUDIO OUT
1
J23
ETHERNET
10/100
19
20
AT91SAM9261-EK
TP64 TP63
MN16
CONTROLLER
R26
R25
R29
R30
CONNECTOR
TOUCH SCREEN
C107
1
2
R31
MN11
TP65
J15
GND
C123
J1
TP66
R75
2-2
C122
C121
6479A–ATARM–26-May-09
R82
BP6
Figure 2-1.
C120
2.3
Layout
AT91SAM9G10-EK Layout - Top View
AT91SAM9G10-EK Evaluation Board User Guide
SD CARD/MMC CARD
DATAFLASH CARD
INTERFACE
L1
S26
S25
S24
S4
J22
C61
C63
C62
R69
S3
C76
C77
C114
L2
C116
C117
C118
C119
C109
C108
R71
C64
S6
S2
C78
L4
S23
C79
R50
S19
R51
S20
R70
S16
S15
S14
R24
R22
R21
C103
2
80
S22
J17
C6
C105
C5
1
79
S10
R57
C98
S13
C101
C34
C32
C33
C35
F1
R61
C97
F2
R60
C100
C96
C99
R8
C28
C41
C29
R58
R14
R10
R56
C26
C23
C27
C14
C39
R59
C12
C42
C24
C13
C21
R7
C31
C30
C15
C22
C25
C18
R13
C37
AT91SAM9G10-EK Evaluation Board User Guide
C43
CR2
C38
C40
R17
S12
2
120
C58
J16
R53
S21
1
119
R85
R15
Figure 2-2.
AT91SAM9G10-EK Layout - Bottom View
6479A–ATARM–26-May-09
2-3
R1
R52
R16
C36
C104
C106
C71
R67
S5
2.4
Powering Up the Board
AT91SAM9G10-EK requires 5V DC (±5%). DC power is supplied to the board via the 2.1 mm by 5.5 mm
socket (J1). The coaxial power plug center pin is positive polarity.
2.5
Backup Power Supply
The user has the possibility to add a battery (3V Lithium Battery CR1225 or equivalent) in order to permanently power the backup part of the device. In this case, J9 configuration must to be set in position 1,
2.
Refer to Table 4-1, “Configuration Jumpers and Straps”.
2.6
Getting Started
The AT91SAM9G10-EK evaluation board is delivered with an embedded demo and documentation files
allowing the user to begin evaluating the AT91 ARM Thumb 32-bit microcontroller quickly. Simply power
the board and connect it to the USB port of your PC to open it. Also, please refer to the AT91 web site,
www.atmel.com/products/AT91/, for the most up-to-date information on getting started with the
AT91SAM9G10-EK.
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6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
AT91SAM9G10-EK Block Diagram
Figure 2-3.
Block Diagram
DBGU
RS232
ETHERNET 10/100
JTAG/ICE
TFT
320 x 240
1/4 VGA DISPLAY
WITH TOUCHSCREEN
HEADPHONE
OUT
RJ45
TXD
RXD
2.7
ADM3202A
POWER SUPPLY
5 VDC
AT73C213
STEREO
AUDIO DAC
EMAC + PHY
LINEAR REGULATOR
TRACE PORT
VDD3V3
3V3
ETM
SPI0
SPI0_NPCS2
SCC1
PA29 / SPI0_NPCS3
SCC1 I2S
HDMB - HDPB
USB HOST
3
2
1
1V2
3
2
1
32
SDRAM
256 Mb
16
SDRAM
256 Mb
SPI0
8
CS
16
1.2V
3V
+
MISO - MOSI - SPCK
EBI
WKUP
GNDBU
SHDN
VDDBU
PIO
SPI0_NPCS0
18.432 MHz
XIN
3V3
LCD CONTROLLER
AT91SAM9G10
XOUT
EXT CLK INPUT
HDMA - HDPA
DDM
USB DEVICE
DRXD - DTXD
SYSTEM CONTROLLER
CONTROLLER
SPI0_NPCS3 / PA6
VDDIO
DBGU
SHUTDOWN
VDDPLL VDDOSC
EBI
VDDCORE
PA11..PA31
1V2
NRST
1V2
REG
1V2
DDP
TOUCHSCREEN
NRST
EXPANSION CONNECTORS
PIO
MCI
5V
LCD CONTROL
SHUTDOWN
YELLOW POWER LED
NANDFLASH
DATAFLASH
DEVICE
3V3
USER'S GREEN LED
9 1 2 3 4 5 6 7 8
SD/MMC
DATAFLASH
CARD READER
AT91SAM9G10-EK Evaluation Board User Guide
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6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
Section 3
Board Description
3.1
AT91SAM9G10 Microcontroller
Incorporates the ARM926EJ-S™ ARM Thumb Processor
– DSP Instruction Extensions
– ARM Jazelle® Technology for Java® Acceleration
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– 266 MHz core frequency
– Memory Management Unit
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
– Mid-level implementation Embedded Trace Macrocell™
Additional Embedded Memories
– 32K Bytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
– 160K Bytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed
External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash and CompactFlash®
LCD Controller
– RGB Addressing
– Supports Passive or Active Displays
– Up to 16-bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048
USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
Dual On-chip Transceivers
Integrated FIFOs and Dedicated DMA Channels
– USB 2.0 Full Speed (12 Mbits per second) Device Port
On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
Bus Matrix
– Handles Five Masters and Five Slaves
– Boot Mode Select Option
– Remap Command
Fully Featured System Controller (SYSC) for Efficient System Management, including
– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16
Bytes
AT91SAM9G10-EK Evaluation Board User Guide
3-1
6479A–ATARM–26-May-09
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Three 32-bit PIO Controllers
Reset Controller (RSTC)
– Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control
Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– 32.768 kHz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow
Clock
– 3 to 20 MHz On-chip Oscillator and two PLLs
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire USART and Support for Debug Communication Channel, Programmable ICE Access
Prevention
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock
Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock
Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
Nineteen Peripheral DMA (PDC) Channels
Multimedia Card Interface (MCI)
– Compliant with Multimedia Cards and SDCards
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard
Compliant
Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
3-2
6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
– Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel EEPROMs Supported
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC and for VDDPLL
– 2.7V to 3.6V for VDDIOP (Peripheral I/Os)
– 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os)
Available in a 217-ball LFBGA RoHS-compliant Package
AT91SAM9G10-EK Evaluation Board User Guide
3-3
6479A–ATARM–26-May-09
AT91SAM9G10 Block Diagram
Figure 3-1.
Block Diagram
ARM926EJ-S Core
ICE
Instruction Cache
16K bytes
TCM
Interface
System Controller
I
PIO
AIC
ITCM
DBGU
PLLA
PLLRCB
PLLB
XIN
XOUT
OSC
OSC
POR
VDDCORE
POR
EBI
CompactFlash
NAND Flash
SDRAM
Controller
PIT
Peripheral
Bridge
RTT
Static
Memory
Controller
Peripheral
DMA
Controller
SHDWC
VDDBU
GNDBU
DTCM
5-layer
Matrix
GPBREG
SHDN
WKUP
D
Fast ROM
32K bytes
PMC
WDT
XIN32
XOUT32
I
Fast SRAM
160K bytes
PDC
PLLRCA
D
DMA
FIFO
RSTC
USB Host
NRST
APB
PIOA
PIOB
TCLK
TPS0-TPS2
TPK0-TPK15
BIU
PIO
TST
FIQ
IRQ0-IRQ2
DRXD
DTXD
PCK0-PCK3
ETM
Data Cache
16K bytes
MMU
PIO
TSYNC
JTAG
Boundary Scan
FIFO
PIOC
USB Device
Transceiver
JTAGSEL
TDI
TDO
TMS
TCK
NTRST
RTCK
BMS
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15/A18-A21
A22/REG
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NCS2
NCS3/NANDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
SDCKE
RAS-CAS
SDWE
SDA10
NWAIT
A23-A24
A25/CFRNW
NCS4/CFCS0
NCS5/CFCS1
CFCE1
CFCE2
NCS6/NANDOE
NCS7/NANDWE
D16-D31
HDMA
HDPA
HDMB
HDPB
Transceiver
3.2
DDM
DDP
DMA
MCI
LUT
LCD Controller
PDC
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
RXD1
TXD1
SCK1
RTS1
CTS1
USART1
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI1_NPCS10
SPI1_NPCS1
SPI1_NPCS12
SPI1_NPCS3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
3-4
6479A–ATARM–26-May-09
PIO
PIO
PDC
SSC0
PDC
TF0
TK0
TD0
RD0
RK0
RF0
SSC1
PDC
TF1
TK1
TD1
RD1
RK1
RF1
PIO
MCCK
MCCDA
MCDA0-MCDA3
RXD2
TXD2
SCK2
RTS2
CTS2
LCDD0-LCDD23
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDCC
FIFO
PDC
USART2
SSC2
PDC
PDC
Timer Counter
SPI0
PDC
TC0
TC1
TC2
TF2
TK2
TD2
RD2
RK2
RF2
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
SPI1
TWI
PDC
TWD
TWCK
AT91SAM9G10-EK Evaluation Board User Guide
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Memory
32 Kbytes of Internal ROM
160 Kbytes of Internal High-speed SRAM
Atmel serial DataFlash
64 Mbytes of SDRAM memory
256 Mbytes of NAND Flash memory
Clock Circuitry
18.432 MHz standard crystal for the embedded oscillator
32.768 kHz standard crystal for the slow clock oscillator
Reset Circuitry
Internal reset controller with a bi-directional reset pin
External reset push button
Shutdown Controller
Programmable shutdown and Wake-Up
Wake-up push button
Power Supply Circuitry
For dynamic power consumption, the AT91SAM9G10 consumes a maximum of 50 mA on VDDCORE
at maximum speed in typical conditions (1.2V, 25°C), processor running full-performance algorithm
On-board 1.2V high efficiency step-down charge pump regulator with shutdown control
On-board 3.3V linear regulator with shutdown control
Remote Communication
One Serial interface (DBGU COM Port) via RS-232 DB9 male socket
USB V2.0 Full-speed Compliant, 12 Mbits per second (UDP)
Two USB Host port V2.0 Full-speed Compliant, 12 Mbits per second (UHP)
One Ethernet 100-base TX with three status LEDs
Audio Stereo Interface
One Atmel stereo audio DAC AT73C213
One 32 Ohm/20 mW Stereo Headset output (J20) with Master Volume and Mute Controls
AT91SAM9G10-EK Evaluation Board User Guide
3-5
6479A–ATARM–26-May-09
3.10
3.11
3.12
User Interface
Four user input pushbuttons
Two user green LEDs
One yellow power LED (can be also software controlled)
One ¼ VGA display LCD with Touchscreen and white LED backlight
Debug Interface
20-pin JTAG/ICE interface connector
DBGU COM Port
Expansion Slot
One DataFlash, SD/MMC card slot
All I/Os of the AT91SAM9G10 are routed to peripheral extension footprint connectors (J16 and J17).
This allows the developer to check the integrity of the components and to extend the features of the
board by adding external hardware components or boards.
3-6
6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
3.13
PIO Usage
Table 3-1. PIO Controller A
I/O Line
Peripheral A
Peripheral B
Comments
PA0
SPI0_MISO
MCDA0
SD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DAC
SPI0_MISO or
MCI0_DA0
PA1
SPI0_MOSI
MCCDA
SD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DAC
SPI0_MOSI or
MCI0_CDA
PA2
SPI0_SPCK
MCCK
SD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DAC
SPI0_SPCK or
MCCK
PA3
SPI0_NPCS0
DATAFLASH DEVICE or DATAFLASH SOCKET (J9)
SPI0_NPCS0
PA4
SPI0_NPCS1
MCDA1
SD/MMC/DATAFLASH SOCKET (J9)
MCDA1
PA5
SPI0_NPCS2
MCDA2
SD/MMC/DATAFLASH SOCKET (J9)
MCDA2
PA6
SPI0_NPCS3
MCDA3
SD/MMC/DATAFLASH SOCKET (J9)
SPI0_NPCS3 or
MCDA3
PA7
TWD
PCK0
PA8
TWCK
PCK1
PA9
DRXD
PCK2
SERIAL DEBUG PORT (J15)
DRXD
PA10
DTXD
PCK3
SERIAL DEBUG PORT (J15)
DTXD
PA11
TSYNC
SCK1
TOUCH SCREEN CONTROLLER (MN16) BUSY
PA11
PA12
TCLK
RTS1
TFT PANEL CONTROL (J23) POWER CONTROL IN
PA12
PA13
TPS0
CTS1
GREEN USER'S LED 1 (DS8)
PA13
PA14
TPS1
SCK2
GREEN USER'S LED 2 (DS7)
PA14
PA15
TPS2
RTS2
PA16
TPK0
CTS2
PA17
TPK1
TF1
I2S AUDIO DAC AT73C213 (MN15) LRFS
TF1
PA18
TPK2
TK1
I2S AUDIO DAC AT73C213 (MN15) BCLK
TK1
PA19
TPK3
TD1
I2S AUDIO DAC AT73C213 (MN15) SDIN
TD1
PA20
TPK4
RD1
PA21
TPK5
RK1
PA22
TPK6
RF1
PA23
TPK7
RTS0
YELLOW POWER LED CONTROL (DS1)
PA23
PA24
TPK8
SPI1_NPCS1
USER'S PUSH BUTTON INPUT (BP6)
PA24
PA25
TPK9
SPI1_NPCS2
USER'S PUSH BUTTON INPUT (BP5)
PA25
PA26
TPK10
SPI1_NPCS3
USER'S PUSH BUTTON INPUT (BP4)
PA26
PA27
TPK11
SPI0_NPCS1
USER'S PUSH BUTTON INPUT (BP3)
PA27
PA28
TPK12
SPI0_NPCS2
TOUCH SCREEN CONTROLLER (MN16)
SPI0_NPCS2
PA29
TPK13
SPI0_NPCS3
I2S AUDIO DAC AT73C213 (MN15)
SPI0_NPCS3
PA30
TPK14
A23
PA31
TPK15
A24
AT91SAM9G10-EK Evaluation Board User Guide
3-7
6479A–ATARM–26-May-09
Table 3-2. PIO Controller B
I/O Line
Peripheral A
Peripheral B
PB0
LCDVSYNC
PB1
LCDHSYNC
PB2
LCDDOTCK
PB3
LCDDEN
PB4
LCDCC
LCDD2
PB5
LCDD0
LCDD3
PB6
LCDD1
LCDD4
PB7
LCDD2
PB8
Comments
TFT PANEL CONTROL (J23)
LCDHSYNC
TFT PANEL CONTROL (J23)
LCDDOTCK
TFT PANEL CONTROL (J23)
LCDDEN
TFT PANEL CONTROL (J23) BACKLIGHT
LCDCC
LCDD5
TFT PANEL CONTROL (J23)
LCDD2
RED
LCDD3
LCDD6
TFT PANEL CONTROL (J23)
LCDD3
RED
PB9
LCDD4
LCDD7
TFT PANEL CONTROL (J23)
LCDD4
RED
PB10
LCDD5
LCDD10
TFT PANEL CONTROL (J23)
LCDD5
RED
PB11
LCDD6
LCDD11
TFT PANEL CONTROL (J23)
LCDD6
RED
PB12
LCDD7
LCDD12
TFT PANEL CONTROL (J23)
LCDD7
RED
PB13
LCDD8
LCDD13
PB14
LCDD9
LCDD14
PB15
LCDD10
LCDD15
TFT PANEL CONTROL (J23)
LCDD10
GREEN
PB16
LCDD11
LCDD19
TFT PANEL CONTROL (J23)
LCDD11
GREEN
PB17
LCDD12
LCDD20
TFT PANEL CONTROL (J23)
LCDD12
GREEN
PB18
LCDD13
LCDD21
TFT PANEL CONTROL (J23)
LCDD13
GREEN
PB19
LCDD14
LCDD22
TFT PANEL CONTROL (J23)
LCDD14
GREEN
PB20
LCDD15
LCDD23
TFT PANEL CONTROL (J23)
LCDD15
GREEN
PB21
TF0
LCDD16
PB22
TK0
LCDD17
PB23
TD0
LCDD18
TFT PANEL CONTROL (J23)
LCDD18
BLUE
PB24
RD0
LCDD19
TFT PANEL CONTROL (J23)
LCDD19
BLUE
PB25
RK0
LCDD20
TFT PANEL CONTROL (J23)
LCDD20
BLUE
PB26
RF0
LCDD21
TFT PANEL CONTROL (J23)
LCDD21
BLUE
PB27
SPI1_NPCS1
LCDD22
TFT PANEL CONTROL (J23)
LCDD22
BLUE
PB28
SPI1_NPCS0
LCDD23
TFT PANEL CONTROL (J23)
LCDD23
BLUE
PB29
SPI1_SPCK
IRQ2
USB DEVICE INTERFACE (J19) USB_CNX
PB29
PB30
SPI1_MISO
IRQ1
PB31
SPI1_MOSI
PCK2
I2S AUDIO DAC AT73C213 (MN15) MCLK
PCK2
3-8
6479A–ATARM–26-May-09
PCK0
AT91SAM9G10-EK Evaluation Board User Guide
Table 3-3. PIO Controller C
I/O Line
Peripheral A
Peripheral B
PC0
NANDOE
NCS6
NAND FLASH DEVICE (MN6x)
NANDOE
PC1
NANDWE
NCS7
NAND FLASH DEVICE (MN6x)
NANDWE
PC2
NWAIT
IRQ0
TOUCH SCREEN CONTROLLER (MN16) PENIRQ
IRQ0
PC3
A25/CFRNW
PC4
NCS4/CFCS0
PC5
NCS5/CFCS1
PC6
CFCE1
PC7
CFCE2
PC8
TXD0
PCK2
PC9
RXD0
PCK3
PC10
RTS0
SCK0
ETHERNET CONTROLLER (MN8) RST
PC10
PC11
CTS0
FIQ
ETHERNET CONTROLLER (MN8) IRQ
PC11
PC12
TXD1
NCS6
PC13
RXD1
NCS7
PC14
TXD2
SPI1_NPCS2
NAND FLASH DEVICE (MN6x) CHIP ENABLE (CE)
PC14
PC15
RXD2
SPI1_NPCS3
NAND FLASH DEVICE (MN6x) READY/BUSY (R/B)
PC15
PC16
D16
TCLK0
EBI DATA BUS D16
D16
PC17
D17
TCLK1
EBI DATA BUS D17
D17
PC18
D18
TCLK2
EBI DATA BUS D18
D18
PC19
D19
TIOA0
EBI DATA BUS D19
D19
PC20
D20
TIOB0
EBI DATA BUS D20
D20
PC21
D21
TIOA1
EBI DATA BUS D21
D21
PC22
D22
TIOB1
EBI DATA BUS D22
D22
PC23
D23
TIOA2
EBI DATA BUS D23
D23
PC24
D24
TIOB2
EBI DATA BUS D24
D24
PC25
D25
TF2
EBI DATA BUS D25
D25
PC26
D26
TK2
EBI DATA BUS D26
D26
PC27
D27
TD2
EBI DATA BUS D27
D27
PC28
D28
RD2
EBI DATA BUS D28
D28
PC29
D29
RK2
EBI DATA BUS D29
D29
PC30
D30
RF2
EBI DATA BUS D30
D30
PC31
D31
PCK1
EBI DATA BUS D31
D31
AT91SAM9G10-EK Evaluation Board User Guide
Comments
3-9
6479A–ATARM–26-May-09
3-10
6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
Section 4
Configuration Straps
4.1
Configuration Straps
Table 4-1 gives details on configuration straps on the AT91SAM9G10-EK evaluation board and their
default settings.
Table 4-1. Configuration Jumpers and Straps
Designation
Default
Setting
Feature
J2
Closed
3.3V Jumper (1)
This jumper footprint is provided for 3.3V power consumption
measurement use. By default, it is closed. To use this feature,
the user has to open the strap by cutting it before soldering a
jumper.
J3
Closed
Forces power on. To use the software shutdown control, J3
must be opened.
J4
Open
Enables Boot on the internal ROM
Closed
Enables Boot on the NCS0
J8
Closed
VDDPLL Jumper (1)
J9
2-3
J12
Closed
VDDBU Jumper select (1)
1-2: Lithium 3V Battery
2-3: 1.2V from VDDCORE
VDDCORE Jumper (1)
J21
1-2
NPCS0 select
1-2: DataFlash device (MN7)
2-3: DataFlash card interface (J22)
Warning: In this case NPCS03 must be configured as
input.
J24
Closed
Enables the selection of the on-board Nand-Flash device.
Remove this jumper to prevent the system boot from that
device and to be able to reprogram it.
S2
Open
S3
Closed
Enables the ICE RTCK return. S6 must be opened
S4
Closed
Enables the ICE NRST input
S5
Open
Selects ICE mode or JTAG mode (See Section 6, Errata)
S6
Open
Disables TCK <-> RTCK local loop. If S6 is closed, S3 must be
opened.
S7-S8
S9
Closed
Open
AT91SAM9G10-EK Evaluation Board User Guide
Disables the ICE NTRST input
Enables the use of 18.432 MHz crystal. If external clock used,
S7-S8 must be opened and S9 closed.
4-1
6479A–ATARM–26-May-09
Table 4-1. Configuration Jumpers and Straps
Designation
Default
Setting
Feature
S10
Closed
Enables the use of SDRAM (NCS1_SDCS)
S12
Open
S13
Closed
Disables NAND FLASH write protect.
S14
Closed
Enables the use of interrupt ETHERNET MAC (PC11_FIQ).
S15
Closed
Enables the use of ETHERNET MAC (NCS2).
S16
Open
S19
Closed
Enables the use of the User LED DS7 (PA14)
S20
Closed
Enables the use of the User LED DS8 (PA13)
S21
Closed
Enables the use of the DBGU RXD signal (PA9)
S22
Closed
Enables the use of the USB CNX detection (PB29)
S23
Closed
Enables the use of AUDIO DAC INTERFACE (NPCS03)
S24
Closed
Enables the use of TOUCH SCREEN CONTROLLER
(NPCS02)
S25
Closed
Enables the use of TOUCH SCREEN CONTROLLER BUSY
signal (PA11)
S26
Closed
Enables the use of TOUCH SCREEN CONTROLLER PENIRQ
(PC2_IRQ0)
TP1
N.A
3.3V Test point.
TP2
N.A
GND Test point.
TP3
N.A
1.2V Test point.
TP4
N.A
GND Test point.
TP63
N.A
0 to 3.3V analog user's input
TP64
N.A
0 to 3.3V analog user's input
TP65
N.A
AGND of TP63
TP66
N.A
AGND of TP64
Note:
4-2
6479A–ATARM–26-May-09
Disables Serial DataFlash write protect.
Disables the use of NWAIT ETHERNET MAC signal
(PC2_NWAIT)
1. These jumpers are provided for measuring power consumption. By default, they are closed. To use this
feature, the user has to open the strap and insert an ammeter.
AT91SAM9G10-EK Evaluation Board User Guide
Section 5
Schematics
5.1
Schematics
This section contains the following schematics:
Power Supply and Audio
AT91SAM9G10 Device
SDRAM and NAND Flash
Ethernet
LCD and User Interface
Serial and I/O Expansion
AT91SAM9G10-EK Evaluation Board User Guide
5-1
6479A–ATARM–26-May-09
6
4
3
POWER
2
EBI SDRAM INTERFACE
DATA BUS
PIO A,B,C
NAND FLASH
DEBUG
PORT
SERIAL
MMC/SD
DATAFASH CARD DATA
FLASH
PIO A,B,C
USB INTERFACES
HOST
DEVICE
D
ADRESSE BUS
SHEET 2
ATMEL
ARM9 Processor
SAM9G10 (LFBGA217)
CARD
READER
C
PIO A,B,C
C
SHEET 4
ICE INTERFACE
ETHERNET
EXPANSION CONNECTORS
B
1
SDRAM
AUDIO DAC
INTERFACE
D
5
EBI SDRAM
7
5V
8
SHEET 7
DATA BUS
B
SHEET 5
LCD
SHEET 3
PIO A,B,C
USER INTERFACE
TOUCH SCREEN
CONTROLLER
A
PIOA
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
SHEET 6
NOTE
"DNP" means the component is not populated by default
USAGE
SPI0_MISO /MCDA0
SPI0_MOSI /MCCDA
SPI0_SPCK
SPI0_NPCS0
MCDA1
MCDA2
SPI0_NPCS3 MCDA3
--DBGU_RXD
DBGU_TXD
BUSY
POW ER CONTROL IN
USER LED
USER LED
--
PIO MUXING
PIOA
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
USAGE
-TF1
TK1
TD1
---POW ER LED
BP6
BP5
BP4
BP3
SPI0_NPCS2
SPI0_NPCS3
---
PIOB
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
USAGE
-LCDHSYNC
LCDDDOTCK
LCDDEN
LCDCC
--R0
R1
R2
R3
R4
R5
--G0
PIOB
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
USAGE
G1
G2
G3
G4
G5
--B0
B1
B2
B3
B4
B5
USB_CNX
USB_DP_PUP
PCK2
USAGE
PIOC
NANDOE
NANDW E
IRQ0 /NW AIT
-------RST
FIQ
--#CE
R/#B
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
A
A INIT EDIT
REV MODIF.
AT91SAM9G10-EK
TOP LEVEL
PP
DES.
15MAY09
DATE
1/1
SCALE
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6
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7
6
5
D
4
3
2
1
D
3V3
AUDIO DAC INTERFACE
10 SQUARE CM COPPER AREA FOR HEAT SINKING
WITH NO SOLDER MASK
LT1963AEQ-3.3
6
REGULATED
5V ONLY
5V
3
C1
330µF
C2
MN1
10µF
10V
2
VIN
R2
100K
1
2
J1
R1
120R
+
CR1
5V
GND
VOUT
SD
GND
FB
1
3
5
J2
4
TP1
3.3V
C3
10µF
3V3
POWER LED
3V3
DS1
YELLOW
C4
10µF
3
TP2
GND
Q1
IRLML2402
1
M5V {6}
15
12
14
13
PA23
PA23 {3,7}
2
C5
1uF
C6
1uF
5
4
8
5V
1
Q2
6
Si1563EDH
C1M
5
J3
6
3
4
C1P C2M
VIN
C2P
VOUT
7
C7 R3
22uF 100K
C8
10PF
1
30
MONOP
29
MONON
2
3
R5
10K
R6
10K
TPS60500
C10
4.7uF
FB
1
EN
GND
9
J20
10
2
3.5 PHONEJACK STEREO
3
1
4
2
R4
200K
C113
TP4
GND
100µF
6V3
C112
+
MN2
{3,7} SHDN
PG
TP3
1.2V
100µF
6V3
6
LINEL
31
AUXP
32
AUXN
4
HSR
3
HSL
8
Z3
Z4
11.1
11.1
Z7
Z8
11.1
11.1
25
26
27
28
SMODE
RSTB
22
21
VDIG
24
3V3
AVDD
2
VCC_DAC
AVDDHS
5
VCM
C107 10uF
9
VREF
C111
1
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS3
PA0
PA1
PA2
PA29
PA0 {3,4,6,7}
PA1 {3,4,6,7}
PA2 {3,4,6,7}
PA29 {3,7}
S23
NRST {3,4,5,7}
C
MCLK
SDIN
LRFS
BCLK
INGND
ADHESIVE FEET
DOUT
DIN
CLK
CS
LINER
+
C9
15PF
PAINP
1V2
2
FORCE
POWER
ON
HPN
LPHN
16
R67
100K
AT73C213
PAINN
VBAT
CBP
HPP
11
10
7
C
MN15
GNDB
20
17
19
18
C110
100NF
10uF
R68
47R
C108 C109
100NF 100NF
GND_DAC
PCK2
TD1
TF1
TK1
PB31
PA19
PA17
PA18
PB31
PA19
PA17
PA18
{3,7}
{3,7}
{3,7}
{3,7}
GNDD
33
23
GND_DAC
VCC_DAC
3V3
L4
4.7uH
B
B
C114
10µF
10V
R69 0R
GND_DAC
A
A
A INIT EDIT
REV MODIF.
AT91SAM9G10-EK
POW ER SUPPLY & AUDIO
SCALE
PP
DES.
15MAY09
DATE
1/1
7
6
5
4
3
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DATE
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7
8
7
6
5
4
3
2
1
{4,5,6,7} PC[0..15]
DNP
R9
TRACECLK
DNP
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
G1
G2
G3
G4
G5
C11
DNP
TRACEPKT[8]
TRACEPKT[9]
TRACEPKT[10]
TRACEPKT[11]
TRACEPKT[12]
TRACEPKT[13]
TRACEPKT[14]
TRACEPKT[15]
ICE_NTRST
TDI
TMS
TCK
ICE_RTCK
TDO
ICE_NRST
DBGRQ
GND
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
R10
DNP
J5
DNP
C
5
6
7
8
3V3
RR1
100K
2
4
6
8
10
12
14
16
18
20
4
3
2
1
J6
1
3
5
7
9
11
13
15 ICE_NRST
17
19
ICE_NTRST
TDI
TMS
TCK
ICE_RTCK
TDO
S4
S2
{7} DDP
{7} DDM
A12
B12
{7} HDPA
{7} HDMA
C12
B14
{7} HDPB
{7} HDMB
A13
A14
S3
NRST
S5
3V3
E17
C17
D17
U17
F16
B10
F17
S6
22nF
C12
C13
C14
15nF
B
R11
2.2nF
R12
C15
2K
1.5nF
S7
2
C16
10PF
1,5K
1%
U9
U10
U12
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
HDPA
HDMA
HDPB
HDMB
TDI
TMS
TCK
RTCK
TDO
JTAGSEL
RAS
CAS
NTRST
SDW E
SDA10
SDCKE
SDCK
PLLRCB
NCS0
SDCS/NCS1
NCS2
NANDCS/NCS3
CFOE/NRD
PLLRCA
XOUT
Y1
18.4320MHz
2
R15
1K
1
3
C126
100NF
VDDIOP
VDDIOP
VDDIOP
P15
P11
VDDIOP
VDDIOP
J14
D11
C15
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
N4
L4
H3
D4
C8
VDDIOM
C3
C5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A16
C7
C11
D3
H8
H9
H10
J3
J8
J9
J10
K8
K9
K10
R3
R16
U4
U7
VDDCORE
VDDCORE
VDDCORE
P12
M4
3
2
1
D5
GNDPLL
VDDCORE
NC1
NC2
NC3
GNDBU
TST
VDDPLL
VDDBU
XIN32
1V2
J9
D8
B8
A8
A7
B7
D7
A6
B6
C6
A5
D6
B5
A4
B4
A3
B3
A2
C4
B2
A1
B1
C2
C1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
C
F2
J4
RAS {4,7}
CAS {4,7}
G3
E4
F1
H4
SDWE {4,7}
SDA10 {4,7}
SDCKE {4,7}
SDCK {4,7}
F4
D2
D1
G4
E3
NCS0 {7}
SDCS_NCS1 {4,7}
NCS2 {5,7}
SMCS_NCS3 {7}
CFOE_NOE_NRD {5,7}
E2
E1
F3
CFWE_NWE_NWR0 {5,7}
CFIOR_NBS1_NWR1 {4,7}
CFIOW_NBS3_NWR3 {4,7}
F15
NRST
B
NRST {2,4,5,7}
R13
1K
K14
GND
OUT
2
CR2
MMBD1704A
J10
VDD
3V3
A
MN10
R1100D121C
{4,5,7}
C10
A9
C14
D10
R14
1K
BP1
3V3 C43
10µF
10V
A
1
3
VDDOSC + VDDPLL
CURRENT MEASURE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
XOUT32
C9
R10
C21
100NF
P9
{4,5,7}
A[0..22]
3V3
SHDN
1
NRST
G1
G2
H1
H2
J1
J2
K1
K4
K2
L1
K3
L2
L3
M1
N1
M2
GNDOSC
WKUP
J8
A11
VDDOSC
B11
2
3V3
A10
32.768 kHz
Y2
C20
10PF
T10
C18
100NF
T11
CFW E/NW E/NW R0
CFIOR/NBS1/NW R1
CFIOW /NBS3/NW R3
XIN
B9
SMB MALE
U11
D9
C19
10PF
4
2
4
S8
S9
1
C17
10PF
1
3
5
1
J7
DNP
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
NBS0/A0
NW R2/NBS2/A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BA0/A16
BA1/A17
A18
A19
A20
A21
A22
AT91SAM9G10
DDP
DDM
D[0..31]
D
VDDIOP
EXTTRIG R8
PA12
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
PA0/SPI0_MISO/MCDA0
PA1/SPI0_MOSI/MCCDA
PA2/SPI0_SPCK/MCCK
PA3/SPI0_NPCS0
PA4/SPI0_NPCS1/MCDA1
PA5/SPI0_NPCS2/MCDA2
PA6/SPI0_NPCS3/MCDA3
PA7/TW D/PCK0
PA8/TW CK/PCK1
PA9/DRXD/PCK2
PA10/DTXD/PCK3
PA11/TSYNK/SCK1
PA12/TCLK/RTS1
PA13/TPS0/CTS1
PA14/TPS1/SCK2
PA15/TPS2/RTS2
PA16/TPK0/CTS2
PA17/TPK1/TF1
PA18/TPK2/TK1
PA19/TPK3/TD1
PA20/TPK4/RD1
PA21/TPK5/RK1
PA22/TPK6/RF1
PA23/TPK7/RTS0
PA24/TPK8/SPI1_NPCS1
PA25/TPK9/SPI1_NPCS2
PA26/TPK10/SPI1_NPCS3
PA27/TPK11/SPI0_NPCS1
PA28/TPK12/SPI0_NPCS2
PA29/TPK13/SPI0_NPCS3
PA30/TPK14/A23
PA31/TPK15/A24
VDDIOP
3V3
PIPESTAT[0]
PIPESTAT[1]
PIPESTAT[2]
TRACESYNC
TRACEPKT[0]
TRACEPKT[1]
TRACEPKT[2]
TRACEPKT[3]
TRACEPKT[4]
TRACEPKT[5]
TRACEPKT[6]
TRACEPKT[7]
VSUPPLY
R11
T12
U13
P10
T13
U14
T14
R12
T15
U16
R13
T16
U15
R14
T17
P13
P14
R15
R17
P16
P17
N15
N14
N16
N17
M14
M15
L15
M16
M17
L14
L16
U6
PA13
PA14
PA15
PA11
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
T5
1
D
U2
P6
T4
U3
R6
T6
U5
P7
R7
T7
T8
P8
R8
U8
R9
T9
P1
N2
M3
R1
T1
R2
P3
T2
P4
U1
T3
R4
P5
R5
P2
N3
MN3
{2,4,6,7} PA[0..31]
ETM
TRACE PORT
NANDOE/NCS6/PC0
NANDWE/NCS7/PC1
NWAIT/IRQ0/PC2
A25/CFRNW/PC3
NCS4/CFCS0/PC4
NCS5/CFCS1/PC5
CFCE1/PC6
CFCE2/PC7
TXD0/PCK2/PC8
RXD0/PCK3/PC9
RTS0/SCK0/PC10
CTS0/FIQ/PC11
TXD1/NCS6/PC12
RXD1/NCS7/PC13
TXD2/SPI1_NPCS2/PC14
RXD2/SPI1_NPCS3/PC15
D16/TCLK0/PC16
D17/TCLK1/PC17
D18/TCLK2/PC18
D19/TIOA0/PC19
D20/TIOB0/PC20
D21/TIOA1/PC21
D22/TIOB1/PC22
D23/TIOA2/PC23
D24/TIOB2/PC24
D25/TF2/PC25
D26/TK2/PC26
D27/TD2/PC27
D28/RD2/PC28
D29/RK2/PC29
D30/RF2/PC30
D31/PCK1/PC31
1K
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
BMS
LCDVSYNC/PB0
LCDHSYNK/PB1
LCDDOTCK/PCK0/PB2
BMS/LCDDEN/PB3
LCDCC/LCDD2/PB4
LCDD0/LCDD3/PB5
LCDD1/LCDD4/PB6
LCDD2/LCDD5/PB7
LCDD3/LCDD6/PB8
LCDD4/LCDD7/PB9
LCDD5/LCDD10/PB10
LCDD6/LCDD11/PB11
LCDD7/LCDD12/PB12
LCDD8/LCDD13/PB13
LCDD9/LCDD14/PB14
LCDD10/LCDD15/PB15
LCDD11/LCDD19/PB16
LCDD12/LCDD20/PB17
LCDD13/LCDD21/PB18
LCDD14/LCDD22/PB19
LCDD15/LCDD23/PB20
TF0/LCDD16/PB21
TK0/LCDD17/PB22
TD0/LCDD18/PB23
RD0/LCDD19/PB24
RK0/LCDD20/PB25
RF0/LCDD21/PB26
SPI1_NPCS1/LCDD22/PB27
SPI1_NPCS0/LCDD23/PB28
SPI1_SPCK/IRQ2/PB29
SPI1_MISO/IRQ1/PB30
SPI1_MOSI/PCK2/PB31
2
R7
J4
PB3
L17
K16
K17
K15
J17
H17
J16
H16
G17
J15
H14
G16
G15
H15
G14
E16
F14
D16
E15
B17
D15
C16
E14
D14
A17
B16
B15
A15
D13
D12
C13
B13
{2,6,7} PB[0..31]
BOOT MODE SELECT
WAKE UP
R16
R17
DNP
100K
C28
10µF
10V
C22
100NF
BP2
{7} VDDBU
{2,7} SHDN
{7} WKUP
C24
C26
100NF 100NF
C23
C25
C27
J12
1
2
10µF
100NF
100NF
1V2
10V
VDDCORE CURRENT MEASURE
C29
C31
C33
C35
100NF
100NF
100NF
100NF
C30
C32
C34
100NF
100NF
100NF
C36
C38
C40
C42
100NF
100NF
100NF
100NF
C37
C39
C41
100NF
100NF
100NF
A INIT EDIT
REV MODIF.
AT91SAM9G10-EK
AT91SAM9G10
SCALE
PP
DES.
15/05/09
DATE
1/1
7
6
5
4
3
2
XX/XX/XX
SHEET
A
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
XXX
REV.
VER.
1
DATE
3
7
8
7
6
5
4
3
2
1
EBI SDRAM INTERFACE
{3,5,7} A[0..22]
{3,5,7} D[0..31]
{3,7} RAS
{3,7} CAS
{3,7}
{3,7}
{3,7}
{3,7}
D
SDW E
SDA10
SDCKE
SDCK
D
{3,7} CFIOR_NBS1_NW R1
{3,7} CFIOW _NBS3_NW R3
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
{3,7} SDCS_NCS1
A13
A16
A17
SDA10
20
21
BA0
BA1
36
40
A14
C
23
24
25
26
29
30
31
32
33
34
22
35
SDCKE
37
SDCK
38
NBS0
15
A0
CFIOR_NBS1_NW R1 39
3V3
R18
100K
CAS
RAS
17
18
SDW E
16
19
MN4
A0 MT48LC16M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
A16
A17
SDA10
20
21
BA0
BA1
36
40
A14
3V3
1
14
27
3
9
43
49
23
24
25
26
29
30
31
32
33
34
22
35
SDCKE
37
SDCK
38
NBS2
15
A1
CFIOW _NBS3_NW R3 39
28
41
54
6
12
46
52
C50
C51
C52
C53
100NF
100NF
100NF
100NF
C44
C45
C46
100NF
100NF
100NF
CAS
RAS
17
18
SDW E
16
19
MN5
256 Mbits
S10
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
A0 MT48LC16M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
1
14
27
3
9
43
49
28
41
54
6
12
46
52
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
3V3
C
C54
C55
C56
C57
100NF
100NF
100NF
100NF
C47
C48
C49
100NF
100NF
100NF
256 Mbits
DUAL FOOTPRINT
{3,5,7} D[0..31]
3V3
3V3
R85
100K
3V3
B
R19
100K
{3,7}
{3,7}
{3,7}
{3,7}
{3,7}
A21
A22
PC0
PC1
PC14
{3,7} PC15
A21
A22
PC0
PC1
PC14 1
J24
PC15
2
16
17
8
18
NANDCE 9
7
19
WP
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
34
35
S13
MN6A
16-bit bus width
CLE
ALE
RE
WE
CE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
R/B
WP
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
N.C18
PRE
N.C19
VCC
VCC
VSS
VSS
VSS
26
28
30
32
40
42
44
46
27
29
31
33
41
43
45
47
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A21
A22
PC0
PC1
NANDCE
PC15
WP
39
38
36
37
12
3V3
C60
100NF
48
25
13
C59
100NF
MT29F2G16AABW P
DNP
16
17
8
18
9
7
19
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
MN6B
8-bit bus width
CLE
ALE
RE
WE
CE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
R/B
WP
N.C18
N.C19
N.C20
N.C21
N.C22
N.C23
PRE
N.C24
N.C25
N.C26
N.C27
N.C28
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
VCC
VCC
VSS
VSS
29
30
31
32
41
42
43
44
36
13
8
1
2
4
SO
SI
SCK
CS
VCC
GND
6
C58
100NF
7
B
3
3V3
R20
100K
RESET
WP
5
AT45DB642D-CNU
S12
W RITE PROTECT
NORMALLY OPEN
{2,3,5,7} NRST
48
47
46
45
40
39
38
35
34
33
28
27
37
12
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
PA0
PA1
PA2
{2,3,6,7} PA0
{2,3,6,7} PA1
{2,3,6,7} PA2
D0
D1
D2
D3
D4
D5
D6
D7
MN7
PA3
{3,7} PA3
3V3
1
2
3
J21
{3,7} PA4
3V3
SD CARD / MMC CARD
DATAFLASH CARD
INTERFACE
R72
10K
J22
PA4
PA0
MCDA1
SPI0_MISO MCDA0
PA2
SPI0_SPCK MCCK
PA1
PA6
PA5
SPI0_MOSI MCCDA
SPI0_NPCS3 MCDA3
MCDA2
8
7
6
5
4
3
2
1
9
3V3
{3,7} PA6
{3,7} PA5
K9F2G08U0A-PCB0
FPS009
C115
100NF
A
A
A INIT EDIT
REV MODIF.
AT91SAM9G10-EK
SDRAM & NANDFLASH
PP
DES.
15MAY09
DATE
1/1
SCALE
7
6
5
4
3
2
XX/XX/XX
SHEET
A
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
XXX
REV.
VER.
1
DATE
4
7
8
7
6
5
4
3
2
1
3V3
D
3V3
R23
4,7K
DS2
GREEN
DS3
YELLOW FULL DUPLEX
DS4
GREEN SPEED 100
LINK&ACT
Note1: 8/16 bit DataBus
selection; Removed R27
when using 16-bit mode;
otherwise is 8-bit mode.
D15
D14
D13
D12
D11
D10
D9
D8
C
3V3
A2
{3,4,7} A2
R28
4,7K
PC11 FIQ
S14
{3,7} CFOE_NOE_NRD
{3,7} CFW E_NW E_NW R0
{3,7} NCS2
D0
D1
D2
D3
D4
D5
D6
D7
{3,7} PC10
742792093
DM9000
3V3
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
R25
49R9
1%
R26
49R9
1%
1 TD+
C62
3V3
100NF
J13
16
TXD0
TX_CLK
TEST5
RX_CLK
RX_ER
RX_DV
COL
CRS
DGND
RXD3
RXD2
RXD1
RXD0
LINK_I
DVDD
AVDD
TXOTXO+
AGND
AGND
RXIRXI+
AVDD
AVDD
BGRES
R32
100K
B
L1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
DVDD
IO16
CMD
SA4
SA5
SA6
SA7
SA8
SA9
DGND
INT
J0026D21
TX+
1
3 CT
VCCA
2 TD-
TX-
2
7 RD+
RX+
3
RX-
6
C
6 CT
8 RDC63
100NF
R29
49R9
1%
75
75
75
4
R30
49R9
1%
4
5
1nF
75
5
7
C64
100NF
8
R31
6,80K
1%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
3V3
1K
15
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
IOR#
IOW#
AEN
IOWAIT
DVDD
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
RST
DGND
TEST1
TEST2
TEST3
TEST4
DVDD
X2_25M
X1_25M
DGND
SD
AGND
{3,7} PC11
1K
R24
C61
100NF
NC1
NC2
DVDD
DVDD
GPIO3
GPIO2
GPIO1
GPIO0
EECS/LED
EECK
EEDO
EEDI
DGND
LINKACT#
DUP#
SPEED#
CLK20MO
DGND
MDC
MDIO
DVDD
TX_EN
TXD3
TXD2
TXD1
R27
{2,3,4,7} NRST
R22
D
VCCA
MN8
DM9000E
DNP
1K
3V3
3V3
{3,4,7} D[0..15]
R21
B
Y3
1
S15
2
C66
22PF
25MHz
C67
22PF
3V3
C76
10µF
10V
PC10 RST
VCCA
L2
4.7uH
C77
100NF
C79
100NF
C78
10µF
10V
3V3
3V3
C68
100NF
3V3
C69
100NF
3V3
C70
100NF
3V3
C71
100NF
3V3
C72
100NF
VCCA
C73
100NF
VCCA
C74
100NF
C75
100NF
3V3
R70 0R
R71
0R
R34
4,7K
PC2
{3,6,7} PC2
NWAIT
S16
NOT USED
A
A
A INIT EDIT
REV MODIF.
AT91SAM9G10-EK
ETHERNET
PP
DES.
15MAY09
DATE
1/1
SCALE
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5
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8
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REV.
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DATE
5
7
8
7
6
5
4
3
2
1
3V3
3V3
X_RIGHT
Y_LOW
X_LEFT
Y_UP
VCTRL
Vctrl
PCI
LCDD18
B0
PB23
B1
PB24
LCDD19
LCDD20
PB25
B2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
Z17 TX09D70VM1CCA
C
R84
100K
TOUCH SCREEN CONTROLLER
54132-4097
B3
B4
B5
LCDD21
LCDD22
LCDD23
PB26
PB27
PB28
G0
G1
G2
LCDD10
LCDD11
LCDD12
PB15
PB16
PB17
G3
G4
G5
LCDD13
LCDD14
LCDD15
PB18
PB19
PB20
R0
R1
R2
LCDD2
LCDD3
LCDD4
PB7
PB8
PB9
R3
R4
R5
LCDD5
LCDD6
LCDD7
PB10
PB11
PB12
DTMG LCDDEN
HSYNC
M5V {2}
R75
10K
1
2
3
4
C87
4.7NF
MN11
RST
IN
N.C
GND
N.C1
N.C2
N.C3
N.C4
X_LEFT
Y_UP
X_RIGHT
Y_LOW
8
7
6
5
R73
R76
R77
R78
C116
10NF
NOT POPULATED
MC34064D
3
2
3
4
5
0R
0R
0R
0R
2
PA12
C117 C118
10NF 10NF
R83 10K
PB4
LCDCC
DCLK
DIN
DOUT
CS
BUSY
PENIRQ
R80
100K
100K
TP63
7
8
IN3
IN4
VREF
VCC
VCC
GND
ADS7843E
AGND
TP65
R74 47R
16
14
12
15
13
11
S24
PA2
PA1
PA0
PA28
SPI0_SPCK
SPI0_MOSI
SPI0_MISO
SPI0_NPCS2
PA2 {2,3,4,7}
PA1 {2,3,4,7}
PA0 {2,3,4,7}
PA28 {3,7}
S25
S26
PA11
PC2
BUSY
IRQ0
PA11 {3,7}
PC2 {3,5,7}
R79 0R
9
1
10
TP66
TWO USER'S ANALOG INPUTS
Full-Scale Input Span 0 to VREF
D
3V3
L5
4.7uH
C120
10µF
10V
TP64
PA12 {3,7}
POW ER CONTROL IN
Q6
IRLML2402
XP
YP
XM
YM
C119
10NF
R81
1
MN16
6
R82 0R
C122
100NF
C121 C123
100NF 100NF
VCTRL
C84
100NF
PB3
C
LCDHSYNC PB1
DCLK LCDDDOTCK PB2
3V3
PB[0..31] {2,3,7}
J23
C124
100NF
C125
10V
10µF
PA27
B
PA27 {3,7}
B
BP3
3V3
GREEN
R50
220R
S19
PA14
PA14 {3,7}
PA26
PA26 {3,7}
PA25
PA25 {3,7}
BP4
DS7
GREEN
R51
220R
S20
PA13
PA13 {3,7}
BP5
DS8
PA24
PA24 {3,7}
BP6
A
A
A INIT EDIT
REV MODIF.
AT91SAM9G10-EK
LCD_USER'S INTERFACE
PP
DES.
15MAY09
DATE
1/1
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6
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8
XXX
REV.
VER.
1
DATE
6
7
4
3
1
C91
100NF
3
4
C94
100NF
D
EXPANSION CONNECTORS
NOT POPULATED
PA[0..31]
{2,3,4,6}
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
C
A[0..22]
{3,4,5}
B
PB[0..31]
{2,3,6}
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PC[0..15]
{3,4,5,6}
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
D[0..31]
{3,4,5}
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
{2,3,4,5} NRST
D10
D11
{3} VDDBU
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
5
R52 0R
NOT POPULATED
J16
PB0
PB2
PB4
PB6
PB8
PB10
PB12
PB14
PB16
PB18
PB20
PB22
PB24
PB26
PB28
PB30
PA0
PA2
PA4
PA6
PA8
PA10
PA12
PA14
PA16
PA18
PA20
PA22
PA24
PA26
PA28
PA30
PC0
PC2
PC4
PC6
PC8
PC10
PC12
PC14
D16
D18
D20
D22
D24
D26
D28
D30
3V3
5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
J17
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
PB1
PB3
PB5
PB7
PB9
PB11
PB13
PB15
PB17
PB19
PB21
PB23
PB25
PB27
{3,4} SDCS_NCS1
PB29
{3,4} CFIOR_NBS1_NWR1
PB31
{3,5} CFOE_NOE_NRD
{3,4} CFIOW_NBS3_NWR3
PA1
{3,4} RAS
PA3
{3,4} SDWE
PA5
{3,4} CAS
PA7
PA9
PA11
PA13
PA15
PA17
PA19
PA21
PA23
PA25
PA27
PA29
PA31
PC1
PC3
PC5
PC7
PC9
PC11
PC13
PC15
D17
D19
D21
D23
D25
D27
D29
D31
A1
A4
A7
A11
A13
A15
A18
A0
A10
A17
A21
A22
D2
D3
D10
D8
D12
D11
D6
D9
3V3
3V3
5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
S21
PA9
{3} PA9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
DBGU_TXD 10
PA10
{3} PA10
11
C1+
16
VCC
15
GND
C1C2+
2
V+
C2-
C92
100NF
C93
100NF
6
V-
SERIAL DEBUG PORT
14
T
1
6
2
7
3
8
4
9
5
RXD
TXD
7
T
13
R
9
R53 0R
8
R
D
ADM3202ARN
SDCKE {3,4}
NCS2 {3,5}
CFWE_NWE_NWR0
SDA10 {3,4}
NCS0 {3}
{3,5}
5V
F1
500 mA
SDCK {3,4}
HDMA
HDPA
{3} HDMA
{3} HDPA
F2
500 mA
J18
CCUSBA-32002-30X
USB HOST INTERFACE
SMCS_NCS3 {3}
D1
D0
D5
D7
D4
D15
D13
D14
R54
39R
R55
39R
R56
15K
A1
A2
A3
A4
C96
47pF
R57
15K
C97
47pF
C
B1
B2
B3
B4
1 2
3 4
C98
100NF
3V3
HDMB
HDPB
{3} HDMB
{3} HDPB
3V3
R58
39R
R59
39R
5V
S22
PB29
{3} PB29
USER'S GRID AERA
USB_CNX
R61
15K
R62 15K
B
WKUP {3}
SHDN {2,3}
3V3
NOT POPULATED
3V3
MN14
5V
VCC
1.27 PITCH
PB30
{3} PB30
{2,3,4,5} NRST
1
USB_DP_PUP
5
4
2
NRST
3
3V3
C99
100NF
C101
47pF
C100
47pF
R63
22K
5V
MALE RIGHT ANGLED
J15
C95
100NF
R60
15K
3V3
1
3V3
MN13
DBGU_RXD 12
A2
A3
A6
A9
A12
A14
A16
A19
A5
A8
A20
2
11
5
10
6
2
7
1
C102
DNP
GND
SN74LVC1G00DBV
DNP
5V
Q5
IRLML6302
DNP
3
8
R64
DNP
2.54 PITCH
USB DEVICE INTERFACE
{3} DDM
{3} DDP
DDM
R65
39R
DDP
R66
39R
C105
15PF
C103
33PF
2
J19
1
3
C106
15PF
C104
100NF
4
5
6
A
A
A INIT EDIT
REV MODIF.
AT91SAM9G10-EK
SCALE
PP
DES.
15MAY09
DATE
1/1
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5-2
6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
Section 6
Errata
6.1
JTAGSEL S5 Footprint Selector
For JTAG selection, the S5 footprint must never be soldered, otherwise the chip can be damaged.
By default, the JTAGSEL input pin integrates a pull-down resistor (ICE mode).
To select JTAG mode, the designer should connect the JTAGSEL input pin to VDDBU power.
6.2
External Capacitor Values on XIN and XOUT
The external capacitor values on XIN and XOUT are not correct.
The 10 pF capacitors must be replaced by 22 pF capacitors.
Please refer to the electrical parameters section of the datasheet.
AT91SAM9G10-EK Evaluation Board User Guide
6-1
6479A–ATARM–26-May-09
6-2
6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
Section 7
Revision History
7.1
Revision History
Table 7-1.
Document
Comments
6479A
First issue.
AT91SAM9G10-EK Evaluation Board User Guide
Change Request
Ref.
7-1
6479A–ATARM–26-May-09
7-2
6479A–ATARM–26-May-09
AT91SAM9G10-EK Evaluation Board User Guide
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