TLK10034 www.ti.com SLLSEC7 – AUGUST 2012 QUAD-CHANNEL XAUI/10GBASE-KR TRANSCEIVER Check for Samples: TLK10034 FEATURES 1 • • • • • • • • • • • • • Quad Channel Multi-Rate Transceiver Supports 10GBASE-KR, XAUI, and 1GBASEKX Ethernet Standards Supports all CPRI and OBSAI Data Rates up to 10 Gbps Supports Multi-Rate SERDES Operation with up to 10.3125Gbps Data Rate on the High Speed Side and up to 5Gbps on the Low Speed Side Differential CML I/Os on Both High Speed and Low Speed Sides Interface to Backplanes, Passive and Active Copper Cables, or SFP+ Optical Modules Selectable Reference Clock per Channel with Multiple Output Clock Options Loopback Capability on Both High Speed and Low Speed Sides Supports Data Retime Operation Supports PRBS, CRPAT, CJPAT, High- /Low/Mixed-Frequency Patterns, and KR PseudoRandom Pattern Generation and Verification, Square-Wave Generation Two Power Supplies: 1.0V, and 1.5 or 1.8V Nominal No Power Supply Sequencing Requirements Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane/Cable Reach on Both High Speed • • • • • • • • • • and Low Speed Sides Programmable Transmit Output Swing on Both High Speed and Low Speed Sides Loss of Signal (LOS) Detection Supports 10G-KR Link Training, Forward Error Correction, Auto-Negotiation Jumbo Packet Support JTAG; IEEE 1149.1 /1149.6 Test Interface Industry Standard MDIO Clause 45 and 22 Control Interfaces 65nm Advanced CMOS Technology Industrial Ambient Operating Temperature (–40°C to 85°C) Power Consumption: 825mW per Channel (Nominal) Device Package: 19mm x 19mm, 324-pin PBGA, 1-mm Ball-Pitch APPLICATIONS • • • • • 10GBASE-KR Compliant Backplane Links 10 Gigabit Ethernet Switch, Router, and Network Interface Cards 10 Gigabit Ethernet Blade Servers Proprietary Cable/Backplane Links High-Speed Point- to-Point Transmission Systems XAUI CHANNEL A 10GBASE-KR CHANNEL A XGXS TLK10034 10GBASE-KR CHANNEL B MAC XGXS XGXS 10GBASE-KR CHANNEL C XAUI CHANNEL C BACKPLANE XAUI CHANNEL B 10GBASE-KR CHANNEL D XGXS XAUI CHANNEL D MDC MDIO 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TLK10034 SLLSEC7 – AUGUST 2012 www.ti.com DESCRIPTION The TLK10034 is a quad-channel multi-rate transceiver intended for use in high-speed bi-directional point-topoint data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode. While operating in the 10GBASE-KR mode, the TLK10034 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10034 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications. While operating in the General Purpose SERDES mode, the TLK10034 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10034 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5Gbps to 5Gbps and the high speed side data rate can range from 1Gbps to 10Gbps. 1:1 retime mode is also supported but limited to 1Gbps to 5Gbps rates. The TLK10034 also supports 1G-KX (1.25Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioning is used, data rates up to 3.125 Gbps are supported. Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. The TLK10034 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1G-KX modes, allowing for asynchronous clocking. The TLK10034 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes. The TLK10034 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High, Low, Mixed, CRPAT long/short, CJPAT, and KR pseudorandom test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen. The TLK10034 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. In the 10GBASE-KR mode, the lane alignment for each channel is achieved through the standard XAUI lane alignment scheme. In the General Purpose SERDES mode the low speed side lane alignment for each channel is achieved through a proprietary lane alignment scheme. The upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved. The four TLK10034 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios. The low speed side of the TLK10034 is ideal for interfacing with an FPGA or ASIC capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The TLK10034 supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems. 2 Copyright © 2012, Texas Instruments Incorporated TLK10034 www.ti.com SLLSEC7 – AUGUST 2012 PHYSICAL CHARACTERISTICS Block Diagram Various interfaces of the TLK10034 device are shown in Figure 1 for Channel A. The implementation of all four channels is identical. The block diagrams for the transmit and receive data paths are shown in Figure 2. This low-power transceiver consists of two serializer/deserializer (SERDES) blocks, one on the low speed side and the other on the high speed side. The core logic block that lies between the two SERDES blocks carries out all the logic functions including channel synchronization, lane alignment, 8B/10B and 64B/66B encoding/decoding, as well as test pattern generation and verification. The TLK10034 provides a management data input/output (MDIO) interface as well as a JTAG interface for device configuration, control, and monitoring. Detailed description of the TLK10034 pin functions is provided in TLK10034 data manual. INA 0P /N INA 1P /N INA 2P /N OU TA1 P/N OU TA2 P/N HSTXAP/N DATA PATH (Channel A) INA 3P /N OU TA0 P/N High Speed Outputs Low Speed Inputs Low Speed Outputs High Speed Inputs HSRXAP/N OU TA3 P/N LS 0_CLK OUT P/N LS 1_ CLK OUT P/N REF C LK0 P/N HSRXA_CLKOUTP/N HST X0_ CLK OUTP/N CLOCKS HST X1_ CLK OUTP/N REF C LK1 P/N REFCLK _SEL PRTAD[ 4:0] LO SA MDIO LS_OK_OUT_A MDC MDIO LS_OK_IN_A CONTROL, STATUS, TEST ST MODE_SEL PDTRX_N TDO RESET_N TMS TESTEN JTAG PRBSEN TRST_N TCK PRBS_PASS TDI GPI[2:0] Figure 1. TLK10034 Interfaces Copyright © 2012, Texas Instruments Incorporated 3 TLK10034 SLLSEC7 – AUGUST 2012 www.ti.com Figure 2. A Simplified One Channel Block Diagram of the TLK10034 Data Paths 4 Copyright © 2012, Texas Instruments Incorporated Request Complete Data Manual at: [email protected] PACKAGE OPTION ADDENDUM www.ti.com 21-Aug-2012 PACKAGING INFORMATION Orderable Device TLK10034AAJ Status (1) ACTIVE Package Type Package Drawing FCBGA AAJ Pins Package Qty 324 84 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish SNAGCU MSL Peak Temp (3) Samples (Requires Login) Level-4-260C-72 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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