M64898GP PLL Frequency Synthesizer with DC/DC Converter For PC REJ03F0168-0200 Rev.2.00 Jun 14, 2006 Description The M64898GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR /PC. It contains the prescaler with operating up to 1.3 GHz, 4 band drivers and DC/DC converter for Tuning voltage. Features • • • • • • • • • Built-in DC/DC converter for Tuning voltage 4 integrated PNP band drivers (IO = 30 mA, Vsat = 0.2 V Typ.@VCC1 to 10 V) Built-in prescaler with input amplifier (max = 1.3 GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X’tal 4 MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64892/M64893 Automatic switching of tuning step according to the number of data bits (62.5 kHz at 18 bits, 32.25 kHz at 19 bits) Built-in Power on reset system Small package (SSOP) Application PC, TV, VCR tuners Recommended Operating Condition • Supply voltage range VCC1 = 4.5 to 5.5 V VCC2 = VCC1 to 10 V • Rated supply voltage VCC1 = 5 V VCC2 = VCC1 Rev.2.00 Jun 14, 2006 page 1 of 13 M64898GP Block Diagram CNT 15 VCC1 3 VDC 9 Ipk 10 S Q Xin 20 OSC fREF Divider Selector R DIV. 11 SWE Latch fin 1 AMP 2 – 1/8 Latch 15 + 15-bit Programmable Divider 1/32, 1/33 Phase Detector Vreg Charge Pump CP Lock Detector CLK 17 18/19-bit Shift Register Control DATA 18 4 5 BS4 6 BS3 Rev.2.00 Jun 14, 2006 page 2 of 13 7 BS2 8 BS1 OS TEST 14 Vin Latch 16 LD/ftest Power-on Reset 4 VCC2 13 Vtu 5 ENA 19 Bias/Band Switch Driver 12 +B 2 GND M64898GP Pin Arrangement M64898GP fin 1 20 Xin GND 2 19 ENA VCC1 3 18 DATA VCC2 4 17 CLK BS4 5 16 LD/ftest BS3 6 15 CONT BS2 7 14 Vin BS1 8 13 Vtu VDC 9 12 +B Ipk 10 11 SWE (Top view) Outline: PLSP0020JA-A (20P2E-A) Rev.2.00 Jun 14, 2006 page 3 of 13 M64898GP Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol fin GND VCC1 VCC2 BS4 BS3 BS2 BS1 VDC lpk 11 12 13 14 SWE +B Vtu Vin Switching output Power supply voltage Tuning output Filter input (charge pump output) 15 LD/ftest Lock detect/Test port Lock detector output. When loop of phase locked loop locked it, it rise with “H” level in “L” level or unlock. In control byte data input, the programmable freq. divider output and reference freq. output is selected by the test mode. 16 CONT fREF Switch 17 18 19 CLOCK DATA ENABLE Clock input Data input Enable input Set up reference frequency divider ratio. In “L” level, set it up in 1/640 (19 Bit) in setting “opening” in 1/1024 (19 Bit) or 1/512 (18 Bit). Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. 20 Xin This is connected to the crystal oscillator. Pin Name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0 V. Power supply voltage terminal. 5.0 V ± 0.5 V Power supply for band switching, VCC1 to 10 V DC/DC power supply voltage Peak current detect DC/DC power supply voltage terminal. 5.0 V ± 0.5V Rev.2.00 Jun 14, 2006 page 4 of 13 PNP open collector method is used. When the band switching data is “H”, the output is ON. When it is “L”, the output is OFF. When potential difference with VDC terminal becomes more than 0.33 V by current limiting detector of DC/DC converter, the listing rises with off. DC/DC converter oscillator output. Power supply voltage for tuning voltage. This supplies the tuning voltage. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fREF), the “source” current state becomes active. If it is behind, the “sink” current becomes active. If the phases are the same, the high impedance state becomes active. This normally at a “L”. When this is at “H”, data and clock signals are received. Data is read into the latch when the enable signal after the 18th signal of the clock signal falls or when the 19th pulse of the clock signal falls. 4.0 MHz crystal oscillator connected. M64898GP Absolute Maximum Ratings (Ta = −20°C to +75°C, unless otherwise noted) Item Supply voltage 1 Supply voltage 2 Input voltage Output voltage Symbol VCC1 VCC2 VI VO Ratings 6.0 10.8 6.0 6.0 10.8 Unit V V V V V Voltage applied when the band output is OFF Band output current VBSOFF ON the time when the band output is ON Power dissipation Operating temperature Storage temperature tBSON 40.0 10 mA s Pd Topr Tstg 255 −20 to +75 −40 to +125 mW °C °C IBSON Condition Pin 3 Pin 4 Not to exceed VCC1 fREF output per 1 band output circuit 40mA per 1 band output circuit 3 circuits are pn at same time. Ta=75°C Recommended Operation Conditions (Ta = −20°C to +75°C, unless otherwise noted) Item Supply voltage 1 Supply voltage 2 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Symbol VCC1 VCC2 fopr1 fopr2 IBDL Rev.2.00 Jun 14, 2006 page 5 of 13 Ratings 4.5 to 5.5 VCC1 to 10.0 4.0 80 to 1300 0 to 30 Unit V V V MHz mA Conditions Pin 3 Pin 4 Crystal oscillation circuit Normally 1 circuit is on. 2 circuit on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. M64898GP Electrical Characteristics (Ta = −20°C to +75°C, unless otherwise noted, VCC1 = 5.0 V, VCC2 = 9.0 V) Item Limits Typ. Max. Unit 11.6 — — — — — −50 −6 −18 — 0.3 11.8 — VCC1 + 0.3 0.4 1.5 10 −80 −10 −30 — 0.5 — −10 V V V µA µA µA µA V V V µA 13 30.5 — — V VCC2 = 9V, Band SW is OFF VO = 0V +B = 31V VtoL 13 — 0.2 0.4 V +B = 31V Icpo 14 — 270 370 µA VCC1 = 5.0V, VO = 2.5V IcpLK ICC1 ICC2A 14 3 4 4 — — — — — 20 — 4.0 50 30 0.3 6.0 nA mA mA mA VCC1 = 5.0V, VO = 2.5V VCC1 = 5.5V VCC2 = 9V VCC2 = 9V 4 — 34.0 36.0 Output current 30 ICC2C mA DC/DC Converter Supply current (action) ICCdc 9 — 1.3 3.0 Output voltage Vdo 12 28 31 35 OSC frequency fOSC 11 — 571 — Current limit detect voltage Vipk 10 — 330 — Note: The typical values are at VCC1 = 5.0 V, VCC2 = 9.0 V, Ta = +25°C. mA VCC2 = 9V, IO = −30mA mA V kHz mV VCC1 = 5.5V VCC1 = 5.5V VCC1 = 5.5V VCC1 = 5.5V Input termina ls Lock output Band SW Tuning output Charge pump Symbol Test Pin “H” input voltage “L” input voltage “L” input voltage “H” input current “L” input current “L” input current “L” input current VIH VIL1 VIL2 IIH IIL1 IIL2 IIL3 IOlk1 17 to 19 15 17 to 19 17 to 19 15 17, 19 18 16 16 5 to 8 5 to 8 “H” input current VOH “L” input current Output voltage VOL VBS Leak current Output voltage “H” VtoH Output voltage “L” “H” output current Leak current Supply current 1 4 circus OFF Supply current 1 circus ON, 2 Output open ICC2B Rev.2.00 Jun 14, 2006 page 6 of 13 Min. 3.0 — — — — — — 5.0 Test Conditions VCC1 = 5.5V, Vi = 4.0V VCC1 = 5.5V, Vi = 0V VCC1 = 5.5V, Vi = 0.5V VCC1 = 5.5V, Vi = 0.5V VCC1 = 5.5V VCC1 = 5.5V VCC2 = 9V, IO = −30mA M64898GP Switching Characteristics (Ta = −20°C to +75°C, unless otherwise noted, VCC1 = 5.0 V, VCC2 = 9.0 V) Min. Limits Typ. Max. Unit Prescaler operating frequency fopr 1 80 — 1300 MHz VCC1 = 4.5 to 5.5V Vin = Vinmin to Vinmax Operating input voltage Vin 1 Enable data interval time Rise time tINT 4 4 4 — — — — — — VCC1 = 4.5 to 5.5V tPWC tSU (D) tH (D) tSU (E) tH (E) — — — — — — — — — dBm Clock pulse width Data setup time Data hold time Enable setup time Enable hold time −24 −27 −15 1 2 1 3 3 1 µs µs µs µs µs µs 950 to 1300MHz VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V tR 17, 18, 19 — — 1 µs VCC1 = 4.5 to 5.5V Fall time tF — — 1 µs VCC1 = 4.5 to 5.5V Next enable prohibit time Next clock prohibit time tBT 17, 18, 19 19 5 — — µs VCC1 = 4.5 to 5.5V tBCL 17, 19 5 — — µs VCC1 = 4.5 to 5.5V Item Symbol Rev.2.00 Jun 14, 2006 page 7 of 13 Test Pin 17 18 18 18 18 19, 18 Test Conditions 80 to 100MHz 100 to 950MHz M64898GP Method of Setting Data The programmable divider ratio uses 15 bits. Setting up the band switching output uses 4 bits. The test mode data uses 8 bits. The total bits used are 27 bits. Data is read in when the enable signal is “H” and the clock signal falls. The band switching data is read in at the 4th pulse of the clock signal. The programmable counter data is read into the latch by the fall of the enable signal after the 18th pulse of the clock signal or the fall of the 19th pulse of the clock signal. When the enable signal goes to “L” before the 18th pulse of the enable signal, only the band SW data is updated and other data is ignored. Automatic judgment facility comes being it, and, as for Shift resister, CONT terminal rises by 18/19 bits at the time of “L”. At the time of data of 18 bits, M9 bit of Programmable divider is done reset of, and it is established in reference frequency divider ratio is established 1/512. At the time of 19 bits, reference frequency divider ratio is established in 1/1024. When reference frequency divider ratio was established in 1/640 by 19 bits at the time if “opening” CONT terminal, and it became “L” before 19 pulses enable signal, only band SW data are renewed, and other data are ignored. 1. Transfer of the 18th bit data (CONT terminal is “L”) Data is latched by the fall of the enable signal after the 18th clock signal. At this time, the divider of the 1/512 of the reference frequency is used. ENA 28 27 26 25 24 23 22 21 20 24 23 22 21 20 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0 BS4 BS3 BS2 BS1 DATA CLK Band Switch Data M Counter Divider Ratio Setting S Counter Divider Ratio Setting Read Into Latch Read Into Latch 2. Transfer of the 19th bit data (CONT terminal is “L” or “open”) The data is latched at the 19th pulse of the clock signal. Reference frequency divider ratio is established in 1/1024 in case of “L” CONT terminal at this time. Reference frequency divider ratio is established in 1/640 in case of “opening” CONT terminal. Invalid the clock signal after 19th pulse. Note: When CONT terminal is “L”, to change reference frequency, set up as ENA in “L” after 19th pulse of clock signal by all means. ENA BS4 BS3 BS2 BS1 DATA 29 28 27 26 25 24 23 22 21 20 24 23 22 21 20 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0 CLK Band Switch Data M Counter Divider Ratio Setting Read Into Latch Rev.2.00 Jun 14, 2006 page 8 of 13 S Counter Divider Ratio Setting Read Into Latch M64898GP How to Set The Dividing Ratio of The Programmable Divider 1. Transfer of the 18th bit data (CONT terminal is “L”) Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N = 8 • (32 M + S) M: 9 bit main counter divider S: 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32 • M • 511 0 • S • 31 Therefore, the range of divider N is 8,192 to 131,064. The tuning frequency fVCO is given in the following equations. fVCO = fREF • N = 7.8125 • 8 • (32 M + S) = 62.5 • (32 M + S) (kHz) Therefore, the tuning frequency range is 64 MHz to 1023.9375 MHz. 2. Transfer of the 19th bit data (CONT terminal is “L”) Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N = 8 • (32 M + S) M: 10 bit main counter divider S: 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32 • M • 1023 0 • S • 31 Therefore, the range of divider N is 8,192 to 262,136. The tuning frequency fVCO is given in the following equations. fVCO = fREF • N = 3.90625 • 8 • (32 M + S) = 31.25 • (32 M + S) (kHz) Therefore, the tuning frequency range is 32 MHz to 1023.96875 MHz. 3. Transfer of the 19th data (CONT terminal is “open”) Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N = 8 • (32M + S) M: 10 bit main counter divider S: 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32 • M • 1023 0 • S • 31 Therefore, the range of divider N is 8,192 to 262,136. The tuning frequency fVCO is given in the following equations. fVCO = fREF • N = 6.25 • 8 • (32 M + S) = 50.0 • (32 M + S) (kHz) But, the tuning frequency range is 51.2 MHz to 1300 MHz from the maximum prescaler operating frequency. Rev.2.00 Jun 14, 2006 page 9 of 13 M64898GP Test Mode Data Set Up Method The data for the test mode uses 20 to 27 bits. Data is latched when the 27th clock signal falls. 1. When transferring 3-wire 27 bit data ENA 1 19 20 CLK M Counter Divider Ratio Setting Band Switch Data S Counter Divider Ratio Setting X X T2 T1 T0 RSa RSb OS Test Data Setting Read Into Latch 2. Test Mode Bit Set Up X : Random, 0 or 1 normal “0” T0, T1 & T2 : Set up test modes RSa, Rsa : Set the frequency divider of the reference frequency OS : Set up the tuning amplifier Setting Up for The Test mode T2 0 T1 0 T0 X Charge Pump Normal operation Pin 12 Condition LD Mode Normal operation 0 1 1 1 1 1 1 1 0 0 X 0 1 0 1 High impedance Sink Source High impedance High impedance LD LD LD fREF f1/N Test mode Test mode Test mode Test mode Test mode RSa, RSb: Set Up for The Reference Frequency Divider Ratio RSa 1 0 X RSb 1 1 0 Divider Ratio 1/512 1/1024 1/640 Tuning Voltage Output ON OFF Mode Normal Test OS: Set Up The Tuning Amplifier OS 0 1 Power On Reset Operation (Initial state the power is turned ON) BS4 to BS1 Charge pump Tuning amplifier Charge pump current Frequency divider ratio Lock detect : OFF : High impedance : OFF : 270 µA : 1/1024 :H Charge pump current is replaced by 70 µA when locks it by automatic change facility. Rev.2.00 Jun 14, 2006 page 10 of 13 M64898GP Timing Diagram tr tf 90% 1.5 V ENABLE 10% 10% tINT DATA VIH 90% tINT 90% 1.5 V 10% CLOCK 1.5 V tPWC tSU(D) tf VIH 10% tr tH(D) VIL tf tH(E) tSU(E) Crystal Oscillator Connection Diagram 20 18 pF 4 MHz Rev.2.00 Jun 14, 2006 page 11 of 13 VIL 90% 10% VIL VIH 90% 10% tr 90% tBT Crystal oscillator characteristics Actual resistance: less than 300 Ω Load capacitance: 20 pF tBCL M64898GP Application Example Built-in PLL Tuner IF AGC IF AGC VHF 4-Band Tuner UHF +B BS4 BS3 BS2 AFT BS1 Lo VT 33 H + 0.01 56 k 0.1 43 100 p VCC1 to 9 V 1000 p M64898GP 4 5 6 7 8 56 k 680 p 0.1 14 1 22 k 68 H 13 9 10 11 Bias Circuit AMP Band Driver Q S 1/8 Charge Pump Power-on Reset 4 1/32 1/33 Phase Detector + – Vreg 3 +5 V R Main Counter Selector 2 5 18/19-bit Shift Resister Data Latch Lock Detector + VCC1 =5V 19 17 18 51 k OSC Divider 9/10 Swallow Counter 12 1.5 15 18 p 20 4 MHz 16 1000 p DATA CLK MCU Note: Filter constant is for reference. Add a capacitor to stabilize the filter circuit. Rev.2.00 Jun 14, 2006 page 12 of 13 ENA LD/ftest Units R: Ω C: F M64898GP Package Dimensions JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JA-A MASS[Typ.] 0.08g 11 *1 E 20 HE Previous Code 20P2E-A F 1 Index mark NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 10 c A2 A1 *2 D A L Reference Dimension in Millimeters Symbol *3 e y bp Detail F D E A2 A A1 bp c HE e y L Rev.2.00 Jun 14, 2006 page 13 of 13 Min 6.4 4.3 Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0 0.1 0.2 0.17 0.22 0.32 0.13 0.15 0.2 0° 10° 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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