RENESAS M64893AGP

M64893AGP
SERIAL INPUT PLL FREQUENCY SYNTHES IZER FOR TV/VCR
REJ03F0008-0100Z
Rev.1.00
Jul.25.2003
Description
The M64093FP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using BiCMOS process. It contains prescaler with operating up to. 1.0 GHz, 4 band driver and a tuning amplifier for direct
tuning.
Features
•
•
•
•
•
•
•
•
•
•
4 integrated PNP band switching drivers (lo = 40 mA, Vsat = 0.2 V typ@Vcc1 to 13.2 V)
Built-in tuning amplifier for direct tuning (33 V)
Low power dissipation (lcc = 24 mA, at Vcc = 5 V)
Built-in prescaler with input amplifier (Fmax = 1.0 GHz)
PLL lock/unlock status display output (built-in pull-up resistor)
Reference driver (Division radio 1/640)
Serial data input (3 wire Bus)
Built-in power on reset
16pin –plastic mold mini flat package (16pin SSOP)
Without protection diode at CLK,DATA,ENA
Application
• TV,VCR tuners
Block Diagram
X in
ENA DATA
16
15
CLK
LD
Vcc3 Vtu
13
12
11
14
10
Vin
9
19-BIT SHIFT
REGISTER
Vc c 1
OSC
DIVIDER
10
LOCK
DETECTOR
10-BIT MAIN
COUNTER
1/32,1/33
5
5-BIT SWALLOW
COUNTER
CHARGE
PUMP
PHASE
DETECTOR
4
P.O.
RESET
1/8
BAND DRIVER
BIAS
1
2
3
4
5
6
7
8
fin
GND
Vcc1
Vcc2
BS4
BS3
BS2
BS1
Rev.1.00, Jul.25.2003, page 1 of 11
M64893AGP
Pin Description
Symbol
Pin No.
Pin name
Function
fin
GND
Vcc1
Vcc2
BS4
BS3
BS2
BS1
Vin
1
2
3
4
5
6
7
8
9
Prescaler input
GND
Power supply voltage 1
Power supply voltage 2
Band switching outputs
Input for the VCO frequency.
Ground to 0 V
Power supply voltage terminal. 5.0 V+/-0.5 V
Power supply voltage terminal. Vcc1 to 13.2 V
PNP open collector method is used.
When the band switching data is “H”, the output is “ON”.
When it is “L”, the output is “OFF”.
Filter input
(Charge pump output)
This is the output terminal for the LPF input and charge pump
output. When the phase of the programmable divider output (f1/N)
is lead compared to the reference frequency (fref), the “source”
current state becomes active. If it is lag, the same, the high
impedance state be comes active.
Vtu
Vcc3
LD
10
11
12
Tuning output
Power supply voltage 3
Lock detect output
CLOCK
DATA
13
14
Clock input
Data input
This supplies the tuning voltage.
Power supply voltage for tuning voltage 28 to 35 V
When 19 bit data is input, lock detector is output.
When 27 bit data is input, lock detector is output.
the programmable divider output and reference divider
output is selected by the test mode.
Data is read into the shift register when the clock signal falls.
Input for band SW and programmable freg. divider set falls.
ENABLE
15
Enable input
This is normally at an “L”. When this is at “H”, data and clock
signals are received. Data is read into the latch when the 19th
pulse of the clock signal falls.
X in
16
This is connected to the
Crystal oscillator.
4.0MHz crystal oscillator connected.
Pin Arrangement
PRESCALER INPUT
GND
fin
1
16
Xin
CRYSTAL OSCILLATOR
G ND
2
15
EN A
ENABLE INPUT
SUPPLY VOLTAGE 1
Vcc1
3
14
DATA
DATAINPUT
SUPPLY VOLTAGE 2
Vcc
4
13
CLK
LOCK INPUT
BS4
5
12
LD
LOCK OUTPUT
BS
6
11
Vcc2
SUPPLY VOLTAGE 3
BS
7
10
Vtu
TUNING OUTPUT
BS1
8
9
Vin
FILTER INPUT
BAND SWITCHING
OUTPUTS
OUTLINE 16P2Z
Rev.1.00, Jul.25.2003, page 2 of 11
M64893AGP
Method of Setting Data
The programmable divider uses 15bits Setting up the band switching output uses 4bits.
The test mode data use s 8bits. The total bits used is 27bits. Data is read in when the enable signal is “H” and the clock
signal falls.
The band switching data is read in the 4th pulse of the clock signal. The programmable driver data is read into the fall
of the 19th pulse of the clock signal .When the enable signal goes to “L” Before the 19th pulse of the enable signal,
only the band switching data is updated and other data is ignored.
ENA
DATA
BS4 BS3 BS2 BS1 29
M9
28
M8
27
M7
26
M6
25 24
M5 M4
23
M3
22
M2
21 20
M1 M0
24 23 22 21 20
S4 S3 S2 S1 S0
CLK
BAND
SWITCHING
DATA
MAIN COUNTER DIVISION
RATIO SETTING
READ INTO LATCH
SWALLOW COUNTER
DIVISION RATIO SETTING
READ INTO LATCH
How to Set The Dividing Radio of The Programmable Divider
Total division N is given by the following from formulas in addition to the prescaler used the previous stage.
N = 8*(32 M+S)
M: 10 bit main counter division
S: 5 bit swallow counter division
The M and S counters are binary the possible ranges of division are follows.
32 ≤ M ≤ 1023
0 ≤ S ≤ 31
Therefore, the rage of division N is 8,192 to 262, 136.
The tuning frequency fvco is given in the following equations.
fvco = fref*N
= 6.25*8*(32M+S)
= 50.0*8*(32M+S)
[KHz]
Therefore, the tuning frequency range is from 51.2 MHz to 1000 MHz
Rev.1.00, Jul.25.2003, page 3 of 11
M64893AGP
Test Mode Data Set Up Method
The data for the test mode uses from 20 to 27 bits. Data is latched when the 27th clock signal falls.
(1) When transferring 3-wire 27 bit data
ENA
1
19 20
27
CLK
BAND
SWITCHING
DATA
MAIN COUNTER DIVISION
RATIO SETTING
X
SWALLOW
COUNTER
DIVISION RATIO
SETTING
CP T 2 T 1
T O RSa RSbOS
TEST DATA SETTING
READ INTO LATCH
(2) Test Mode Bit Set Up
X
:Random, 0 or 1.normal "0"
CP
:Set up the charge pump current value
T0, T1,&T2
:Set up test modes
RSa, Rsa
:Set the frequency division of the reference frequency
OS
:Set up the tuning amplifier
Setting Up the Charge Pump Current of The Phase Comparator
CP
Charge pump current
Mode
0
1
50 µA
250 µA
Normal
Test
Setting Up The Test Mode
T2
T1
T0
Charge pump
12 pin output
Mode
0
0
X
Normal operation
LD
Test
0
1
X
High impedance
LD
Test
1
1
0
Sink
LD
Test
1
1
1
Source
LD
Test
1
0
0
High impedance
fref
Test
1
0
1
High impedance
f1/N
Test
Rev.1.00, Jul.25.2003, page 4 of 11
M64893AGP
Set Up for The Reference Frequency Division Radio
RSa
RSb
Division radio
0
1
X
1
1
0
1/512
1/1024
1/640
OS
Tuning voltage output
mode
0
1
ON
OFF
Normal
Test
Set Up The Tuning Amplifier
Power On Reset Operation (Initial State The Power is Turned ON)
•
•
•
•
•
•
BS4 to BS1
Charge pump
Tuning amplifier
Charge pump current
Frequency division radio
Lock output
:OFF
:high impedance
:OFF
:250 µΑ
:1/640
:H
Rev.1.00, Jul.25.2003, page 5 of 11
M64893AGP
Timing Diagram
tr
ENABLE
10%
tf
90%
1.5V
90%
tINT
tINT
V IH
10%
tBT
90%
DATA
1.5V
10%
10%
tr
tPWC
tr
tH(D)
tSU(D)
V IL
V IH
10%
tf
V IL
tH(E)
tBCL
tSU(E)
Crystal Oscillator Connection Diagram
16
Crystal oscillator characteristics
Actual resistance : less than300ohm
18pF
4MHz
Rev.1.00, Jul.25.2003, page 6 of 11
V IH
tf
90%
90%
1.5V
10%
CLOCK
90%
V IL
Load capacitance : 20pF
M64893AGP
Absolute Maximum Ratings
(Ta = –20°C to 75°C unless otherwise noted)
Parameter
Symbols
Max.ratings
Units
Conditions
Standby voltage1
Vcc1
6.0
V
Pin3
Standby voltage2
Standby voltage3
Input voltage
Output voltage
Voltage applied when
the band output current is OFF
Vcc2
Vcc3
VI
VBSOFF
IBSON
14.4
36.0
6.0
6.0
14.4
V
V
V
V
V
Pin4
Pin11
Not to exceed Vcc1
Pin 12
Band output current
tBSON
50.0
mA
Per 1 band output circuit
ON the time when the band
output is ON
Pd
10
sec
50 mA per 1 band output circuit
3 cicuits are pn at same time
Power dissipation
Operating temperature
Storage temperature
Topr
Tstg
Tstg
350
–20 to +75
–40 to +125
mW
°C
°C
Ta = 75°C
Recommended Operating Conditions
(Ta = –20°C to 75°Cunless otherwise noted)
Parameter
Standby voltage1
Standby voltage2
Standby voltage3
Operating frequency(1)
Operating frequency(2)
Band output current 5 to 8
Rev.1.00, Jul.25.2003, page 7 of 11
Symbols
Ratings
Units
Vcc1
Vcc2
Vcc3
fopr2
fopr2
IBDL
4.5 to 5.5
5.0 to 3.2
30 to 35
4.0
80 to 100
0 to 40
V
V
V
MHz
MHz
mA
Conditions
Crystal oscillation circuit
Normally 1 circuit is on. 2 circuits on at
the same time is max. It is prohibited to
have 3 or more circuits turned on at the
same time.
M64893AGP
Electrical Characteristics
(Ta = –20°C to 75°Cunless otherwise noted)Vcc1 = 5.0 V, Vcc = 12 V, Vcc3 s= 33 V
Parameters
input terminals
“H” input voltage
“L” input voltage
“H” input voltage
“L” input current
Lock output
“H” output voltage
“L” output voltage
Band SW
output voltage
Leak current
Tuning output
output voltage “H”
output voltage “L”
Charge pump
“H” output current
“L” output current
Leak current
Supply current 1
Supply current 2
4circuits OFF
1 circuits ON,
Output open
Output current 40mA
Supply current 3
Symbol
Test pin
Test conditions
Limits
Unit
Min
Typ
Max
—
—
—
–2
Vcc1+0.3
1.5
10
–10–
V
V
µA
µA
VIH
VIL
IIH
IIL
13 to 15
13 to 15
13 to 15
13 to 15
Vcc1 = 5.5 V, Vi = 4.0 V
Vcc1 = 5.5 V, Vi = 0.4 V
3.0
—
—
—
VOH
VOL
12
12
Vcc1 = 5.5 V
Vcc1 = 5.5 V
5.0
—
—
0.3
—
0.5
V
V
VBS
lOIK1
5 to 8
5 to 8
Vcc2 = 12 V lo = -40 mA
Vcc2 = 12 V Band SW is OFF
11.6
—
11.8
—
—
1
µA
32.5
—
—
0.2
—
0.4
V
V
±250
±50
µA
µA
—
24
±470
±130
±50
Vcc1 = 5.5 V
—
—
—
—
V to H
V to L
10
10
Vcc3 = 33 V
Vcc3 = 33 V
Vcc1 = 5.0 V Vo = 1 V
Vcc1 = 5.0 V Vo = 1 V
Vcc1 = 5.0 V Vo = 2.5 V
IOH
IOL
IcpLK
ICC1
9
9
9
ICC2A
4
Vcc2 = 12 V
—
ICC2B
ICC2C
ICC3C
4
4
Vcc2 = 12 V
Vcc2 = 12 V lo = –40 mA
11
Vcc3 = 33 V Output ON
Note: The typical values are at Vcc1 = 5.0 V, Vcc2 = 12 V, Vcc3 = 33 V, Ta = 25°C
Rev.1.00, Jul.25.2003, page 8 of 11
V
31
nA
mA
—
0.5
mA
—
—
5.0
45.0
6.0
46.0
mA
mA
—
3.6
4.5
mA
M64893AGP
Switching Characteristics
(Ta = –20°C to 75°C, Vcc1 = 5.0 V, Vcc = 12 V, Vcc3 = 33 V, unless otherwise noted)
Parameter
Symbol
Test pin
Test conditions
Limits
Prescaler operating frequency
fopr
Vin
Vcc1 = 4.5 to 5.5 V
Vin = Vinmin to Vinmax
Vcc = 4.5 to 5.5 V
80 to 100 MHz
100 to 200 MHz
200 to 800 MHz
800 to 1000 MHz
1000 to 1300 MHz
80
Operating input voltage
1
1
13
–24
–27
–30
–27
–24
—
—
—
—
—
4
4
4
4
4
Min
Min
Max
Unit
used
1000
MHz
dBm
Clock pulse width
Data setup time
Data hold time
Enable setup time
t PWC
t SU(D)
t H(D)
t SU(E)
14
14
15
15
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
1
2
1
3
—
—
—
—
—
—
—
—
µs
µs
µs
µs
Enable hold time
Enable data interval time
Rise time
Fall time
Next enable prohibit time
Next clock prohibit time
t H(E)
t INT
tr
tf
tbt
tbcl
15,14
13,14,15
13,14,15
15
13.15
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
3
1
—
—
5
5
—
—
—
—
—
—
—
—
1
1
—
—
µs
µs
µs
µs
µs
µs
Rev.1.00, Jul.25.2003, page 9 of 11
M64893AGP
Application Example
BUILT-IN PLL TUNER
+5V
+
10
-
1000pF
5 to 12 V
M64893AGP
3
18
5
Vcc2
SW
+B
4
47k
BS4
BS3
11
12
BS4
5
47k
BS2
BS3
IF
13
BS2
BS1
14
BS1
8
M54938
MCU
1000pF
fIN
14
GND
17
3
DATA
4
CLK
15
2
EN
10
Lo
16
2000pF
1000 pF
13
2000pF
IF
7
47k
TEST
4-BAND
T UNER
6
47k
1
UHF VHF
15
2000pF
12
20
LD
/f 1/N
XIN
6
+5V
16
X OUT
7
18pF
9
10
9
51K
AGC
VT
15K
PD
AGC
1500pF
56K
56K
AFT
2200pF
*
100pF
GND
8
Note) Filter constant is for reference.
*Touch a capacitance because
ilter circuit is instability.
11
4MHz
+33V
BT
Unit Resisrance: Ω
Rev.1.00, Jul.25.2003, page 10 of 11
HE
G
Z1
e
EIAJ Package Code
SSOP16-P-225-0.65
E
Rev.1.00, Jul.25.2003, page 11 of 11
1
16
z
D
Detail G
y
8
9
b
JEDEC Code
–
MMP
x
F
M
A
Weight(g)
0.08
x
L1
Detail F
A2
c
A1
Lead Material
Cu Alloy
e1
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
x
y
Symbol
b2
e1
I2
b2
Dimension in Millimeters
Min
Nom
Max
–
–
1.9
0.05
–
–
–
–
1.5
0.17
0.32
0.22
0.2
0.15
0.13
5.0
5.2
4.8
4.4
4.6
4.2
0.65
–
–
6.2
6.5
5.9
0.4
0.6
0.2
0.9
–
–
–
–
0.225
0.375
–
–
–
0.13
–
0.1
–
–
0°
–
10°
–
0.35
–
–
5.72
–
–
–
1.27
Recommended Mount Pad
e
Plastic 16pin 225mil SSOP
I2
16P2Z-A
M64893AGP
Package Dimensions
L
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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