Advance Information
LMX2322 PLLatinumTM
2.0 GHz Frequency Synthesizer
for RF Personal Communications
General Description
Features
The LMX2322 is a high performance frequency synthesizer with
integrated 32/33 dual modulus prescaler designed for RF operation
up to 2.0 GHz. Using a proprietary digital phase locked loop
technique, the LMX2322’s linear phase detector characteristics
can generate very stable, low noise control signals for UHF and
VHF voltage controlled oscillators.
RF operation up to 2.0 GHz
2.7 V to 3.9 V operation
Serial data is transferred into the LMX2322 via a three-line
TM
MICROWIRE interface (Data, LE, Clock). Supply voltage range
is from 2.7 V to 3.9 V. The LMX2322 features very low current
consumption, typically 3.5 mA at 3.75V.
The charge pump
provides 4mA output current.
The LMX2322 is manufactured using National’s ABiC V BiCMOS
process and is packaged in a 16 pin TSSOP and a 16 pin Chip
Scale Package (CSP).
Low current consumption: Icc = 3.5 mA (typ) at Vcc = 3.75 V
Dual modulus prescaler: 32/33
Internal balanced, low leakage charge pump
Applications
Cellular telephone systems (GSM, NADC, CDMA, PDC, PHS)
Personal wireless communications (DCS-1800, DECT, CT-1+)
Wireless local area networks (WLANs)
Other wireless communication systems
Functional Block Diagram
OSCin
OSC
18-Bit
Microwire
Interface
CLOCK
LE
DATA
fin
10-Bit
R Counter
Prescaler
32/33
Phase
Comp
Charge
Pump
CPo
15-Bit
N Counter
fin
9/24/1998
Rev 1.6
1
LMX2322
Advance Information
Connection Diagram
OSCin
1
16
NC
NC
2
15
NC
Vp
3
14
NC
Vcc
4
13
NC
CPo
5
12
CE
GND
6
11
LE
Xfin
7
10
Data
fin
8
9
Clock
NC
OSCin
NC
16
15
14
13
NC
2
12
NC
CPo
3
11
CE
GND
4
10
LE
Xfin
5
9
Data
Vp
1
Vcc
TSSOP 16
6
7
fin
NC
8
Clock
CSP 16 (TOP VIEW)
Pin Description
Pin
No.
TSSOP
16
Pin
Name
I/O
Description
I
Oscillator input. A CMOS inverting gate input. The input has a
Vcc/2 input threshold and can be driven from an external CMOS
or TTL logic gate. May also be used as a buffer for an externally
provided reference oscillator.
Power supply for charge pump. Must be > Vcc
Power supply voltage input. Input may range from 2.7V to 3.9V.
Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
Internal charge pump output. For connection to a loop filter for
driving the voltage control input of an external oscillator.
Ground.
RF prescaler complimentary input. In single-ended mode, a
bypass capacitor should be placed as close as possible to this
pin and be connected directly to the ground plane. The LMX2322
can be driven differentially when a bypass capacitor is omitted.
RF prescaler input.
Small signal input from the voltage
controlled oscillator.
High impedance CMOS Clock input. Data is clocked in on the
rising edge, into the various counters and registers.
Binary serial data input. Data entered MSB first. LSB is control
bit. High impedance CMOS input.
Load enable input. When Load Enable transitions HIGH, data is
loaded into either the N or R register (control bit dependent). See
timing diagram.
PLL Enable.
A LOW on CE powers down the device
asynchronously and TRI-STATEs the charge pump output.
No Connect
CSP 16
1
15
OSCin
3
1
Vp
4
2
Vcc
5
3
CPo
O
6
4
GND
I
7
5
Xfin
8
6
fin
I
9
8
Clock
I
10
9
Data
I
11
10
LE
12
11
CE
2,13,14,
15, 16
7,12,13
14, 16
NC
-
I
I
9/24/1998
Rev 1.6
2
LMX2322
Advance Information
Absolute Maximum Ratings (Note 1)
Value
Parameter
Symbol
Min
Power Supply Voltage
Vcc
Power Supply for Charge Pump
Vp
Voltage on any pin with GND=0 volts
Max
Unit
-0.3
4.3
V
Vcc
4.3
V
Vi
-0.3
Vcc+0.5
V
Storage Temperature Range
TS
- 65
+ 150
oC
Lead Temp. (solder 4 sec)
TL
+ 260
o
ESD - whole body model (Note 2)
Typ
2
C
kV
Recommended Operating Conditions (Note 1)
Value
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
Parameter
Vcc
2.7
3.75
3.9
V
Power Supply for Charge Pump
Vp
Vcc
3.9
V
Operating Temperature
TA
- 40
+ 85
oC
Notes:
1. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Conditions
indicate conditions for which the device is intended to be functional. For guaranteed specifications and test conditions,
see the Electrical Characteristics.
2. This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device
should on be done on ESD protected workstations.
9/24/1998
Rev 1.6
3
LMX2322
Advance Information
Electrical Characteristics Vcc = 3.75, Vp = 3.75V ; -40oC <TA< 85oC
Symbol
Icc
Parameter
Power Supply Current
Condition
except as specified
Min
Typ
Vcc = 3.75 V
Icc
Vcc=2.7V to 3.9V
Icc-PWDN
Vcc = 3.9V (Note 1)
10
Vcc = 3.9V (Note 2)
fin
RF Operating Frequency
fosc
Oscillator Frequency
fφ
Phase Detector Frequency
Vfin
Input Sensitivity
Zin
Input Impedance
Vosc
Oscillator Sensitivity
Phase Noise (Note 4)
0.7
5
0.2
45
ICPo-sink vs.
ICPo-source
ICPo vs. T
tCS
10
MHz
450
mVRMS
Vpp
-86
Note 6
dBc/Hz
Fin=900MHz, Vosc>=0.8Vpp
Ω
Ω
Fin=900MHz, Vosc>=0.4Vpp
-82
Note 6
Fin=1800MHz, Vosc>=0.8Vpp
-82
Note 6
-80
Note 6
2.5
V
0.4
V
VIH = Vcc = 3.9 V
-1.0
1.0
µA
VIL = 0, Vcc = 3.9 V
-1.0
1.0
µA
100
uA
VIH = Vcc = 3.9 V
-100
VCPo = Vp/2
0.5 < VCPo < Vp - 0.5
T= 25o C
0.5 < VCPo < Vp - 0.5
T = 25o C
VCPo = Vp/2
T = 25o C
VCPo = Vp/2
-40o C < T < +85o C
uA
-4.0
VCPo = Vp/2
(Note 4)
MHz
1.2
VIL = 0, Vcc = 3.9 V
Charge Pump Output Current
magnitude variation vs. Voltage
Charge Pump Output Current
Sink vs. Source Mismatch
Charge Pump Output Current
Magnitude Variation vs. Temperature
40
0.8
High-level Input Current (Clock, Data,
Load Enable)
Low-level Input Current (Clock, Data,
Load Enable)
Oscillator Input Current
ICPo vs
VCPo
GHz
0.4
IIH
Charge Pump Tri-State Current
µA
2.0
OSCin
(Note 5)
ICPo-Tri
300
150
Low-level Input Voltage
ICPo-sink
µA
360
VIL
Charge Pump Output Current
mA
20
100
(Note 5)
IIL
7.0
130
Fin=1800MHz, Vosc>=0.4Vpp
ICPo-source
mA
f=1900MHz (Note 3)
High-level Input Voltage
IIH
13
Unit
Vcc = 2.7 to 3.9 V
Balanced input
f=900MHz (Note 3)
VIH
IIL
Max
3.5
mA
4.0
-2.5
0.1
mA
2.5
nA
10
%
5
%
8
%
Data to Clock Set Up Time
See Data Input Timing
50
ns
Data to Clock Hold Time
See Data Input Timing
10
ns
tCWH
Clock Pulse Width High
See Data Input Timing
50
ns
tCWL
Clock Pulse Width Low
See Data Input Timing
50
ns
tCH
tES
Clock to Enable Set Up Time
See Data Input Timing
50
ns
tEW
Enable Pulse Width
See Data Input Timing
50
ns
Note 1: This Icc-PWDN represents CLK, DATA, LE and CE being tied to either higher than 0.8Vcc or lower than 0.2Vcc.
Note 2: This Icc-PWDN represents a software power down condition of CE = VIH = 2.5V while LE, CLK and DATA = VIL = 0.4V. Worst case Icc-PWDN of 300µA
occurs when CE, LE, CLK and DATA are all held at VIH = 2.5V (4x75µA).
Note 3: Balanced input, | Z | = | R - jXc |
Note 4: Phase noise is measured 1kHz off from the carrier frequency. Comparison frequency is 200kHz. OSCin frequency is 13MHz.
Note 5: except fin and OSCin
Note 6: Typical values are determined from measurements on the reference evaluation boards. A 3dB (3 sigma) degradation is estimated from statistical
distribution in manufacturing. Units will NOT be tested in production.
9/24/1998
Rev 1.6
4
LMX2322
Advance Information
Charge Pump Current Specification Definitions
I2 I1
Current (mA)
I3
I4
I5
VOLTAGE
OFFSET
∆V
∆V
I6
0
∆V
Vp -∆ V
Vp/2
Do Voltage
I1 = CP sink current at VCPo = Vp - ∆V
I4 = CP source current at VCPo = Vp-∆V
I2 = CP sink current at VCPo = Vp/2
I5 = CP source current at VCPo = Vp/2
I3 = CP sink current at VCPo = ∆V
I6 = CP source current at VCPo = ∆V
Vp
∆V = Voltage offset from positive and negative rails. Dependant on VCO tuning range relative to Vcc and ground.
Typical values are between 0.5V and 1.0V
1. ICPo
vs
VCPo =
Charge Pump Output Current magnitude variation vs. Voltage =
[ 1/2 * {|I1| - |I3| ]} / [ 1/2 * { |I1| + |I3|} ] *100%
2. ICPo-sink vs. ICPo-source
=
and
[ 1/2 * {|I4| - |I6|} ] / [ 1/2 * { |I4| + |I6|} ] *100%
Charge Pump Output Current Sink vs. Source Mismatch =
[ |I2| - |I5| ] / [ 1/2 * { |I2| + |I5| } ] * 100%
3. ICPo
vs
TA =
Charge Pump Output Current magnitude variation vs. Temperature =
[ |I2 @ temp| - |I2 @ 25° C| ] / | I2 @ 25° C| * 100%
and
[ |I5 @ temp| - | I5 @ 25° C| ] / |I5 @ 25° C| * 100%
9/24/1998
Rev 1.6
5
LMX2322
1.0
Advance Information
Functional Description
The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a
frequency synthesizer such as the National Semiconductor LMX2322, a voltage controlled oscillator (VCO), and
a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, as well
as programmable reference [R] and feedback [N] frequency dividers. The VCO frequency is established by
dividing the crystal reference signal down via the R counter to obtain a frequency that sets the comparison
frequency. This reference signal, fr, is then presented to the input of a phase/frequency detector and compared
with another signal, fp, the feedback signal, which was obtained by dividing the VCO frequency down by way of
the N counter. The phase/frequency detector's current source outputs pump charge into the loop filter, which
then converts the charge into the VCO's control voltage. The phase/frequency comparator’s function is to
adjust the voltage presented to the VCO until the feedback signal’s frequency (and phase) match that of the
reference signal. When this ‘phase-locked’ condition exists, the RF VCO’s frequency will be N times that of the
comparison frequency, where N is the divider ratio.
1.1
Oscillator
The reference oscillator frequency for the PLL is provided by an external reference TCXO through the OSCin
pin. OSCin block can operate to 40MHz with a minimum input sensitivity of 0.4Vpp.
The inputs have a Vcc/2
input threshold and can be driven from an external CMOS or TTL logic gate.
1.2
Reference Divider (R Counter)
The R Counter is clocked through the oscillator block. The maximum input frequency is 40MHz and the
maximum output frequency is 10MHz. The R Counters is a 10 bit CMOS binary counters with a divide range
from 2 to 1,023. See programming description 2.2.1.
1.3
Programmable Divider (N Counter)
The N counter is clocked by the small signal fin input. The LMX2322 RF N counter is a 15 bit integer divider.
The N counter is configured as a 5 bit A Counter and a 10 bit B Counter, offering a continuous integer divide
range from 992 to 32,767. The LMX2322 is capable of operating from 700MHz to 2.0GHz with a 32/33 precaler.
1.3.1 Prescaler
The RF inputs to the prescaler consist of the fin and fin pins which are the complimentary inputs of a differential
pair amplifier.
The differential fin configuration can operate to 2GHz with a minimum input sensitivity of
45mVrms. The input buffer drives A counter’s ECL D-type flip-flops in a dual modulus configuration. The
LMX2322 has a 32/33 prescaler ratio. The prescaler clocks the subsequent CMOS flip-flop chain comprising
the fully programmable A and B counters.
1.4
Phase/Frequency Detector
The phase/frequency detector is driven from the N and R counter outputs. The maximum frequency at the
phase detector inputs is 10 MHz. The phase detector outputs control the charge pumps. The polarity of the
pump-up or pump-down control is programmed using PD_POL, depending on whether RF VCO characteristics
are positive or negative (see programming description 2.2.2). The phase detector also receives a feedback
signal from the charge pump, in order to eliminate dead zone.
1.5
Charge Pump
The phase detector's current source output pumps charge into an external loop filter, which then converts the
charge into the VCO's control voltage. The charge pumps steer the charge pump output, Cpo, to Vcc (pump-up)
or Ground (pump-down). When locked, Cpo is primarily in a Tri-state mode with small corrections. The RF
charge pump output current magnitude is set to 4.0mA. The charge pump output can also be used to output
divider signals as detailed in section 2.2.3.
1.6
Microwire Serial Interface
The programmable functions are accessed through the Microwire serial interface. The interface is made of three
functions: clock, data and latch enable (LE). Serial data for the various counters is clocked in from data on the
rising edge of clock, into the 18- bit shift register. Data is entered MSB first. The last bit decodes the internal
register address. On the rising edge of LE, data stored in the shift register is loaded into one of the two
9/24/1998
Rev 1.6
6
LMX2322
Advance Information
appropriate latches (selected by address bits). A complete programming description is included in the following
sections.
1.7
Power Control
The PLL can be power controlled in two ways.
The first method is by setting the CE pin LOW.
This
asynchronously powers down the PLL and TRI-STATEs the charge pump output, regardless of the PWDN bit
status. The second method is by programming through MICROWIRE, while keeping the CE HIGH.
Programming the PWDN bit in the N register HIGH (CE=HIGH) will disable the N counter and de-bias the fin
input (to a high impedance state). The R counter functionality also becomes disabled. The reference oscillator
block powers down when the power down bit is asserted. The OSCin pin reverts to a high impedance state
when this condition exists. Power down forces the charge pump and phase comparator logic to a TRI-STATE
condition. A power down counter reset function resets both N and R counters. Upon powering up the N counter
resumes counting in "close" alignment with the R counter (The maximum error is one prescaler cycle). The
MICROWIRE control register remains active and capable of loading and latching in data during all of the power
down modes.
9/24/1998
Rev 1.6
7
LMX2322
Advance Information
2.0 Programming Description
2.1
MICROWIRETM Interface
TM
The MICROWIRE
interface is comprised of an 18 bit shift register, a R register and a N register. The shift
register consists of a 17 bit DATA field and a 1 bit address (ADDR) field as shown below. When Latch Enable
transitions HIGH, data stored in the shift register is loaded into either the R or N register depending on the ADDR
bit as described in Table 2.1.1. The data is loaded MSB first. The DATA field assignment for the R and N
registers are shown in Table 2.1.2 below.
MSB
LSB
DATA [16:0]
ADDR
17
1
2.1.1
0
Address bit Truth Table
When LE is transitioned high, data is transferred from the 18-bit shift register into either the 14-bit R register, or
the 17 bit N register depending upon the state of the ADDR bit.
ADDR
2.1.2
DATA Location
0
N register
1
R register
Register Content Truth Table
First Bit
SHIFT REGISTER BIT LOCATION
17 16 15
14
N register
R register
2.2
13
12
11
10 9 8 7 6 5 4 3
NB_CNTR
X
X
X
Last Bit
NA_CNTR
TEST RS PD_POL CP_TRI
2
1
CTL_WORD
R_CNTR
0
0
1
R REGISTER
If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into
the 14-bit R register. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide
ratio is programmed using the bits R_CNTR as shown in Table 2.2.1. The ratio must be ≥ 2. The PD_POL,
CP_TRI and TEST bits control the phase detector polarity, charge pump tri-state, and test mode respectively, as
shown in Table 2.2.2 . The RS bit is reserved and should always be set to zero. X denotes a don’t care condition.
First Bit
SHIFT REGISTER BIT LOCATION
17 16 15
X
X
X
14
13
12
11
10 9 8 7 6 5 4 3
TEST RS PD_POL CP_TRI
R_CNTR[9:0]
Last Bit
2
1
0
1
9/24/1998
Rev 1.6
8
LMX2322
Advance Information
2.2.1 10-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
R_CNTR
Divide
Ratio
2
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
0
3
0
0
0
0
0
0
0
0
1
1
•
•
•
•
•
•
•
•
•
•
•
1,023
1
1
1
1
1
1
1
1
1
1
NOTES: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited)
R_CNTR - These bits select the divide ratio of the programmable reference dividers
2.2.2 R Register Truth Table
BIT
LOCATION
FUNCTION
0
1
CP_TRI
R[11]
Charge Pump TRISTATE
Normal
operation
TRISTATE
PD_POL
R[12]
Phase Detector Polarity
Negative
Positive
TEST
R[14]
Test mode bit
Normal
operation
Test mode
If the test mode is NOT activated (R[14]=0), the charge pump is active when CP_TRI is set LOW. When
CP_TRI is set HIGH, the charge pump output and phase comparator are forced to a TRI-STATE condition. This
bit must be set HIGH if the test mode is ACTIVATED (R[14]=1).
If the test mode is NOT activated (R[14]=0), PD_POL sets the VCO characteristics to positive when set HIGH.
When PD_POL is set LOW, the VCO exhibits a negative characteristic where the VCO frequency decreases
with increasing control voltage.
If the test mode is ACTIVATED (R[14]=1), the outputs of the N and R counters are directed to the CPo output to
allow for testing. The PD_POL bit selects which counter output according to Table 2.2.3.
2.2.3
Test mode truth table (R[14] = 1)
CPo Output
CP_TRI
R[11]
PD_POL
R[12]
R divider output
1
0
N divider output
1
1
2.3 N REGISTER
If the address bit is LOW (ADDR=0), when LE is transitioned high, data is transferred from the 18-bit shift register
into the 17-bit N register.
The N register consists of the 5-bit swallow counter (A counter), the 10 bit
programmable counter (B counter) and the control word. Serial data format is shown below in tables 2.3.1 and
2.3.2. The pulse swallow function which determines the divide ratio is described in section 2.3.3.
First Bit
17
16
SHIFT REGISTER BIT LOCATION
15
14
13
12
11
10
9
8
NB_CNTR [9:0]
7
6
5
Last Bit
4
3
NA_CNTR[4:0]
2
1
CTL_WORD[1:0]
0
0
9/24/1998
Rev 1.6
9
LMX2322
2.3.1
Advance Information
5-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
Swallow
Count
(A)
4
3
2
1
0
0
0
0
0
0
0
1
0
0
0
0
1
•
•
•
•
•
•
31
1
1
1
1
1
Notes:
NA_CNTR
Swallow Counter Value: 0 to 31
NB_CNTR > NA_CNTR
2.3.2 10-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
NB_CNTR
Divide
Ratio
3
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
1
4
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
1023
1
1
1
1
1
1
1
1
1
1
NOTES:
Divide ratio: 3 to 1,023(Divide ratios less than 3 are prohibited)
NB_CNTR > NA_CNTR
2.3.3
PULSE SWALLOW FUNCTION
The N divider counts such that it divides the VCO RF frequency by (P+1) A times, and then divides by P(B-A)
times. The B value (NB_CNTR) must be > 3. The continuous divider ratio is from 992 to 32,767. Divider ratios
less than 992 are achievable as long as the binary counter value is greater than the swallow counter value
(NB_CNTR > NA_CNTR).
fvco = N x ( fosc / R )
N = (P x B) + A
fvco:
Output frequency of external voltage controlled oscillator (VCO)
fosc:
Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of binary 10-bit programmable reference counter (3 to 1023)
N:
Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767)
B:
Preset divide ratio of binary 10-bit programmable B counter (3 to 1023)
A:
Preset value of binary 5-bit swallow A counter (0 < A < 31, A < B)
P:
Preset modulus of dual modulus prescaler (P=32)
9/24/1998
Rev 1.6
10
LMX2322
Advance Information
2.3.4 CTL_WORD
MSB
LSB
CNT_RST
PWDN
2.3.4.1 Reserve Word Truth Table
CE
CNT_RST
PWDN
FUNCTION
1
0
0
Normal Operation
1
0
1
Synchronous Powerdown
1
1
0
counter reset
1
1
1
Asynchronous Powerdown
0
X
X
Asynchronous Powerdown
Notes:
X denotes don’t care.
1. The Counter Reset bit when activated allows the reset of both N and R counters. Upon powering up the N counter
resumes counting in "close" alignment with the R counter. (The maximum error is one prescalar cycle).
2. Both synchronous and asynchronous power down modes are available with the LMX2322 to be able to adapt to
different types of applications. The MICROWIRE control register remains active and capable of loading and latching in
data during all of the powerdown modes
Synchronous Power down Mode
The PLL loops can be synchronously powered down by setting the counter reset mode bit to LOW (N[2] = 0)
and its power down mode bit to HIGH (N[1] = 1). The power down function is gated by the charge pump. Once
the power down mode and counter reset mode bits are loaded, the part will go into power down mode upon the
completion of a charge pump pulse event.
Asynchronous Power down Mode
The PLL loops can be asynchronously powered down by setting the counter reset mode bit to HIGH (N[2] = 1)
and its power down mode bit to HIGH(N[1] = 1). The power down function is NOT gated by the charge pump.
Once the power down and counter reset mode bits are loaded, the part will go into power down mode
immediately.
The R and N counters are disabled and held at load point during the synchronous and asynchronous power
down modes. This will allow a smooth acquisition of the RF signal when the PLL is programmed to power up.
Upon powering up, both R and N counters will start at the ‘zero’ state, and the relationship between R and N will
not be random.
9/24/1998
Rev 1.6
11
LMX2322
Advance Information
SERIAL DATA INPUT TIMING
Data
N18: MSB
N17
(R15: MSB)
N10
(R14)
(R8)
C2
N9
(R6)
(R7)
C1: LSB
(C2)
C1: LSB
Clock
t CWL
LE
tES
OR
tCS
tCH
t CWH
tEW
LE
NOTES:
Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around Vcc/2. The test
waveform has an edge rate of 0.6 V/nsec with amplitudes of 2.2V @ Vcc=2.7 V and 2.6V @ Vcc = 3.9 V.
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
fr
fp
H
Z
CPo
fr > fp
NOTES:
fr = fp
L
fr < fp
fr < fp
fr < fp
Phase difference detection range: - 2π to + 2π
The minimum width pump up and pump down current pulses occur at the CPo pin when the loop is locked.
PD_POL = 1
fr:
Phase comparator input from the R Divider
fp:
Phase comparator input from the N divider
CPo: Charge pump output
9/24/1998
Rev 1.6
12
LMX2322
Advance Information
Physical Dimensions
16pin Chip Scale Package
9/24/1998
Rev 1.6
13
LMX2322
Advance Information
Physical Dimensions (continued)
16pin Thin Shrink Small Outline Packages
9/24/1998
Rev 1.6
14