ams AG

TAOS Inc.
is now
ams AG
The technical content of this TAOS datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: [email protected]
Please visit our website at www.ams.com
TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
r
r
TAOS098 − MARCH 2010
PACKAGE CS
6-LEAD CHIPSCALE
(TOP VIEW)
Features
D Approximately 30 More Sensitive Than the
TSL2560/61 Device
D Approximates Human Eye Response
D Programmable ALS Interrupt Function with
D
Package Drawings are Not to Scale
PACKAGE FN
DUAL FLAT NO-LEAD
(TOP VIEW)
Vdd 1
D
6 SDA
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D Automatically Rejects 50/60-Hz Lighting
D
4 SCL
GND 3
al
id
D
5 INT
ADDR SEL 2
User-Defined Upper and Lower Threshold
Settings
16-Bit Digital Output with SMBus (TSL2580)
at 100 kHz or I2C (TSL2581) Fast-Mode at
400 kHz
Programmable Analog Gain and Integration
Time Supporting 1,000,000-to-1 Dynamic
Range
Available in Ultra-Small 1.25 mm 1.75 mm
Chipscale Package
lv
D
6 SDA
Vdd 1
ADDR SEL 2
Ripple
Low Quiescent Current 3 A in Power
Down Mode
RoHS Compliant
GND 3
5 INT
4 SCL
Applications
D Ambient Light Sensor (ALS) for Smart
Phones, Digital Photo Frames, and Portable
Navigation Systems
D ALS for LED Signs, Laptop Computers, and
LCD TVs
Description
ni
ca
The TSL2580 and TSL2581 are very-high sensitivity light-to-digital converters that transform light intensity to
a digital signal output capable of direct I2C (TSL2581) or SMBus (TSL2580) interface. Each device combines
one broadband photodiode (visible plus infrared) and one infrared-responding photodiode on a single CMOS
integrated circuit capable of providing a near-photopic response over an effective 16-bit dynamic range (16-bit
resolution). Two integrating ADCs convert the photodiode currents to a digital output that represents the
irradiance measured on each channel. This digital output can be input to a microprocessor where illuminance
(ambient light level) in lux is derived using an empirical formula to approximate the human eye response. The
TSL2580 device permits an SMB-Alert style interrupt, and the TSL2581 device supports a traditional level style
interrupt that remains asserted until the firmware clears it.
Te
ch
While useful for general purpose light sensing applications, the TSL2580/81 devices are designed particularly
for display panels (LCD, OLED, etc.) with the purpose of extending battery life and providing optimum viewing
in diverse lighting conditions. Display panel backlighting, which can account for up to 30 to 40 percent of total
platform power, can be automatically managed. Both devices are also ideal for controlling keyboard illumination
based upon ambient lighting conditions. Illuminance information can further be used to manage exposure
control in digital cameras. The TSL2580/81 devices are ideal in notebook/tablet PCs, LCD monitors, flat-panel
televisions, cell phones, and digital cameras. In addition, other applications include street light control, security
lighting, sunlight harvesting, machine vision, and automotive instrumentation clusters.
The LUMENOLOGY r Company
Copyright E 2010, TAOS Inc.
r
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972)
r 673-0759
www.taosinc.com
1
TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
Functional Block Diagram
Channel 0
Visible and IR
Channel 1
IR Only
VDD = 2.7 V to 3.6 V
Command
Register
Address Select
ADDR SEL
ADC
Register
Interrupt
al
id
Integrating
A/D Converter
INT
SCL
Two-Wire Serial Interface
lv
SDA
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Detailed Description
The TSL2580 and TSL2581 are second-generation ambient light sensor devices. Each contains two integrating
analog-to-digital converters (ADC) that integrate currents from two photodiodes. Integration of both channels
occurs simultaneously. Upon completion of the conversion cycle, the conversion result is transferred to the
Channel 0 and Channel 1 data registers, respectively. The transfers are double-buffered to ensure that the
integrity of the data is maintained. After the transfer, the device automatically begins the next integration cycle.
Communication to the device is accomplished through a standard, two-wire SMBus or I2C serial bus.
Consequently, the TSL258x device can be easily connected to a microcontroller or embedded controller. No
external circuitry is required for signal conditioning, thereby saving PCB real estate as well. Since the output
of the TSL258x device is digital, the output is effectively immune to noise when compared to an analog signal.
Te
ch
ni
ca
The TSL258x devices also support an interrupt feature that simplifies and improves system efficiency by
eliminating the need to poll a sensor for a light intensity value. The primary purpose of the interrupt function is
to detect a meaningful change in light intensity. The concept of a meaningful change can be defined by the user
both in terms of light intensity and time, or persistence, of that change in intensity. The TSL258x devices have
the ability to define a threshold above and below the current light level. An interrupt is generated when the value
of a conversion exceeds either of these limits.
Copyright E 2010, TAOS Inc.
The LUMENOLOGY r Company
r
r
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
Terminal Functions
TERMINAL
NAME
CS PKG
NO.
FN PKG
NO.
TYPE
I
DESCRIPTION
ADDR SEL
2
2
GND
3
3
Address select — three-state.
INT
5
5
O
Level or SMB Alert interrupt — open drain.
SCL
4
4
I
Serial clock input terminal — clock signal.
SDA
6
6
I/O
Serial data I/O terminal — serial data I/O.
VDD
1
1
al
id
Power supply ground. All voltages are referenced to GND.
Supply voltage.
DEVICE
INTERFACE
PACKAGE − LEADS
PACKAGE DESIGNATOR
SMBus
Chipscale−6
CS
TSL2580
SMBus
Dual Flat No-Lead−6
FN
I2C
Dual Flat No-Lead−6
FN
ORDERING NUMBER
TSL2580CS
TSL2580FN
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TSL2580
TSL2581
lv
Available Options
TSL2581FN
Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V
Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.8 V
Digital output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 mA to 20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
Supply voltage, VDD
ca
Recommended Operating Conditions
Operating free-air temperature, TA
MIN
NOM
MAX
2.7
3
3.6
V
70
°C
−30
ni
SCL SDA input low voltage,
SCL,
voltage VIL
0.8
TSL2581 (Note 3)
0.3 VDD
TSL2580 (Note 2)
2
TSL2581 (Note 3)
0.7 VDD
ch
SCL SDA input high voltage,
SCL,
voltage VIH
TSL2580 (Note 2)
UNIT
V
V
Te
NOTES: 2. Meets SMB specifications.
3. Meets I2C specifications where VDD = VBUS.
The LUMENOLOGY r Company
Copyright E 2010, TAOS Inc.
r
r
www.taosinc.com
3
TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
Electrical Characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Active
Supply current
INT SDA output low voltage
INT,
I LEAK
Leakage current
UNIT
250
μA
10
μA
3 mA sink current
0
0.4
V
6 mA sink current
0
0.6
V
−5
5
μA
3
Power down
VOL
MAX
175
al
id
IDD
TYP
Operating Characteristics, VDD = 3 V, TA = 25C, (unless otherwise noted) (Notes 1, 2, 3, and 4)
TEST CONDITIONS
CHANNEL
Oscillator frequency
Ee = 0, ITIME = 0xB6 (200 ms),
gain = 16×
Dark ADC count value
Ch0
Ch1
Ch0
Full scale ADC count value
ITIME = 0x6C (400 ms)
ADC count value
ADC count value ratio: Ch1/Ch0
Irradiance responsivity
750
MAX
UNIT
795
kHz
0
1
5
0
1
5
65535
Ch1
λp = 850 nm, ITIME = 0xF6 (27 ms)
Ee = 220 μW/cm2, gain = 16×
Ch0
Ch1
5000
6000
700
4000
Ch1
5000
6000
10 8
10.8
15 8
15.8
20.8
20 8
41
55
68
Ch0
29.1
Ch1
4
Ch0
22.8
Ch1
12.5
%
counts/
(μW/
cm2)
8×
Ch0
7
8
Ch1
7
8
9
16×
Ch0
15
16
17
Ch1
15
16
17
Ch0
97
107
115
Ch1
100
115
125
ca
counts
2750
λp = 850 nm
111×
counts
65535
4000
λp = 625 nm
λp = 850 nm
nm, ITIME = 0xF6 (27 ms)
Gain scaling (relative to 1×)
37887
Ch0
Ch0
counts
37887
Ch1
λp = 625 nm, ITIME = 0xF6 (27 ms)
Ee = 171.6 μW/cm2, gain = 16×
λp = 625 nm
nm, ITIME = 0xF6 (27 ms)
Re
TYP
705
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ITIME = 0xDB (100 ms)
MIN
lv
PARAMETER
fosc
9
×
Te
ch
ni
NOTES: 1. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDs
and infrared 850 nm LEDs are used for final product testing for compatibility with high-volume production.
2. The 625 nm irradiance Ee is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength
λp = 625 nm and spectral halfwidth Δλ½ = 20 nm.
3. The 850 nm irradiance Ee is supplied by a light-emitting diode with the following characteristics: peak wavelength
λp = 850 nm and spectral halfwidth Δλ½ = 42 nm.
4. The integration time Tint, is dependent on internal oscillator frequency (fosc) and on the number of integration cycles (ITIME) in the
Timing Register (0xFF) as described in the Register section. For nominal fosc = 750 kHz, nominal Tint = 2.7 ms × ITIME.
Copyright E 2010, TAOS Inc.
The LUMENOLOGY r Company
r
r
4
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
AC Electrical Characteristics, VDD = 3 V, TA = 25C (unless otherwise noted)
PARAMETER†
t(CONV)
TEST CONDITIONS
Conversion time
Clock frequency (I2C only)
f(SCL)
TYP
MAX
UNIT
2.7
688
ms
0
400
kHz
100
kHz
10
Bus free time between start and stop condition
1.3
μs
t(HDSTA)
Hold time after (repeated) start condition. After
this period, the first clock is generated.
0.6
μs
t(SUSTA)
Repeated start condition setup time
0.6
t(SUSTO)
Stop condition setup time
0.6
t(HDDAT)
Data hold time
t(SUDAT)
Data setup time
t(LOW)
SCL clock low period
t(HIGH)
SCL clock high period
t(TIMEOUT)
Detect clock/data low timeout (SMBus only)
tF
tR
Ci
Input pin capacitance
0
μs
μs
0.9
μs
ns
lv
100
al
id
Clock frequency (SMBus only)
t(BUF)
1.3
μs
0.6
μs
35
ms
Clock/data fall time
300
ns
Clock/data rise time
300
ns
10
pF
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25
Specified by design and characterization; not production tested.
Te
ch
ni
ca
†
MIN
The LUMENOLOGY r Company
Copyright E 2010, TAOS Inc.
r
r
www.taosinc.com
5
TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
PARAMETER MEASUREMENT INFORMATION
t(LOW)
t(R)
t(F)
VIH
SCL
VIL
t(HDSTA)
t(BUF)
t(HIGH)
t(SUSTA)
t(HDDAT)
t(SUSTO)
t(SUDAT)
al
id
VIH
SDA
VIL
S
S
Start
Condition
Start
P
Stop
t(LOWSEXT)
SCLACK
SCLACK
t(LOWMEXT)
t(LOWMEXT)
t(LOWMEXT)
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SCL
lv
P
Stop
Condition
SDA
Figure 1. Timing Diagrams
1
9
SCL
A6
SDA
A5
A4
Start by
Master
A3
A2
A1
A0
R/W
1
D7
9
D6
D5
D4
D3
D2
D1
ACK by
TSL258x
D0
ACK by Stop by
TSL258x Master
Frame 1 SMBus Slave Address Byte
Frame 2 Command Byte
ca
Figure 2. Example Timing Diagram for SMBus Send Byte Format
1
A6
A5
A4
ch
SDA
ni
SCL
A3
A2
A1
A0
9
R/W
Start by
Master
1
D7
Te
D6
D5
D4
D2
D1
D0
NACK by Stop by
Master Master
Frame 2 Data Byte From TSL258x
Figure 3. Example Timing Diagram for SMBus Receive Byte Format
The LUMENOLOGY r Company
r
r
6
D3
ACK by
TSL258x
Frame 1 SMBus Slave Address Byte
Copyright E 2010, TAOS Inc.
9
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
TYPICAL CHARACTERISTICS
NORMALIZED RESPONSIVITY
vs.
ANGULAR DISPLACEMENT
SPECTRAL RESPONSIVITY
0.4
Ch 1
0.2
0
300
0.6
lv
Normalized Responsivity
0.6
0.4
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Normalized Responsivity
Ch 0
Optical Axis
0.8
0.8
al
id
1.0
1
0.2
400
500
600
700
800
900 1000 1100
λ − Wavelength − nm
0
−90
−60
−30
0
30
60
− Angular Displacement − °
Figure 5
Te
ch
ni
ca
Figure 4
90
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Copyright E 2010, TAOS Inc.
r
r
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7
TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
PRINCIPLES OF OPERATION
Analog-to-Digital Converter
al
id
The TSL258x contains two integrating analog-to-digital converters (ADC) that integrate the currents from the
channel 0 and channel 1 photodiodes. Integration of both channels occurs simultaneously, and upon completion
of the conversion cycle the conversion result is transferred to the channel 0 and channel 1 data registers,
respectively. The transfers are double buffered to ensure that invalid data is not read during the transfer. After
the transfer, the device automatically begins the next integration cycle.
Digital Interface
lv
Interface and control of the TSL258x is accomplished through a two-wire serial interface to a set of registers
that provide access to device control functions and output data. The serial interface is compatible with System
Management Bus (SMBus) versions 1.1 and 2.0, and I2C bus Fast-Mode. The TSL258x offers three slave
addresses that are selectable via an external pin (ADDR SEL). The slave address options are shown in Table 1.
am
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Table 1. Slave Address Selection
ADDR SEL TERMINAL LEVEL
SLAVE ADDRESS
SMB ALERT ADDRESS
GND
0101001
0001100
Float
0111001
0001100
VDD
1001001
0001100
NOTE: The Slave and SMB Alert Addresses are 7 bits. Please note the SMBus and I2C protocols on pages 10 through 12. A read/write bit should
be appended to the slave address by the master device to properly communicate with the TSL258x device.
SMBus and I2C Protocols
Each Send and Write protocol is, essentially, a series of bytes. A byte sent to the TSL258x with the most
significant bit (MSB) equal to 1 will be interpreted as a COMMAND byte. The lower four bits of the COMMAND
byte form the register select address (see Table 2), which is used to select the destination for the subsequent
byte(s) received. The TSL258x responds to any Receive Byte requests with the contents of the register
specified by the stored register select address.
The TSL2580 implements the following protocols of the SMB 2.0 specification:
ca
Send Byte Protocol
Receive Byte Protocol
ni
Write Byte Protocol
Write Word Protocol
ch
Read Word Protocol
Block Write Protocol
Block Read Protocol
Te
D
D
D
D
D
D
D
The TSL2581 implements the following protocols of the Philips Semiconductor I2C specification:
D I2C Write Protocol
D I2C Read (Combined Format) Protocol
Copyright E 2010, TAOS Inc.
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
When an SMBus Block Write or Block Read is initiated (see description of COMMAND Register), the byte
following the COMMAND byte is ignored but is a requirement of the SMBus specification. This field contains
the byte count (i.e. the number of bytes to be transferred). The TSL2580 (SMBus) device ignores this field and
extracts this information by counting the actual number of bytes transferred before the Stop condition is
detected.
al
id
When an I2C Write or I2C Read (Combined Format) is initiated, the byte count is also ignored but follows the
SMBus protocol specification. Data bytes continue to be transferred from the TSL2581 (I2C) device to Master
until a NACK is sent by the Master.
The data formats supported by the TSL2580 and TSL2581 devices are:
D Master transmitter transmits to slave receiver (SMBus and I2C):
−
The transfer direction in this case is not changed.
−
lv
D Master reads slave immediately after the first byte (SMBus only):
At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter
becomes a master receiver and the slave receiver becomes a slave transmitter.
−
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D Combined format (SMBus and I2C):
During a change of direction within a transfer, the master repeats both a START condition and the slave
address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and a STOP condition.
For a complete description of SMBus protocols, please review the SMBus Specification at
http://www.smbus.org/specs. For a complete description of I2C protocols, please review the I2C Specification
at http://www.semiconductors.philips.com.
1
7
1
1
8
1
1
S
Slave Address
Wr
A
Data Byte
A
P
X
X
Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)
P
Stop Condition
Rd
Read (bit value of 1)
S
Start Condition
Sr
Repeated Start Condition
Wr
Write (bit value of 0)
ni
ca
A
Shown under a field indicates that that field is required to have a value of X
...
Continuation of protocol
Te
ch
X
The LUMENOLOGY r Company
Master-to-Slave
Slave-to-Master
Figure 6. SMBus and I2C Packet Protocol Element Key
Copyright E 2010, TAOS Inc.
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r
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
1
7
1
1
8
1
1
S
Slave Address
Wr
A
Data Byte
A
P
Figure 7. SMBus Send Byte Protocol
1
7
1
1
8
1
1
S
Slave Address
Rd
A
Data Byte
A
P
al
id
1
Figure 8. SMBus Receive Byte Protocol
7
1
1
S
Slave Address
Wr
A
8
Command Code
1
8
A
Data Byte
1
7
S
1
Slave Address
1
Wr
1
A
P
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Figure 9. SMBus Write Byte Protocol
1
lv
1
8
A
Command Code
1
1
7
1
1
8
1
1
A
S
Slave Address
Rd
A
Data Byte Low
A
P
1
Figure 10. SMBus Read Byte Protocol
1
7
1
S
Slave Address
Wr
1
8
1
8
1
8
1
1
A
Command Code
A
Data Byte Low
A
Data Byte High
A
P
Figure 11. SMBus Write Word Protocol
1
Slave Address
Wr
1
8
A
Command Code
1
1
7
1
1
8
1
A
S
Slave Address
Rd
A
Data Byte Low
A
8
Data Byte High
...
1
1
A
P
1
Figure 12. SMBus Read Word Protocol
Te
ch
ni
S
7
ca
1
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
1
S
7
Slave Address
1
1
Wr
A
8
Command Code
1
8
1
8
1
A
Byte Count = N
A
Data Byte 1
A
8
8
1
Data Byte 2
...
A
...
Data Byte N
1
1
A
P
Figure 13. SMBus Block Write or I2C Write Protocols
S
7
Slave Address
1
1
Wr
A
8
Command Code
8
Data Byte 1
1
1
7
1
1
8
A
Sr
Slave Address
Rd
A
Byte Count = N
1
A
8
Data Byte 2
1
A
1
A
...
8
...
lv
1
al
id
NOTE: The I2C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 12 for additional information regarding the Block Read/Write protocol.
Data Byte N
1
1
A
P
1
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Figure 14. SMBus Block Read or I2C Read (Combined Format) Protocols
NOTE: The I2C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates
a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
Register Set
The TSL258x is controlled and monitored by sixteen registers and a command register accessed through the
serial interface. These registers provide for a variety of control functions and can be read to determine results
of the ADC conversions. The register set is summarized in Table 2.
Table 2. Register Address
−−
00h
01h
02h
03h
04h
05h
06h
07h
REGISTER FUNCTION
COMMAND
Specifies register address
CONTROL
Control of basic functions
TIMING
W
Interrupt control
THLLOW
Low byte of low interrupt threshold
THLHIGH
High byte of low interrupt threshold
THLLOW
Low byte of high interrupt threshold
THLHIGH
High byte of high interrupt threshold
ANALOG
Analog control register
ID
R/W
Part number / Rev ID
CONSTANT
Number 4 (for SMBus block reads)
14h
DATA0LOW
ADC channel 0 LOW data register
15h
DATA0HIGH
ADC channel 0 HIGH data register
16h
DATA1LOW
ADC channel 1 LOW data register
17h
DATA1HIGH
ADC channel 1 HIGH data register
18h
TIMERLOW
Manual integration timer LOW register
19h
TIMERHIGH
Manual integration timer HIGH register
ch
13h
Te
R/W
Integration time/gain control
INTERRUPT
ni
12h
RESISTER NAME
ca
ADDRESS
R
The mechanics of accessing a specific register depends on the specific SMB protocol used. See the section
on SMBus protocols, above. In general, the COMMAND register is written first to specify the specific
control/status register for following read/write operations.
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TSL2580, TSL2581
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Command Register
The command register specifies the address of the target register for subsequent read and write operations and
contains eight bits as described in Table 3. The command register defaults to 00h at power on.
Table 3. Command Register
7
6
CMD
5
4
3
TRANSACTION
FIELD
BIT
CMD
7
2
1
0
Reset
00h
ADDRESS
DESCRIPTION
Select command register. Must write as 1 when addressing COMMAND register.
Select type of transaction to follow in subsequent data transfers:
TRANSACTION
6:5
TRANSACTION
DESCRIPTION
lv
FIELD VALUE
al
id
Bit :
00
Byte protocol
SMB read/write byte protocol
01
Word protocol
SMB read/write word protocol
Block protocol
SMB and I2C read/write block protocol. Regarding SMBus block
transfer, see note below.
Special function
Specifies a special command function in the ADDRESS field (see
below).
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10
11
Register Address/Special Function. This field selects the specific control or status register for following
write and read commands according to Table 2. When the TRANSACTION field is set to 11b, this field
specifies a special command function as outlined below.
ADDRESS
4:0
FIELD VALUE
SPECIAL
FUNCTION
00000
Reserved
00001
Interrupt clear
Clear any pending interrupt and is a write−once−to−clear bit
00010
Stop manual
integration
When the Timing Register is set to 00h, a SendByte command
with the ADDRESS field set to 0010b will stop a manual
integration. The actual length of the integration cycle may be read
in the MANUAL INTEGRATION TIMER Register.
00011
Start manual
integration
When the Timing Register is set to 00h, a SendByte command
with the ADDRESS field set to 0011b will start a manual
integration. The actual length of the integration cycle may be read
in the MANUAL INTEGRATION TIMER Register.
x11xx
Reserved
DESCRIPTION
Reserved. Write as 0000b.
Reserved. Write as 11xxb.
ni
ca
NOTE: An I2C block transaction will continue until the Master sends a stop condition. See Figure 13 and Figure 14. Unlike the I2C protocol, the
SMBus read/write protocol requires a Byte Count. All four ADC Channel Registers (14h through 17h) can be read simultaneously in a
single SMBus transaction. This is the only 32-bit data block supported by the TSL258x SMBus protocol. The TRANSACTION Field Value
must be set to 10b, and a read condition should be initiated with a COMMAND CODE of D3h. By using a COMMAND CODE of D3h during
an SMBus Block Read Protocol, the TSL258x device will automatically insert the appropriate Byte Count (Byte Count = 4) as illustrated
in Figure 14. A write condition should not be used in conjunction with the 13h register.
Te
ch
NOTE: Only the Send Byte Protocol should be used when clearing interrupts.
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Control Register (00h)
The CONTROL register primarily used to power the TSL258x device up and down as shown in Table 4.
Table 4. Control Register
Address
00h
7
6
Resv
Resv
FIELD
BIT
5
4
ADC_INTR
ADC_VALID
Resv
3
2
1
Resv
Resv
ADC_EN
DESCRIPTION
POWER
Reset
00h
Resv
7:6
ADC_INTR
5
ADC Interrupt. Read only. Indicates that the device is asserting an interrupt.
ADC_VALID
4
ADC Valid. Read only. Indicates that the ADC channel has completed an integration cycle.
Resv
3
Reserved. Write as 0.
Resv
2
Reserved. Write as 0.
ADC_EN
1
ADC Enable. This field enables the two ADC channels to begin integration. Writing a 1 activates the ADC
channels, and writing a 0 disables the ADCs.
POWER
0
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Reserved. Write as 0.
0
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Bit :
Power On. Writing a 1 powers on the device, and writing a 0 turns it off.
NOTE: ADC_EN and POWER must be asserted before the ADC changes will operate correctly. After POWER is asserted, a 2-ms delay is
required before asserting ADC_EN.
Te
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NOTE: The TSL258x device registers should be configured before ADC_EN is asserted.
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Timing Register (01h)
The TIMING register controls the internal integration time of the ADC channels in 2.7 ms increments. The
TIMING register defaults to 00h at power on.
Table 5. Timing Register
7
6
5
4
Address
01h
FIELD
3
2
1
0
Reset
00h
ITIME
BIT
al
id
Bit :
DESCRIPTION
lv
Integration Cycles. Specifies the integration time in 2.7-ms intervals. Time is expressed as a 2’s
complement number. So, to quickly work out the correct value to write: (1) determine the number of
2.7-ms intervals required, and (2) then take the 2’s complement. For example, for a 1 × 2.7-ms interval,
0xFF should be written. For 2 × 2.7-ms intervals, 0xFE should be written. The maximum integration time
is 688.5 ms (00000001b).
Writing a 0x00 to this register is a special case and indicates manual timing mode. See CONTROL and
MANUAL INTEGRATION TIMER Registers for other device options related to manual integration.
7:0
TIME
−
Manual integration
00000000
VALUE
1
2.7 ms
11111111
2
5.4 ms
11111110
19
51.3 ms
11101101
37
99.9 ms
11011011
74
199.8 ms
10110110
148
399.6 ms
01101100
255
688.5 ms
00000001
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ITIME
INTEG_CYCLES
NOTE: The Send Byte protocol cannot be used when ITIME is greater than 127 (for example ITIME[7] = 1) since the upper bit is set aside for
write transactions in the COMMAND register.
Interrupt Register (02h)
ni
ca
The INTERRUPT register controls the extensive interrupt capabilities of the device. The open-drain interrupt
pin is active low and requires a pull-up resistor to VDD in order to pull high in the inactive state. The TSL258x
permits both SMB-Alert style interrupts as well as traditional level style interrupts. The Interrupt Register
provides control over when a meaningful interrupt will occur. The concept of a meaningful change can be defined
by the user both in terms of light intensity and time, or persistence of that change in intensity. The value must
cross the threshold (as configured in the Threshold Registers 03h through 06h) and persist for some period of
time as outlined in Table 6.
ch
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value
outside of the programmed threshold window. The interrupt is active-low and remains asserted until cleared by
writing an 11 in the TRANSACTION field in the COMMAND register.
Te
In SMB-Alert mode, the interrupt is similar to the traditional level style and the interrupt line is asserted low. To
clear the interrupt, the host responds to the SMB-Alert by performing a modified Receive Byte operation, in
which the Alert Response Address (ARA) is placed in the slave address field, and the TSL258x that generated
the interrupt responds by returning its own address in the seven most significant bits of the receive data byte.
If more than one device connected on the bus has pulled the SMBAlert line low, the highest priority (lowest
address) device will win control of the bus during the slave address transfer. If the device loses this arbitration,
the interrupt will not be cleared. The Alert Response Address is 0Ch.
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When INTR = 11, the interrupt is generated immediately following the SMBus write operation. Operation then
behaves in an SMB-Alert mode, and the software set interrupt may be cleared by an SMB-Alert cycle.
Note: Interrupts
are based on the value of Channel 0 only.
Table 6. Interrupt Control Register
7
6
Address
02h
Resv
INTR_STOP
FIELD
BITS
Resv
7
Reserved. Write as 0.
INTR_STOP
6
Stop ADC integration on interrupt. When high, ADC integration will stop once an interrupt is asserted. To
resume operation (1) de-assert ADC_EN using CONTROL register, (2) clear interrupt using COMMAND
register, and (3) re-assert ADC_EN using CONTROL register. Note: Use this bit to isolate a particular
condition when the sensor is continuously integrating.
INTR
5:4
INTR Control Select. This field determines mode of interrupt logic according to Table 7, below.
PERSIST
3:0
Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 8, below.
4
3
2
INTR
1
0
Reset
00h
PERSIST
al
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5
lv
DESCRIPTION
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Bit :
Table 7. Interrupt Control Select
INTR FIELD VALUE
READ VALUE
00
Interrupt output disabled
01
Level Interrupt
10
SMBAlert compliant
11
Test Mode: Sets interrupt and functions as mode 10
NOTE: Field value of 11 may be used to test interrupt connectivity in a system or to assist in debugging interrupt service routine software.
Table 8. Interrupt Persistence Select
PERSIST FIELD VALUE
Every ADC cycle generates interrupt
0001
Any value outside of threshold range
0010
2 integration time periods out of range
3 integration time periods out of range
4 integration time periods out of range
0101
5 integration time periods out of range
0110
6 integration time periods out of range
ca
0011
0100
ni
ch
Te
The LUMENOLOGY r Company
INTERRUPT PERSIST FUNCTION
0000
0111
7 integration time periods out of range
1000
8 integration time periods out of range
1001
9 integration time periods out of range
1010
10 integration time periods out of range
1011
11 integration time periods out of range
1100
12 integration time periods out of range
1101
13 integration time periods out of range
1110
14 integration time periods out of range
1111
15 integration time periods out of range
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Interrupt Threshold Register (03h − 06h)
al
id
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison
function for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low
threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses
above the high threshold specified, an interrupt is asserted on the interrupt pin. Registers THLLOW and
THLHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold. Registers THHLOW
and THHHIGH provide the low and high bytes, respectively, of the upper interrupt threshold. The high and low
bytes from each set of registers are combined to form a 16-bit threshold value. The interrupt threshold registers
default to 00h on power up.
Table 9. Interrupt Threshold Register
ADDRESS
BITS
THLLOW
3h
7:0
ADC channel 0 lower byte of the low threshold
DESCRIPTION
THLHIGH
4h
7:0
ADC channel 0 upper byte of the low threshold
THHLOW
5h
7:0
ADC channel 0 lower byte of the high threshold
THHHIGH
6h
7:0
ADC channel 0 upper byte of the high threshold
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REGISTER
NOTE: Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the Send Byte protocol should
not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the
COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired.
The Write Word protocol should be used to write byte-paired registers. For example, the THLLOW and THLHIGH registers (as well as
the THHLOW and THHHIGH registers) can be written together to set the 16-bit ADC value in a single transaction.
Analog Register (07h)
The ANALOG register provides eight bits of control to the analog block. These bits control the analog gain
settings of the device.
Table 10. Analog Register
7
Address
07h
6
5
4
3
2
1
RESV
FIELD
BITS
Resv
7:3
0
GAIN
ca
Bit :
Reset
00h
DESCRIPTION
Reserved. Write as 0.
Gain Control. Sets the analog gain of the device according to the following table.
GAIN VALUE
1×
x00
2:0
x01
8×
x10
16×
x11
111×
Te
ch
Gain
ni
FIELD VALUE
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ID Register (12h)
The ID register provides the value for both the part number and silicon revision number for that part number.
It is a read-only register whose value never changes.
Table 11. ID Register
7
6
Address
12h
5
4
3
2
PARTNO
1
0
Reset
−−
REVNO
al
id
Bit :
BITS
DESCRIPTION
PARTNO
7:4
Part Number Identification: field value 1000b = TSL2580, field value 1001b = TSL2581
REVNO
3:0
Revision number identification
lv
FIELD
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Constant (13h)
The CONSTANT register provides a means to facilitate SMBus block transfers that is used as the Byte Count
in the SMBus protocol. For example, all four ADC Channel Data Registers can be read in a single SMBus block
transfer if an SMBus Block Read is initiate at address 13h. This register defaults to the constant 4, but may be
set to other values depending upon the end application. For example, if manual integration is employed and
the register is set to 5, then all four ADC Channel Data Registers and the Manual Integration Timer Register
can be read in a single SMBus read block transaction.
Table 12. Constant Register
Bit :
7
Address
12h
6
5
4
3
2
1
CONSTANT
FIELD
BITS
7:0
Reset
−−
DESCRIPTION
Constant value used as the byte count for SMBus block read/write transactions. I2C protocol does not use
the byte count field in the block transaction, so this register should be ignored if an TSL2581 device is used.
Te
ch
ni
ca
CONSTANT
0
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ADC Channel Data Registers (14h − 17h)
The ADC channel data are expressed as 16-bit values spread across two registers. The ADC channel 0 data
registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of
channel 0. Registers DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC
value of channel 1. All channel data registers are read-only and default to 00h on power up.
Table 13. ADC Channel Data Registers
BITS
14h
7:0
ADC channel 0 lower byte
DESCRIPTION
DATA0HIGH
15h
7:0
ADC channel 0 upper byte
DATA1LOW
16h
7:0
ADC channel 1 lower byte
DATA1HIGH
17h
7:0
ADC channel 1 upper byte
al
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ADDRESS
lv
REGISTER
DATA0LOW
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The upper byte data registers can only be read following a read to the corresponding lower byte register. When
the lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a
subsequent read to the upper byte. The upper register will read the correct value even if additional ADC
integration cycles end between the reading of the lower and upper registers.
NOTE: The Read Word protocol can be used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as
the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction
Manual Integration Timer (18h − 19h)
The MANUAL INTEGRATION TIMER registers provide the number of cycles in 10.9 μs increments that
occurred during a manual start/stop integration period. The timer is expressed as a 16-bit value across two
registers. See CONTROL and TIMING Registers for further instructions in configuring a manual integration.
The maximum time that can be derived without an overflow is 714.3 ms.
Table 14. Manual Integration Timer Registers
Bit :
7
Address
18h 19h
6
5
4
3
2
1
TIMER
TIMERLOW
18h
TIMERHIGH
19h
BITS
ca
ADDRESS
7:0
Manual Integration Timer lower byte
7:0
Manual Integration Timer upper byte
Reset
00h
DESCRIPTION
Te
ch
ni
REGISTER
0
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APPLICATION INFORMATION: SOFTWARE
Basic Operation
EXT
PWR
al
id
After applying VDD, the device will initially be in the power-down state. To operate the device, issue a command
to access the CONTROL register followed by the data value 01h to the CONTROL register to power up the
device. The TIMING register should be configured for the preferred integration period, and then the ADC_EN
should be set to 1 to enable both ADC channels.
NO
lv
YES
am
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POWER
DOWN
(Power = 0)
ACTIVE
(ADC_EN = 0
Power = 1)
ALS
(ADC_EN = 1
Power =1)
Figure 15. State Diagram
The following pseudo code illustrates a procedure for reading the TSL258x device (ALS) using word
transactions:
//Set Command bit and Control Reg
ca
Command = 0x80
Power_On = 0x01
ni
//Power on device
WriteByte (Address, Command, Power_On)
//Set Command bit and ALS Timing Reg
//200 ms integration cycle
ch
Command = 0x81
ITIME = 0xb6
//Configure ALS Timing Register for 200 ms integration cycle
WriteByte (Address, Command, ITIME)
//Set Command bit and Control Reg
//Enable ADC Channels
Te
Command = 0x80
ADC_En = 0x03
//Keep device powered on and enable ADC prior to reading channel data
WriteByte (Address, Command, ADC_En | Power_On)
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// Read ADC Channels Using Read Word Protocol − RECOMMENDED
//Address the Ch0 lower data register and configure for Read Word
Command = 0Xb4
//Set Command bit and Word bit
//Reads two bytes from sequential registers 0x14 and 0x15
//Results are returned in DataLow and DataHigh variables
ReadWord (Address, Command, DataLow, DataHigh)
Channel0 = 256 * DataHigh + DataLow
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//Address the Ch1 lower data register and configure for Read Word
Command = 0xb6
//Set Command bit and Word bit
Te
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//Reads two bytes from sequential registers 0x16 and 0x17
//Results are returned in DataLow and DataHigh variables
ReadWord (Address, Command, DataLow, DataHigh)
Channel1 = 256 * DataHigh + DataLow
//Shift DataHigh to upper byte
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APPLICATION INFORMATION: SOFTWARE
Interrupts
al
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The interrupt feature of the TSL258x device simplifies and improves system efficiency by eliminating the need
to poll the sensor for a light intensity value. Interrupt mode is determined by the INTR field in the INTERRUPT
CONTROL Register. The interrupt feature may be disabled by writing a field value of 00h to the Interrupt Control
Register (02h) so that polling can be performed.
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The versatility of the interrupt feature provides many options for interrupt configuration and usage. The primary
purpose of the interrupt function is to signal a meaningful change in light intensity. However, it can also be used
as an end-of-conversion signal. The concept of a meaningful change can be defined by the user both in terms
of light intensity and time, or persistence, of that change in intensity. The TSL258x device implements two
16-bit-wide interrupt threshold registers that allow the user to define thresholds above and below a desired light
level. An interrupt will then be generated when the value of a conversion exceeds either of these limits. For
simplicity of programming, the threshold comparison is accomplished only with Channel 0. This simplifies
calculation of thresholds that are based, for example, on a percent of the current light level. It is adequate to
use only one channel when calculating light intensity differences because, for a given light source, the channel 0
and channel 1 values are linearly proportional to each other and thus both values scale linearly with light
intensity.
To further control when an interrupt occurs, the TSL258x device provides an interrupt persistence feature. This
feature allows the user to specify a number of conversion cycles for which a light intensity exceeding either
interrupt threshold must persist before actually generating an interrupt. This can be used to prevent transient
changes in light intensity from generating an unwanted interrupt. With a value of 1, an interrupt occurs
immediately whenever either threshold is exceeded. With values of N, where N can range from 2 to 15, N
consecutive conversions must result in values outside the interrupt window for an interrupt to be generated. For
example, if N is equal to 10 and the integration time is 402 ms, then an interrupt will not be generated unless
the light level persists for more than 4 seconds outside the threshold.
Two different interrupt styles are available: Level and SMBus Alert. The difference between these two interrupt
styles is how they are cleared. Both result in the interrupt line going active low and remaining low until the
interrupt is cleared. A level style interrupt is cleared by selecting the Special Function in the COMMAND register
and writing a 0 to the Interrupt Clear field value. The SMBus Alert style interrupt is cleared by an Alert Response
as described in the Interrupt Control Register section and SMBus specification.
Te
ch
ni
ca
To configure the interrupt as an end-of-conversion signal so that every ADC integration cycle generates an
interrupt, the interrupt PERSIST field in the Interrupt Control Register (02h) is set to 0000b. Either Level or
SMBus Alert style can be used. An interrupt will be generated upon completion of each conversion. The interrupt
threshold registers are ignored.
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APPLICATION INFORMATION: SOFTWARE
Calculating Lux
al
id
The TSL258x is intended for use in ambient light detection applications such as display backlight control, where
adjustments are made to display brightness or contrast based on the brightness of the ambient light, as
perceived by the human eye. Conventional silicon detectors respond strongly to infrared light, which the human
eye does not see. This can lead to significant error when the infrared content of the ambient light is high, such
as with incandescent lighting, due to the difference between the silicon detector response and the brightness
perceived by the human eye.
lv
This problem is overcome in the TSL258x through the use of two photodiodes. One of the photodiodes
(channel 0) is sensitive to both visible and infrared light, while the second photodiode (channel 1) is sensitive
primarily to infrared light. An integrating ADC converts the photodiode currents to digital outputs. Channel 1
digital output is used to compensate for the effect of the infrared component of light on the channel 0 digital
output. The ADC digital outputs from the two channels are used in a formula to obtain a value that approximates
the human eye response in the commonly used Illuminance unit of Lux:
Lux = 0.105 CH0 − 0.208 CH1
Lux = 0.1088 CH0 − 0.2231 CH1
Lux = 0.0729 CH0 − 0.1286 CH1
Lux = 0.060 CH0 − 0.10 CH1
Lux/CH0 = 0
ODFN Package
For CH1/CH0 = 0.00 to 0.30
For CH1/CH0 = 0.30 to 0.38
For CH1/CH0 = 0.38 to 0.45
For CH1/CH0 = 0.45 to 0.54
For CH1/CH0 > 0.54
Lux = 0.130 CH0 − 0.240 CH1
Lux = 0.1649 CH0 − 0.3562 CH1
Lux = 0.0974 CH0 − 0.1786 CH1
Lux = 0.062 CH0 − 0.100 CH1
Lux/CH0 = 0
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Chipscale Package
For CH1/CH0 = 0.00 to 0.25
For CH1/CH0 = 0.25 to 0.38
For CH1/CH0 = 0.38 to 0.45
For CH1/CH0 = 0.45 to 0.60
For CH1/CH0 > 0.60
The formulas shown above were obtained by optical testing with fluorescent and incandescent light sources,
and apply only to open-air applications. Optical apertures (e.g. light pipes) will affect the incident light on the
device.
ca
Simplified Lux Calculation
Te
ch
ni
Below is the argument and return value including source code (shown on following page) for calculating lux with
the TSL2581FN. The source code is intended for embedded and/or microcontroller applications. All floating
point arithmetic operations have been eliminated since embedded controllers and microcontrollers generally
do not support these types of operations. Because floating point has been removed, scaling must be performed
prior to calculating illuminance if the integration time is not 400 msec and/or if the gain is not 1× as denoted in
the source code on the following pages
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al
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//****************************************************************************
//
// Copyright 2004−2008 TAOS, Inc.
//
// THIS CODE AND INFORMATION IS PROVIDED ”AS IS” WITHOUT WARRANTY OF ANY
// KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR
// PURPOSE.
//
// Module Name:
// lux.cpp
//
//****************************************************************************
#define LUX_SCALE 16 // scale by 2^16
#define RATIO_SCALE 9 // scale ratio by 2^9
See Timing Register
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#define CH_SCALE 16 // scale channel values by 2^16
#define NOM_INTEG_CYCLE 148 // Nominal 400 ms integration.
lv
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// Integration time scaling factors
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// Gain scaling factors
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#define CH0GAIN128X 107 // 128X gain scalar for Ch0
#define CH1GAIN128X 115 // 128X gain scalar for Ch1
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// FN Package coefficients
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
ni
ca
// For Ch1/Ch0=0.00 to 0.30:
//
Lux=0.130*Ch0−0.240*Ch1
//
// For Ch1/Ch0=0.30 to 0.38:
//
Lux=0.1649*Ch0−0.3562*Ch1
//
// For Ch1/Ch0=0.38 to 0.45:
//
Lux=0.0974*Ch0−0.1786*Ch1
//
// For Ch1/Ch0=0.45 to 0.54:
//
Lux=0.062*Ch0−0.10*Ch1
//
// For Ch1/Ch0>0.54:
//
Lux/Ch0=0
//
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#define K1C 0x009A // 0.30 * 2^RATIO_SCALE
#define B1C 0x2148 // 0.130 * 2^LUX_SCALE
#define M1C 0x3d71 // 0.240 * 2^LUX_SCALE
ch
#define K2C 0x00c3 // 0.38 * 2^RATIO_SCALE
#define B2C 0x2a37 // 0.1649 * 2^LUX_SCALE
#define M2C 0x5b30 // 0.3562 * 2^LUX_SCALE
Te
#define K3C 0x00e6 // 0.45 * 2^RATIO_SCALE
#define B3C 0x18ef // 0.0974 * 2^LUX_SCALE
#define M3C 0x2db9 // 0.1786 * 2^LUX_SCALE
#define K4C 0x0114 // 0.54 * 2^RATIO_SCALE
#define B4C 0x0fdf // 0.062 * 2^LUX_SCALE
#define M4C 0x199a // 0.10 * 2^LUX_SCALE
#define K5C 0x0114 // 0.54 * 2^RATIO_SCALE
#define B5C 0x0000 // 0.00000 * 2^LUX_SCALE
#define M5C 0x0000 // 0.00000 * 2^LUX_SCALE
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
unsigned
unsigned
unsigned
unsigned
long
long
long
long
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// lux equation approximation without floating point calculations
//////////////////////////////////////////////////////////////////////////////
// Routine: unsigned int CalculateLux(unsigned int ch0, unsigned int ch0, int iType)
//
// Description: Calculate the approximate illuminance (lux) given the raw
//
channel values of the TSL2581. The equation if implemented
//
as a piece−wise linear approximation.
//
// Arguments: unsigned int iGain − gain, where 0:1X, 1:8X, 2:16X, 3:128X
//
unsigned int tIntCycles − INTEG_CYCLES defined in Timing Register
//
unsigned int ch0 − raw channel value from channel 0 of TSL2581
//
unsigned int ch1 − raw channel value from channel 1 of TSL2581
//
unsigned int iType − package type (1:CS)
//
// Return:
unsigned int − the approximate illuminance (lux)
//
//////////////////////////////////////////////////////////////////////////////
unsigned int CalculateLux(unsigned int iGain, unsigned int tIntCycles, unsigned int ch0,
unsigned int ch1, int iType)
{
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// first, scale the channel values depending on the gain and integration time
// 1X, 400ms is nominal setting
chScale0;
chScale1;
channel1;
channel0;
// No scaling if nominal integration (148 cycles or 400 ms) is used
if (tIntCycles == NOM_INTEG_CYCLE)
chScale0 = (1 << CH_SCALE);
else
chScale0 = (NOM_INTEG_CYCLE << CH_SCALE) / tIntCycles;
ch
ni
ca
switch (iGain)
{
case 0: // 1x gain
chScale1 = chScale0;
// No scale. Nominal setting
break;
case 1: // 8x gain
chScale0 = chScale0 >> 3;
// Scale/multiply value by 1/8
chScale1 = chScale0;
break;
case 2: // 16x gain
chScale0 = chScale0 >> 4;
// Scale/multiply value by 1/16
chScale1 = chScale0;
break;
case 3: // 128x gain
chScale1 = chScale0 / CH1GAIN128X; //Ch1 gain correction factor applied
chScale0 = chScale0 / CH0GAIN128X; //Ch0 gain correction factor applied
break;
}
Te
// scale the channel values
channel0 = (ch0 * chScale0) >> CH_SCALE;
channel1 = (ch1 * chScale1) >> CH_SCALE;
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// find the ratio of the channel values (Channel1/Channel0)
// protect against divide by zero
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LIGHT-TO-DIGITAL CONVERTER
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unsigned long ratio1 = 0;
if (channel0 != 0) ratio1 = (channel1 << (RATIO_SCALE+1)) / channel0;
// round the ratio value
unsigned long ratio = (ratio1 + 1) >> 1;
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// is ratio <= eachBreak?
unsigned int b, m;
switch (iType)
{
case 1: // CS package
if ((ratio >= 0) && (ratio <= K1C))
{b=B1C; m=M1C;}
else if (ratio <= K2C)
{b=B2C; m=M2C;}
else if (ratio <= K3C)
{b=B3C; m=M3C;}
else if (ratio <= K4C)
{b=B4C; m=M4C;}
else if (ratio > K5C)
{b=B5C; m=M5C;}
break;
}
unsigned long temp;
unsigned long lux;
temp = ((channel0 * b) − (channel1 * m));
// round lsb (2^(LUX_SCALE−1))
temp += (1 << (LUX_SCALE−1));
// strip off fractional portion
lux = temp >> LUX_SCALE;
return(lux);
Te
ch
ni
ca
}
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TSL2580, TSL2581
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APPLICATION INFORMATION: HARDWARE
Power Supply Decoupling and Application Hardware Circuit
VBUS
VDD
RP
RPI
TSL2580/
TSL2581
0.1 F
lv
RP
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The power supply lines must be decoupled with a 0.1 μF capacitor placed as close to the device package as
possible (Figure 16). The bypass capacitor should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents caused by internal logic switching.
am
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INT
SCL
SDA
Figure 16. Bus Pull-Up Resistors
Pull-up resistors (Rp) maintain the SDAH and SCLH lines at a high level when the bus is free and ensure the
signals are pulled up from a low to a high level within the required rise time. For a complete description of the
SMBus maximum and minimum Rp values, please review the SMBus Specification at
http://www.smbus.org/specs. For a complete description of I2C maximum and minimum Rp values, please
review the I2C Specification at http://www.semiconductors.philips.com.
Te
ch
ni
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A pull-up resistor (RPI) is also required for the interrupt (INT), which functions as a wired-AND signal in a similar
fashion to the SCL and SDA lines. A typical impedance value between 10 kΩ and 100 kΩ can be used. Please
note that while Figure 16 shows INT being pulled up to VDD, the interrupt can optionally be pulled up to VBUS.
Copyright E 2010, TAOS Inc.
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
APPLICATION INFORMATION: HARDWARE
PCB Pad Layouts
Suggested PCB pad layout guidelines for the CS chipscale package are shown in Figure 17.
al
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0.50
0.50
0.21
lv
6
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0.50
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 17. Suggested CS Package PCB Layout
Suggested PCB pad layout guidelines for the Dual Flat No-Lead (FN) surface mount package are shown in
Figure 18.
2.3
0.9
0.9
0.40
0.65
ca
1.70
ni
0.65
0.40
Figure 18. Suggested FN Package PCB Layout
Te
ch
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
MECHANICAL DATA
PACKAGE CS
Six-Lead Chipscale Device
TOP VIEW
PIN OUT
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BOTTOM VIEW
1
lv
6
5
2
3
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st
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4
1250
END VIEW
400 50
700 55
6 100
BOTTOM VIEW
TYP 30
SIDE VIEW
375 30
6
ca
500
210 30
ch
ni
500
1750
375 30
Lead Free
All linear dimensions are in micrometers. Dimension tolerance is ± 25 μm unless otherwise noted.
Solder bumps are formed of Sn (96.5%), Ag (3%), and Cu (0.5%).
The top of the photodiode active area is 410 μm below the top surface of the package.
The layer above the photodiode is glass and epoxy with an index of refraction of 1.53.
This drawing is subject to change without notice.
Te
NOTES: A.
B.
C.
D.
E.
Pb
500
Figure 19. Package CS — Six-Lead Chipscale Packaging Configuration
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MECHANICAL DATA
PACKAGE FN
Dual Flat No-Lead
TOP VIEW
PIN OUT
TOP VIEW
PIN 1
2000 75
6 SDA
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Vdd 1
ADDR SEL 2
5 INT
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2000
75
END VIEW
4 SCL
lv
GND 3
Photo-Active Area
SIDE VIEW
650 50
Seating Plane
BOTTOM VIEW
203 8
650
300
50
ni
300 50
Pb
750 150
ch
PIN 1
ca
650
Lead Free
Te
NOTES: A. All linear dimensions are in micrometers. Dimension tolerance is ± 20 μm unless otherwise noted.
B. The photodiode active area is 466 μm square and its center is 140 μm above and 20 μm to the right of the package center. The die
placement tolerance is ± 75 μm in any direction.
C. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
D. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish.
E. This package contains no lead (Pb).
F. This drawing is subject to change without notice.
Figure 20. Package FN — Dual Flat No-Lead Packaging Configuration
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TAOS098 − MARCH 2010
MECHANICAL DATA
TOP VIEW
2.00 0.05
1.75
1.50
4.00
al
id
4.00
B
+ 0.30
8.00
− 0.10
lv
3.50 0.05
0.60
0.05
DETAIL A
5 Max
B
A
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st
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A
DETAIL B
5 Max
0.250
0.02
1.35 0.05
1.85 0.05
0.97 0.05
Bo
Ko
All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted.
The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001.
Each reel is 178 millimeters in diameter and contains 3500 parts.
TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
This drawing is subject to change without notice.
Te
ch
NOTES: A.
B.
C.
D.
E.
F.
G.
ni
ca
Ao
Copyright E 2010, TAOS Inc.
Figure 21. Package CS Carrier Tape
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MECHANICAL DATA
TOP VIEW
2.00 0.05
1.75
1.50
4.00
al
id
4.00
B
+ 0.30
8.00
− 0.10
1.00
0.25
B
A
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A
lv
3.50 0.05
DETAIL B
DETAIL A
5 Max
5 Max
0.254
0.02
2.18 0.05
Ao
2.18 0.05
0.83 0.05
Bo
ni
ca
Ko
All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted.
The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001.
Each reel is 178 millimeters in diameter and contains 3500 parts.
TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
This drawing is subject to change without notice.
Te
ch
NOTES: A.
B.
C.
D.
E.
F.
G.
The LUMENOLOGY r Company
Figure 22. Package FN Carrier Tape
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
MANUFACTURING INFORMATION
The package has been tested and have demonstrated an ability to be reflow soldered to a PCB substrate. The
process, equipment, and materials used in these test are detailed below.
Table 15. TSL2580/81 Solder Reflow Profile
PARAMETER
REFERENCE
TSL2580/81
tsoak
2 to 3 minutes
Time above 217°C
t1
Max 60 sec
Time above 230°C
t2
Max 50 sec
Time above Tpeak −10°C
t3
Max 10 sec
2.5°C/sec
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Soak time
lv
Average temperature gradient in preheating
Peak temperature in reflow
Tpeak
260° C (−0°C/+5°C)
Temperature gradient in cooling
Tpeak
al
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The solder reflow profile describes the expected maximum heat exposure of components during the solder
reflow process of product on a PCB. Temperature is measured on top of component. The components should
be limited to a maximum of three passes through this solder reflow profile.
Max −5°C/sec
Not to scale — for reference only
T3
T2
ca
Temperature (C)
T1
Time (sec)
ni
t3
t2
tsoak
ch
t1
Te
Figure 23. TSL2580/TSL2581 Solder Reflow Profile Graph
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MANUFACTURING INFORMATION
Moisture Sensitivity
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Optical characteristics of the device can be adversely affected during the soldering process by the release and
vaporization of moisture that has been previously absorbed into the package molding compound. To ensure the
package molding compound contains the smallest amount of absorbed moisture possible, each device is
dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica
gel to protect them from ambient moisture during shipping, handling, and storage before use.
CS package
5°C to 50°C
60% maximum
1 year out of bag at ambient < 30°C / 60% RH
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Temperature Range
Relative Humidity
Floor Life
lv
The CS package has been assigned a moisture sensitivity level of MSL 2 and the devices should be stored under
the following conditions:
Rebaking will be required if the aluminized envelope has been open for more than 1 year. If rebaking is required,
it should be done at 90°C for 3 hours.
FN package
The FN package has been assigned a moisture sensitivity level of MSL 3 and the devices should be stored under
the following conditions:
Temperature Range
Relative Humidity
Total Time
Opened Time
5°C to 50°C
60% maximum
6 months from the date code on the aluminized envelope — if unopened
168 hours or fewer
Te
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Rebaking will be required if the devices have been stored unopened for more than 6 months or if the aluminized
envelope has been open for more than 168 hours. If rebaking is required, it should be done at 90°C for 4 hours.
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PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
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Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
am
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Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other
limited information may not be available for release.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
ca
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
Te
ch
ni
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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