GPIO ICs Series GPIO Expander IC No.09098EAT02 BU1850MUV ●Description GPIO expander is useful especially for the application that is in short of IO ports. It can 2 1. Control GPIO output states by I C write protocol. 2 2. Know GPIO input states by I C read protocol. Furthermore,it has the interrupt function that can release CPU from polling the registers in the GPIO expander. GPIO expander are also equipped with Built-in power on reset, 3V tolerant input,and NMOS open-drain output. ●Features 1) An 8-Port General purpose input/output interface 150kΩPull-down resistance. 2) NMOS Open-drain output interrupt controller with up to 1us pulse noise filter and bit mask function for individual GPIO port. 3) 3volt tolerant Input 4) Built-in Power On Reset 5) 3mmx3mm small package ●Absolute maximum ratings o (Ta=25 C) Parameter Supply Voltage*1 Symbol Rating Unit comment VDD -0.3 ~ +4.5 V VDD≦VDDIO VDDIO -0.3 ~ +4.5 V *1 VI -0.3 ~ VDD +0.3 V XRST, ADR XINT, SCL, SDA, GPIO[7:0] Input voltage VIT -0.3 ~ 4.5 V Storage temperature range Tstg -55 ~ +125 ℃ Package power PD 272*2 mW This IC is not designed to be X-ray proof. *1 *2 It is prohibited to exceed the absolute maximum ratings even including +0.3 V. o o Package dissipation will be reduced each 2.72mW/ C when the ambient temperature increases beyond 25 C. ●Operating conditions Parameter Symbol Min Typ Max Unit Conditions VVDD 1.65 1.80 3.6 V Core, XINT, XRST, SCL, SDA, ADR, Power On Reset VVDDIO 1.65 1.80 3.6 V GPIO[7:0] VIN -0.2 - VVDD+0.2 V XRST, ADR VINT -0.2 - 3.6 V XINT, SCL, SDA, GPIO[7:0] Operating temperature range Topr -30 - +85 ℃ I2C operating frequency FI2C - - 400 kHz Supply voltage range (VDD) Supply voltage range (VDDIO) Input voltage range www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/17 Slave 2009.09 - Rev.A Technical Note BU1850MUV ●Package Specification B U 1 8 5 0 Lot No. (UNIT: mm) Fig.1 Package Specification (VQFN016V3030) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/17 2009.09 - Rev.A Technical Note BU1850MUV 9 GPIO0 10 GPIO1 11 GPIO2 12 GPIO3 ●Pin Assignment 7 VDDIO 15 GPIO6 6 VDD 16 GPIO7 5 SDA 3 SCL 4 ADR 14 GPIO5 2 XRST 8 VSS 1 XINT 13 GPIO4 Fig.2 Pin Diagram (Top View) ●Block Diagram Functional Block Diagram XINT Interrupt Filter Interrupt Logic INT_MASK IN/OUT Control VDD ADR VDDIO SCL I2C Bus Control Input Filter SDA Power On Reset XRST Reset Gen Shift Register 8bit GPIO [7:0] 8bit GPIO[7:0] Write Pulse Read Pulse VSS Fig.3 Functional Block Diagram www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/17 2009.09 - Rev.A Technical Note BU1850MUV ●Pin-out Functional Descriptions PIN No. PIN name I/O Power source system Function Init Cell Type 1 XINT O VDD Interrupt signal (1s pulse cut)*1 (NMOS Open-drain) Hi-Z B 2 XRST I VDD Reset（Low Active） I E I A I E Hi-Z C - - 3 4 SCL ADR I 2 VDD I Clock for I C 2 VDD Select device address of I C 2 *1 *2 *3 Serial data inout for I C (NMOS Open-drain) Power supply (Core, I/O, Power On Reset) 5 SDA I/O VDD 6 VDD - - 7 VDDIO - - Power supply (I/O) - - 8 VSS - - GND - - 9 GPIO0 I/O VDDIO 10 GPIO1 I/O VDDIO 11 GPIO2 I/O VDDIO 12 GPIO3 I/O VDDIO GPIO4 I/O VDDIO I Pull-down D 13 General purpose input/output. *2 (NMOS Open-drain /CMOS Output, *3 150kΩPull-down ) 14 GPIO5 I/O VDDIO 15 GPIO6 I/O VDDIO 16 GPIO7 I/O VDDIO Specific bit mask control is decided by internal register value. Pull-up more than VDDIO voltage. It is possible to select Pull-down ON or OFF with register. A B C D E Fig.4 Equivalent IO circuit diagram www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/17 2009.09 - Rev.A Technical Note BU1850MUV ●Functional Description 1. Power Modes The device enters the state of Power Down when XRST=”Low” or enters the operation state when XRST=High after powered. Refer to “Electrical Specification” section 5 for a detailed startup sequence. 1-1 Power supply A single supply to Core power supply (VDD) and IO power supply (VDDIO) is prohibited. Supply the power supply to the Core power supply and the IO power supply at the same time. 1-2 Power On Reset A Power On Reset logic is implemented in this device. Therefore, it will operate correctly even if the XRST port is not used. In this case, the XRST port must be connected to high(VDD). 1-3 State of Power Down 2 The device enters the state of Power Down by XRST=”Low”. An internal circuit is initialized and I C interface is invalid is input. Power On Reset becomes inactive during this state. 1-4 State of operation The device enters the operation state by setting XRST to "High". The I2C interface starts communication is the START condition. It becomes standby by the STOP condition. Power On Reset is active in this state. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/17 2009.09 - Rev.A Technical Note BU1850MUV 2. 2 I C Bus Interface Each function of GPIO is controlled by an internal register. The I2C Slave interface is used to write or read this internal register. The device supports up to 400kHz Fast-mode data transfer rate. 2-1 Slave address Two device addresses (Slave address) can be selected by ADR port. A7 A6 A5 A4 A3 A2 A1 ADR=0 0 0 0 1 0 0 1 ADR=1 0 0 0 1 1 1 0 R/W 1/0 2-2 Data transfer One bit of data is transferred during SCL = “1”. During the bit transfer SCL = “1” cycle, the signal SDA should keep the value. If SDA changes during SCL = “1”, a START condition or STOP condition occur and it is interpreted as a control signal. SDA SCL Data is valid when SDA is stable SDA is variable Fig.5 Data transfer 2-3 START-STOP-Repeated START conditions When SDA and SCL are “1”, the data isn’t transferred on the 2-wire bus. If SCL remains “1” and SDA transfers from “1” to “0”, it means a “Start condition” is occurred and access is started. If SCL remains “1” and SDA transfers from “0” to “1”, it means a “Stop condition” is occurred and access is stopped. It becomes repeated START condition (Sr) the START condition enters again although the STOP condition is not done. SDA SCL S START Condition Sr P Repeated START Condition STOP Condition Fig.6 START-STOP-Repeated START conditions www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/17 2009.09 - Rev.A Technical Note BU1850MUV 2-4 Acknowledge After start condition is occurred, 8 bits data will be transferred. SDA is latched by the rising edge of SCL. Then the “Master” opens SDA to “1” and “Slave” de-asserts SDA to “0” as an “Acknowledge” returned. Fig.7 Acknowledge 2-5 Writing protocol Register address is transferred after one byte of slave address with R/W bit. The 3rd byte data is written to internal register which defined by the 2nd byte. However, when the register address increased to the final address (13h), it will be reset to (00h) after the byte transfer. S X X X X X X X 0 A X X X A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A Slave address Register address Transmit from slave data data R/W=0(write) Transmit from master D7 D6 D5 D4 D3 D2 D1 D0 A P Register address increment Register address increment A=acknowledge A=not acknowledge S=Start condition P=Stop condition Fig.8 Writing protocol www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/17 2009.09 - Rev.A Technical Note BU1850MUV 2-6 Reading protocol After Writing the slave address and Read/Write commend bits, the next byte is read. The reading register address is next of previous accessed address. Therefore, the data is read with address increment. When the address in increased to the last, the following read address will be reset to (00h). Fig.9 Readout protocol 2-7 Complex reading protocol After the specifying the internal register address, a repeated START condition occurs and the direction of data transfer is changed then reading access is done. Therefore, the data is read followed by address increment. If the address is increased to the last, it will be reset to (00h). S X X X X X X X 0 A X X X A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A Slave address Register address Slave address R/W=0(write) R/W=1(read) D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P data Transmit from master data Register address increment Transmit from slave Register address increment A=acknowledge A=not aclnowledge S=Start condition P=Stop condition Sr=Repeated Start condition Fig.10 Complex reading protocol 2-8 Illegal access of I2C The data accessed at that time is annulled, and access it again. The illegal accesses are as follows. The START condition and the STOP condition are continuously generated. When the Slave address and the R/W bit is written, repeated START condition and the STOP condition are generated. Repeated START condition and the STOP condition are generated while writing data. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/17 2009.09 - Rev.A Technical Note BU1850MUV 3. Register configuration The address is increased one by one when data is continuously written. When the final address is set to 13h, then the next address 00h will be written. By making XRST “Low”, the setting register value will be initialed shown in following register map. 3-1 Register map Addr Init Type D7 D6 D5 D4 D3 D2 D1 D0 00h - - reserved reserved reserved reserved reserved reserved reserved reserved 01h - - reserved reserved reserved reserved reserved reserved reserved reserved 02h - - reserved reserved reserved reserved reserved reserved reserved reserved 03h - - reserved reserved reserved reserved reserved reserved reserved reserved 04h 00h R/W RESET reserved reserved reserved reserved reserved reserved reserved 05h - - reserved reserved reserved reserved reserved reserved reserved reserved 06h - - reserved reserved reserved reserved reserved reserved reserved reserved 07h - - reserved reserved reserved reserved reserved reserved reserved reserved 08h 00h R/W INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 09h - - reserved reserved reserved reserved reserved reserved reserved reserved 0Ah - - reserved reserved reserved reserved reserved reserved reserved reserved 0Bh - - reserved reserved reserved reserved reserved reserved reserved reserved 0Ch - - reserved reserved reserved reserved reserved reserved reserved reserved 0Dh - - reserved reserved reserved reserved reserved reserved reserved reserved 0Eh - - reserved reserved reserved reserved reserved reserved reserved reserved 0Fh - - reserved reserved reserved reserved reserved reserved reserved reserved 10h 00h R GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 11h 00h R/W GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 GPO0 12h 00h R/W WRSEL7 WRSEL6 WRSEL5 WRSEL4 WRSEL3 WRSEL2 WRSEL1 WRSEL0 13h 00h R/W XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 ※ Do not write reserved resisters excluding "0". 10h address register is disregarded even if it is written. 3-2 Resister function ※ n is the number of GPIO[7:0] ports. Symbol Addr Description RESET 04h The register is returned to an initial value by writing "1". This register value is returned to "0". GPIn register is not initialized. INTENn 08h Interrupt of GPIOn port is enabled by "1". It is masked by "0". GPIn 10h Read GPIOn port. Writing is disregarded. GPOn 11h Output value of GPIOn port. WRSELn 12h GPIOn port is input by "0" and output by "1". XPDn 13h Pull-down of GPIOn port is on by "0" and off by "1". GPIOn should be input. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/17 2009.09 - Rev.A Technical Note BU1850MUV 4. GPIO-Interrupt 4-1 GPIO configuration As the default value, GPIO[7:0] ports are input and Pull-down. At this time, WRSELn is "0" and XPDn is "0". (n is the number of GPIO[7:0] ports.) Refer to the following for the configuration of GPIO. Register State of GPIO GPOn WRSELn XPDn Input, Pull-down ON * 0 0 Input, Pull-down OFF * 0 1 Output, H drive 1 1 * Output, L drive 0 1 * 0 0 1 ※1 Output, Hi-Z -1 ※1 Make external Pull-up the terminal potential which is the potential of VVDDIO or more. About GPIO port not used When making it to the output, open it. When making it to the input, do not open it. It is forced by "0" or Pull-down on. When interrupt is enabled, mask INTEN register in which the port is not used to "0". 4-2 Interrupt configuration When interrupt is generated, L is output from XINT port. The default value is Hi-Z. Make it Pull-up. For the default value, interrupt is masked with INTEN register "0". The bit to be used is made "1", and the mask is released. WRSEL register should be "0"(input). 4-3 Write to GPIO port After setting the internal register address, the data from master is written from MSB. After Acknowledge is returned, the value of each GPIO port will be changed. When the register is written, Write Configuration Pulse is generated according to the timing of Acknowledge. SCL 1 SDA S X 2 X 3 4 X 5 X X 6 X Start Condition 7 X 8 0 Write 9 Ack MSB Reg Address LSB Ack MSB Data1 (GPO[7:0]) LSB Ack P Acknowledge From Slave Stop Condition Acknowledge From Slave Write Configuration Pulse Data1 Valid GPIO[7:0] tDV SCL SDA 1 S X 2 X Start Condition 3 X 4 X 5 X 6 X 7 X 8 0 Write 9 Ack MSB Reg Address Acknowledge From Slave LSB Ack MSB Data1 (GPO[7:0]) Acknowledge From Slave LSB Ack MSB WRSEL = Write Mode LSB Ack P Acknowledge From Slave Stop Condition Write Configuration Pulse Data1 Valid GPIO[7:0] tDV Fig.11 Write to GPIO port www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/17 2009.09 - Rev.A Technical Note BU1850MUV 4-4 Read from GPIO port After writing of the Slave address and R/W bits, reading GPIO port is begun from the following byte. The data that had been being fixed between the following Acknowledge after Acknowledge is taken into the GPI register, and it is transmitted to Master. All ports that are the input by WRSEL register are read to the GPI register according to the timing of Read Configuration Pulse. Therefore, the data of each bit that SDA transmits is the GPI register value taken immediately before that. SCL S SDA 1 2 3 4 5 6 7 8 9 X X X X X X X 1 Ack D1 [6] D1 [5] D1 [4] D2 [3] D2 [2] D2 [1] D2 [0] NA P Stop Condition No Acknowledge From Master Acknowledge From Slave Read Start Condition D1 [7] Read Configuration Pulse GPI[7:0] Reg D2 D1 D1 GPIO[7:0] tDS D2 tDS tDH tDH Fig.12 Read from GPIO port 4-5 Interrupt Valid/Reset If GPIO port becomes different from the GPIn register (default is "0"), XINT port is changed from "1" into "0". It becomes "1" to release "0" of XINT port after acknowledge by reading GPI register. Because the value of GPIO port is reflected in the output as it is and is not latched, XINT becomes "1" again if the port returns to the same value. If the ports with INTEN register "1" are different even by one, XINT becomes "0". If it is distinguished which GPIO port changes, it is necessary to keep the GPI register value on the master side and compare with the value that is read after XINT is asserted. SCL SDA S 1 2 3 4 5 6 7 8 9 X X X X X X X 1 Ack Read Start Condition MSB Data2 (GPI[7:0]) LSB NA P Stop Condition Acknowledge From Slave No Acknowledge From Master GPIOn Data1 GPIn Reg Data1 Data3 Data2 Data2 Data2 XINT tIV tIR tIV tIR Fig.13 Interrupt Valid/Reset www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/17 2009.09 - Rev.A Technical Note BU1850MUV ●Electrical Specification 1. DC characteristics VVDD=1.8V，VVDDIO=1.8V，Topr=25℃ Specification Parameter Symbol Unit Min Typ Max Conditions Input H Voltage1 VIH1 0.7xVVDDIO - 3.6 V Input L Voltage1 VIL1 -0.2 - 0.3xVVDDIO V Input H Voltage2 VIH2 0.7xVVDD - 3.6 V SCL, SDA, Input L Voltage2 VIL2 -0.2 - 0.3xVVDD V SCL, SDA, XRST, ADR Input H Voltage3 VIH3 0.7xVVDD - VVDD+0.2 V XRST, ADR Input H Current1 (3V Tolerant) IIH1 -1 - 1 A VIN=3.6V*1 Input H Current2 IIH2 -1 - 1 A VIN=1.8V, XRST,ADR IIL -1 - 1 A VIN=0V*1, XRST,ADR Output H Voltage1 VOH1 0.75xVVDDIO - - V IOH=-2mA, GPIO[7:0] Output L Voltage1 VOL1 - - 0.25xVVDDIO V IOL=2mA, GPIO[7:0] Output H Voltage2 VOH2 VVDDIO-0.25 - - V IOH=-0.2mA, GPIO[7:0] Output L Voltage2 VOL2 - - 0.25 V IOL=0.2mA, GPIO[7:0] Output L Voltage3 VOL3 - - 0.3 V IOL=3mA, SDA, XINT GPIO[7:0] Input L Current *1 XINT(Hi-Z), XRST, SCL, SDA(IN), ADR, GPIO[7:0](IN, Pull-down OFF) 2. Circuit Current VVDD=1.8V，VVDDIO=1.8V，Topr=25℃ Specification Parameter Symbol Unit Min Typ Max Condition Power Down Current (VDD) IPD1 - - 1.0 A Power Down Current (VDDIO) IPD2 - - 1.0 A ISTBY1 - - 3.0 A Standby Current (VDDIO) ISTBY2 - - 1.0 A Operating Current1 (VDD) IOP1 - 14 25 A I2C 400kHz 100% traffic density*1 Operating Current1 (VDD) IOP2 - 2 8 A I2C 400kHz 1% traffic density*2 Standby Current (VDD) *1 *2 XRST=VSS XRST=VDD, SCL=VDD, SDA=VDD All GPIO ports are output, and they repeat 01010101 and 10101010. The period when I2C did not operate was inserted in *1 pattern by 99%. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/17 2009.09 - Rev.A Technical Note BU1850MUV 3. I2C AC characteristics State （Repeated） START BIT 7 BIT 6 tSU;STA tLOW tHIGH Ack STOP 1/fSCLK SCL SDA tSU;STO tSU;DAT tHD;DAT tBUF tHD;STA Fig.14 I2C AC Timing VVDD=1.8V，VVDDIO=1.8V，Topr=25℃ Specification Parameter Symbol Unit Min Typ Max SCL Clock Frequency fSCLK - - 400 kHz Bus free time tBUF 1.3 - - s (Repeated)START Condition Setup Time tSU;STA 0.6 - - s (Repeated)START Condition Hold Time tHD;STA 0.6 - - s SCL Low Time tLOW 1.3 - - s SCL High Time tHIGH 0.6 - - s Data Setup Time tSU;DAT 100 - - s Data Hold Time tHD;DAT 0 - - ns STOP Condition Setup Time tSU;STO 0.6 - - s www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/17 Conditions 2009.09 - Rev.A Technical Note BU1850MUV 4. GPIO AC Characteristics State BIT 1 BIT 0 Ack BIT 1 BIT 0 Ack SCL tDV GPIO[7:0](Output) tDS tDH GPIO[7:0](Input) tIV tIR XINT Fig.15 GPIO AC timing VVDD=1.8V，VVDDIO=1.8V，Topr=25℃ Specification Parameter Symbol Unit Min Typ Max Output Data Valid Time tDV - - 0.8 s Input Data Setup Time tDS 100 - - ns Input Data Hold Time tDH 0.8 - - s Interrupt Valid Time tIV - - 5 s Interrupt Reset Time tIR - - 5 s Conditions See Fig.11 See Fig.12 See Fig.13 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/17 2009.09 - Rev.A Technical Note BU1850MUV 5. Startup sequence tVDD tVDD tVDD VDD, VDDIO tRV tRWAIT XRST tRWAIT tVDD tI2CWAIT tI2CWAIT SCL SDA Fig.16 Start Sequence timing VVDD=1.8V，VVDDIO=1.8V，Topr=25℃ Specification Parameter Symbol Min Typ Max Unit Conditions VDD Stable Time tVDD - - 5 ms VDD and VDDIO are ON at the same time. Reset Wait Time tRWAIT 0 - - s XRST controlling *1 Reset Valid Time tRV 10 - - s tI2CWAIT 10 - - s I2C Wait Time *1 Even if XRST port is not used, it operates because Power On Reset is built in. In this case, connect XRST port with VDD on the set PCB. Note) At VDD=0V, when SCL port is changed from 0V to 0.5V or more, SCL port pulls the current. It is same in SDA, XINT, and GPIO[7:0] ports of 3V tolerant I/O. (VDDIO=0V in case of GPIO[7:0] ports) VDD 0V Port (2kΩ Pull-Up) Port Pull Current 3V 0V 0.1～1mA 2～3ms Fig.17 Port operating at VDD=0V www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 15/17 2009.09 - Rev.A Technical Note BU1850MUV ●Application circuit example 1.8V 3.0V 0.1uF IN XINT SCL SCL SDA SDA GPIO7 GPIO6 ADR XINT GPIO5 GPIO4 GPIO3 GPIO2 SCL SDA VSS VDD XRST VDDIO VSS 0.1uF 0.1uF BU1850MUV ADR BU1850MUV XRST MPU VDD 0.1uF VDDIO 1.8V GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO1 GPIO0 GPIO0 Other I2C Devices Fig.18 Application circuit example www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 16/17 2009.09 - Rev.A Technical Note BU1850MUV ●Ordering part number B U 1 Part No. 8 5 0 M Part No. U V Package MUV: VQFN016V3030 - E 2 Packaging and forming specification E2: Embossed tape and reel VQFN016V3030 <Tape and Reel information> 3.0±0.1 3.0±0.1 0.5 5 13 0.75 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 4 16 8 12 E2 9 1.4±0.1 0.4±0.1 1 3000pcs (0.22) 1.4±0.1 +0.03 0.02 –0.02 1.0MAX S C0.2 Embossed carrier tape Quantity Direction of feed 1PIN MARK 0.08 S Tape +0.05 0.25 –0.04 1pin (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 17/17 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.09 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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