ROHM BD6029GU_10

System Power Supply ICs for CCD Camera of Mobile Phones
Power Supply
for CCD Camera Module
BD6029GU
No.10033EAT01
●Description
BD6029GU is system power supply LSI for CCD camera that supplies all voltage sources for CCD camera. This IC has Step
up DC/DC converter and LDO for CCD sensor, Inverted DC/DC converter for CCD sensor, Series Regulators for DSP 3ch,
CCD I/O 1ch and V-driver 1ch. Each output voltage has an adjustable to the register, and this IC can correspond to various
CCD modules. A necessary power supply for CCD camera is integrated into 1chip, and it contributes to space saving.
BD6029GU achieves compact size with the chip size package.
●Features
1) The BD6029GU is equipped with all voltage sources for CCD camera.
2) Each output has an adjustable voltage, and hence this IC can correspond to various CCD modules.
3) The BD6029GU has 3ch voltage regulators which have adjustable voltage for DSP, and hence
BD6029GU can correspond to various DSP chip sets.
4) The BD6029GU has other 2ch voltage regulators for CCD I/O and V-driver.
2
5) The BD6029GU is controlled by I C BUS format.
6) The BD6029GU employs 4.35mm2 chip size package, so this IC achieves compact size.
●Functions
1) Step up DC/DC converter and LDO for CCD sensor (+15V/+14.5V/+13V)
2) Inverted DC/DC converter for CCD sensor (-8V/-7.5V/-7V)
3) 5ch Series Regulator
REG1 : 1.2V/1.8V, Iomax=150mA
REG2 : 2.7V/3.0V/3.3V, Iomax=150mA
REG5 : 1.8V/3.0V, Iomax=150mA
REG6 : 3.0V/3.1V/3.2V/3.3V, Iomax=200mA
REGA: 1.8V/3.0V/3.3, Iomax=150mA
2
4) Correspondence to I C BUS format
5) Thermal shutdown (Auto-reset type)
6) VCSP85H4 small package (chip size package)
●Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Ratings
Unit
Maximum Applied voltage 1
(Note 1)
VMAX1
20
V
Maximum Applied Voltage 2
(Note 2)
VMAX2
18
V
Maximum Applied Voltage 3
(Note 3)
VMAX3
-13.5
V
Maximum Applied Voltage 4
(Note 4)
VMAX4
6
V
Power Dissipation
(Note 5)
Pd
1925
mW
Operating Temperature Range
Topr
-30 ~ +85
°C
Storage Temperature Range
Tstg
-55 ~ +125
°C
(Note 1) SW，VPLUS1，VPLUS2 pin
(Note 2) VDD3 pin
(Note 3) VDD4 pin
(Note 4) Except Note1~Note3 pin
(Note 5) Power dissipation deleting is 15.4mW/ oC, when it’s used in over 25 oC.
(It’s deleting is on the board that is ROHM’s standard)
●Recommended Operating Conditions (VBAT≥VIO, Ta=-30~85 °C)
Parameter
Symbol
VBAT input voltage
VIO pin voltage
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© 2010 ROHM Co., Ltd. All rights reserved.
Limits
Unit
VBAT
2.7 ~ 5.5
V
VIO
1.62 ~ 3.3
V
1/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V/3.0V)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
Circuit Current
VBAT Circuit current 1
IBAT1
-
0.1
3.0
μA
RST=0V, VIO=0V
VBAT Circuit current 2
IBAT2
-
0.5
3.0
μA
RST=0V
VBAT Circuit current 3
IBAT3
-
90
135
μA
REG1:ON, Io=0mA
VBAT Circuit current 4
IBAT4
-
90
135
μA
REG2:ON, Io=0mA
VBAT Circuit current 5
IBAT5
-
90
135
μA
REG5:ON, Io=0mA
VBAT Circuit current 6
IBAT6
-
90
135
μA
REG6:ON, Io=0mA
VBAT Circuit current 7
IBAT7
-
90
135
μA
VBAT Circuit current 8
IBAT8
-
9
14
mA
REGA:ON, Io=0mA
SWREG3:ON,REG3:ON,
SWREG4:ON, Io=0mA
Output voltage 1
VoPD1
-
17.0
-
V
Io=60mA
Output voltage 2
VoPD2
-
16.5
-
V
Io=60mA
Output voltage 3
VoPD3
-
14.5
-
V
Io=60mA
Output current
IoPD
-
-
60
mA
Efficiency
EffPD
-
(80)
-
%
Oscillator frequency
foscPD
0.8
1.0
1.2
MHz
SW saturation voltage
VsatPD
-
200
400
mV
Over voltage protection
OvPD
18.0
18.5
19.0
V
Over current protection
OcPD
1.0
1.25
1.5
A
Output voltage 1
VoND1
-8.4
-8.0
-7.6
V
Io=100mA
Output voltage 2
VoND2
-7.9
-7.5
-7.1
V
Io=100mA
Output voltage 3
VoND3
-7.4
-7.0
-6.6
V
Io=100mA
Output current
IoND
-
-
100
mA
Efficiency
EffND
-
(75)
-
%
foscND
0.8
1.0
1.2
MHz
Over voltage protection
OvND
-10.5
-10.0
-9.5
V
Over current protection
OcND
1.0
1.25
1.5
A
ROFFN
0.5
1.0
1.5
kΩ
SWREG3
SWREG4
(Step up DC/DC)
(Note 6)
Io=60mA
(Note 6)
Iin=200mA
(Inverted DC/DC)
Oscillator frequency
Electric discharge resister at OFF
(Note 6)
Io=100mA
(Note 6)
(Note 6) The power efficiency changes with the fluctuation of external parts and the board mounting condition.
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2/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V/3.0V)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
REG1
(1.2V/1.8V LDO)
Output voltage 1
Vo11
1.140
1.20
1.260
Output voltage 2
Vo12
1.746
1.80
1.854
V
Io1
-
-
150
mA
Load stability
∆Vo11
-
10
60
mV
Io=1~150mA, Vo=1.8V
Input stability
∆Vo12
-
10
60
mV
RR1
-
65
-
dB
Ilim01
-
200
400
mA
VBAT=3.2~4.5V, Io=100mA, Vo=1.8V
f=100Hz, Vin=200mVp-p, Vo=1.2V
Io=50mA, BW=20Hz~20kHz
Vo=0V
ROFF1
-
1.0
1.5
kΩ
Output voltage 1
Vo21
2.619
2.70
2.781
V
Io=150mA
Output voltage 2
Vo22
2.910
3.00
3.090
V
Io=150mA
Output voltage 3
Vo23
3.201
3.30
3.399
V
Io=150mA
Output current
Ripple rejection ratio
Current over load limiter
Discharge resister at OFF
REG2
V
Io=150mA
Io=150mA
Vo=1.8V
(2.7V/3.0V/3.3V LDO)
Output current
Io2
-
-
150
mA
I/O voltage difference
Vsat2
-
0.2
0.3
V
Load stability
∆Vo21
-
10
60
mV
Io=1~150mA, Vo=2.7V
Input stability
∆Vo22
-
10
60
mV
RR2
-
60
-
dB
Ilim02
-
200
400
mA
VBAT=3.4~4.5V, Io=50mA, Vo=2.7V
f=100Hz, Vin=200mVp-p, Vo=2.7V
Io=50mA, BW=20Hz~20kHz
Vo=0V
ROFF2
-
1.0
1.5
kΩ
Output voltage 1
Vo31
14.05
14.5
14.95
V
Io=60mA
Output voltage 2
Vo32
14.55
15.0
15.45
V
Io=60mA
Output voltage 3
Vo33
12.55
13.0
13.45
V
Io=60mA
I/O voltage difference
Vsat3
-
0.32
0.5
V
VPLUS2=11V, Io=60mA
Load stability
∆Vo31
-
20
80
mV
Io=1～60mA
Input stability
Output voltage temperature
fluctuation rate
Output ripple voltage
∆Vo32
-
10
60
mV
VPLUS2=16.5～17.5V, Io=60mA
∆Vo33
-
±100
-
ppm/°C Ta=-30℃～85℃, Io=60mA
RR3
-
-
3
mVp-p Io=60mA, BW=20Hz～80kHz(Note 7)
Ilim03
-
100
-
mA
ROFF3
0.5
1.0
1.5
kΩ
Ripple rejection ratio
Current over load limiter
Discharge resister at OFF
REG3
VBAT=2.5V, Io=150mA, Vo=2.7V
(15V/14.5V/13V LDO)
Current over load limiter
Discharge resister at OFF
(Note 7)
Vo=2.7V
Vo=0V
BW: Band width
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© 2010 ROHM Co., Ltd. All rights reserved.
3/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VIO=1.8V/3.0V)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
REG5
(1.8V/3.0V LDO)
Output voltage 1
Vo51
1.746
1.80
1.854
Output voltage 2
Vo52
2.910
3.00
3.090
V
Io5
-
-
150
mA
Output current
V
Io=150mA
Io=150mA
Vo=1.8V
I/O voltage difference
Vsat5
-
0.2
0.3
V
Load stability
∆Vo51
-
10
60
mV
Io=1~150mA, Vo=1.8V
Input stability
∆Vo52
-
10
60
mV
RR5
-
65
-
dB
VBAT=3.3~4.5V, Io=80mA, Vo=1.8V
f=100Hz, Vin=200mVp-p, Vo=1.8V
Io=50mA, BW=20Hz~20kHz
Vo=0V
Ripple rejection ratio
Current over load limiter
VBAT=2.5V, Io=150mA, Vo=3.0V
Ilim05
-
200
400
mA
ROFF5
-
1.0
1.5
kΩ
Output voltage 1
Vo61
2.910
3.00
3.090
V
Io=200mA
Output voltage 2
Vo62
3.007
3.10
3.193
V
Io=200mA
Output voltage 3
Vo63
3.104
3.20
3.296
V
Io=200mA
Output voltage 4
Vo64
3.201
3.30
3.399
V
Io=200mA
Io6
-
-
200
mA
Discharge resister at OFF
REG6
(3.0V/3.1V/3.2V/3.3V LDO)
Output current
Vo=3.0V
I/O voltage difference
Vsat6
-
0.2
0.3
V
Load stability
∆Vo61
-
10
60
mV
Io=1~200mA, Vo=3.0V
Input stability
∆Vo62
-
10
60
mV
RR6
-
60
-
dB
VBAT=3.4~4.5V, Io=200mA, Vo=3.0V
f=100Hz, Vin=200mVp-p, Vo=3.0V
Io=50mA, BW=20Hz~20kHz
Vo=0V
Ripple rejection ratio
Current over load limiter
VBAT=2.5V, Io=200mA, Vo=3.0V
Ilim06
-
250
500
mA
ROFF6
-
1.0
1.5
kΩ
Output voltage 1
VoA1
1.746
1.80
1.854
V
Io=150mA
Output voltage 2
VoA2
2.910
3.00
3.090
V
Io=150mA
Output voltage 3
VoA3
3.201
3.30
3.399
V
Io=150mA
IoA
-
-
150
mA
Discharge resister at OFF
REGA (1.8V/3.0V/3.3V LDO)
Output current
I/O voltage difference
Vo=1.8V
VsatA
-
0.2
0.3
V
Load stability
ΔVoA1
-
10
60
mV
Io=1~150mA, Vo=1.8V
Input stability
ΔVoA2
-
10
60
mV
RRA
-
65
-
dB
Current over load limiter
Ilim0A
-
200
400
mA
VBAT=3.4~4.5V, Io=150mA, Vo=1.8V
f=100Hz, Vin=200mVp-p, Vo=1.8V
Io=50mA, BW=20Hz~20kHz
Vo=0V
Discharge resister at OFF
ROFFA
-
1.0
1.5
kΩ
Ripple rejection ratio
VBAT=2.5V, Io=150mA, Vo=3.0V
I2C Input (RST, SDA, SCL)
LOW level input voltage
VIL
-0.3
-
0.25VIO
V
HIGH level input voltage
Hysteresis of Schmitt trigger
input
LOW level output voltage
(SDA) at 3mA sink current
VIH
0.75VIO
-
VIO+0.3
V
Vhys
0.05VIO
-
-
V
VOL
0
-
0.30
V
li
-10
-
10
μA
Input current each I/O pin
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4/19
input voltage between 0.1 VIO and
0.9 VIO
2010.03 - Rev.A
Technical Note
BD6029GU
●Power Dissipation (On the ROHM’s standard board)
2
1925mW
1.8
Power Dissipation Pd （W)
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
Ta(℃)
Fig.1 Power Dissipation
Information of the ROHM’s standard board
Material : glass-epoxy
Size
: 50mm×58mm×1.75mm (8 Layer)
Pattern of the board : Refer to P.18
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© 2010 ROHM Co., Ltd. All rights reserved.
5/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Block Diagram / Application Circuit example
Battery
1μF(6.3V)
F
RB521S-30
VPLUS2
GNDP
GNDPS
VPLUS1
1μF(25V)
SW
10μH
MONR1
2.2μF(6.3V)
MONR2
F
VBAT1
VBAT2
0.08Ω
VBAT7
-
S
R
Q
VBAT6
+
Driver
VBAT5
-
1μF(16V)
REG1
REG2
T3
2.7V / 3.0V
/ 3.3V
Iomax=150mA
OSC
+
T1
-
-
1μF(6.3V)
VDD2
1μF(6.3V)
Feed Back
REG5
+
T4
VDD5
1.8V / 3.0V
Iomax=150mA
SWREG3
REGA
VREF
VDD1
1.2V / 1.8V
Iomax=150mA
+
Control
T2
VDD3
REG3
15V / 14.5V
/13V
Iomax=60mA
Over Voltage Limit
VBAT4
Current Sense
VBAT3
1μF(6.3V)
AVDD
1.8V / 3.0V
/ 3.3V
Iomax=150mA
VREF
0.1μF(6.3V)
REG6
1μF(6.3V)
VDD6
3.0V / 3.1V
/ 3.2V / 3.3V
Iomax=200mA
VIO
CCD
Camera
Module
1μF(6.3V)
MVDD1
RST
MVDD2
CONT
SDA
CPU
2
IC
SWREG4
VBATN2
Current Sense
SCL
-
VBATN1
0.08Ω
+
OSC
TESTO1
+
-
TESTO2
SENSN1
2.2μF(6.3V)
SENSN2
Control
R
TRSW
Q
QS5U26
Driver
S
TESTI1
Over Voltage Limit
-
TESTI2
+
-8V / -7.5V
/ -7V
Iomax=100mA
GND7
+
GND6
GND5
GND4
GND3
GND2
GND1
Pin Connection
1μF(16V)
VDD4
-
TSD
4.7μH
T1~T4, TESTI1, TESTI2
TEST01, TEST02, MVDD1, MVDD2
Output of unused LDO
MONR1-MONR2 short
MVDD1-MVDD2 short
: GND short
: Open
: Open
Fig.2 Block Diagram / Application Circuit example
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6/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Pin Configuration ［Bottom
View］
H
T4
VDD3
VPLUS1
GNDP
MONR2
SW
GND6
T3
G
TESTI1
TESTI2
VPLUS2
GNDPS
MONR1
VBAT5
TESTO2
AVDD
F
RST
VIO
VBAT4
VDD5
E
GND7
SDA
VREF
GND5
D
VDD2
SCL
VBAT3
VDD1
C
VBAT6
VBAT7
VBAT2
VDD6
B
MVDD2
MVDD1
VBATN1
SENSN2
VBAT1
GND3
TESTO1
GND4
A
T1
GND1
VBATN2
SENSN1
TRSW
GND2
VDD4
T2
1
2
3
4
5
6
7
8
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© 2010 ROHM Co., Ltd. All rights reserved.
7/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Package Outline
VCSP85H4 (BU6029GU)
(unit:mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
8/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Pin Functions
No
Pin
No
Pin
Name
1
B5
VBAT1
2
C7
VBAT2
3
D7
VBAT3
4
F7
VBAT4
5
G6
VBAT5
6
C1
VBAT6
7
C2
VBAT7
8
A1
T1
9
A8
T2
10 H8
T3
11 H1
T4
12 E7
VREF
13
F2
VIO
14
F1
RST
15 E2
SDA
16 D2
SCL
17 A2
GND1
18 A6
GND2
19 B6
GND3
20 B8
GND4
21 E8
GND5
22 H7
GND6
23 E1
GND7
24 H6
SW
25 H5 MONR2
26 G5 MONR1
27 H4
GNDP
28 G4 GNDPS
29 H3 VPLUS1
30 G3 VPLUS2
31 H2
VDD3
32 D8
VDD1
33 D1
VDD2
34
F8
VDD5
35 G8
AVDD
36 C8
VDD6
37 B2 MVDD1
38 B1 MVDD2
39 B7 TESTO1
40 G7 TESTO2
41 G1
TESTI1
42 G2
TESTI2
43 A3 VBATN2
44 B3 VBATN1
45 A4 SENSN1
46 B4 SENSN2
47 A5
TRSW
48 A7
VDD4
Total: 48Pin
I/O
Input
Level
O
I
I
I
O
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
O
O
VIO
VIO
VIO
-
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© 2010 ROHM Co., Ltd. All rights reserved.
ESD Diode
For
For
Power
GND
GND
GND
GND
GND
GND
GND
GND
VBAT
GND
GND
GND
VBAT
GND
VBAT
GND
VBAT
GND
VIO
GND
VIO
GND
VIO
GND
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
GND
GND
VPLUS2 GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
VIO
GND
VIO
GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
VBAT
GND
GND
-
Functions
Initial
Conditions
Battery is connected
Battery is connected
Battery is connected
Battery is connected
Battery is connected
Battery is connected
Battery is connected
Test pin
Test pin
Test pin
Test pin
Reference voltage output
Power supply for logic
Reset input
I2C data input
I2C clock input
Ground
Ground
Ground
Ground
Ground
Ground
Ground
SWREG3 coil switching pin
SWREG3 current sense pin
SWREG3 current sense pin
SWREG3 current sense pin
SWREG3 current sense pin
SWREG3 boost voltage feedback pin
Power supply input for REG3 (15.5V/14.5V/13V LDO)
REG3 (15.5V/14.5V/13V LDO) output pin
REG1 (1.2V/1.8V LDO) output pin
REG2 (2.7V/3.0V/3.3V LDO) output pin
REG5 (1.8V/3.0V LDO) output pin
REGA (1.8V/3.0V/3.3V LDO) output pin
REG6 (3.0V/3.1V/3.2V/3.3V LDO) output pin
NC
NC
Test pin
Test pin
Test pin
Test pin
Battery is connected (SWREG4 current sense)
Battery is connected (SWREG4 current sense)
SWREG4 current sense pin
SWREG4 current sense pin
SWREG4 switching Tr. drive pin
SWREG4 (-8V/-7.5V/-7V) output pin
0V output
Stop operating
0V output
0V output
0V output
0V output
0V output
0V output
Stop operating
0V output
9/19
2010.03 - Rev.A
Technical Note
BD6029GU
●I2C BUS format
2
The writing/reading operation is based on the I C slave standard.
◦ Slave address
A7
A6
0
0
A5
0
A4
1
A3
0
A2
0
A1
1
R/W
1/0
◦ Bit Transfer
SCL transfers 1-bit data during H. SCL cannot change signal of SDA during H at the time of bit transfer. If SDA changes
while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal.
SDA
SCL
data line
Stable; data valid
change of
data
allowed
◦ START and STOP condition
2
When SDA and SCL are H, data is not transferred on the I C- bus. This condition indicates, if SDA changes from H to L
while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL
has been H, it will become STOP (P) conditions and an access end.
SDA
SCL
S
P
START condition
STOP condition
◦ Acknowledge
It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and
a receiver returns the acknowledge signal by setting SDA to L.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL
S
1
2
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9
clock pulse for
acknowledgement
START condition
© 2010 ROHM Co., Ltd. All rights reserved.
8
10/19
2010.03 - Rev.A
Technical Note
BD6029GU
◦ Writing protocol
A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is
carried out automatically. However, when a register address turns into the last address(07h), it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.
* 1
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
slave address
register address
* 1
D7 D6 D5 D4 D3 D2 D1 D0 A P
DATA
DATA
R/W=0(write)
register address
increment
register address
increment
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing
from master to slave
from slave to master
◦ Reading protocol
It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following
address accessed at the end, and the data of the address that carried out the increment is read after it. If an address turns
into the last address(07h), the next byte will read out 00h. After the transmission end, the increment of the address is
carried out.
S X X X X X X X
1 A D7 D6 D5 D4 D3 D2 D1 D0 A
slave address
D7 D6 D5 D4 D3 D2 D1 D0 A P
DATA
DATA
register address
increment
register address
increment
R/W=1(read)
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
from master to slave
from slave to master
◦ Multiple reading protocols
After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The
data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte will
read out 00h. After the transmission end, the increment of the address is carried out.
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A
slave address
register address
slave address
R/W=0(write)
R/W=1(read)
D7 D6 D5 D4 D3D2 D1D0 A
DATA
D7D6 D5D4D3D2D1D0 A P
DATA
register address
increment
register address
increment
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
Sr=repeated START condition
from master to slave
from slave to master
As for reading protocol and multiple reading protocols, please do A(not acknowledge) after doing the final reading
operation. It stops with read when ending by A(acknowledge), and SDA stops in the state of Low when the reading data of
that time is 0. However, this state returns usually when SCL is moved, data is read, and A(not acknowledge) is done.
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© 2010 ROHM Co., Ltd. All rights reserved.
11/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Timing Diagram
SDA
tf
t LOW
tr
t SU;DAT
tf
t BUF
tr
t HD;STA
t SP
SCL
S
t HD;STA
t SU;STO
t SU;STA
t HD;DAT
t HIGH
S
P
Sr
●Electrical Characteristics (Unless otherwise specified, Ta=25oC, VBAT=3.6V, VIO=1.8V/3.0V)
Standard-mode
Fast-mode
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
I2C BUS format
SCL clock frequency
fSCL
0
-
100
0
-
400
kHz
LOW period of the SCL clock
tLOW
4.7
-
-
1.3
-
-
μs
HIGH period of the SCL clock
tHIGH
4.0
-
-
0.6
-
-
μs
Hold time (repeated) START condition
After this period, the first clock is generated
tHD;STA
4.0
-
-
0.6
-
-
μs
Set-up time for a repeated START condition
tSU;STA
4.7
-
-
0.6
-
-
μs
Data hold time
tHD;DAT
0
-
3.45
0
-
0.9
μs
Data set-up time
tSU;DAT
250
-
-
100
-
-
ns
Set-up time for STOP condition
tSU;STO
4.0
-
-
0.6
-
-
μs
Bus free time between a STOP
and START condition
tBUF
4.7
-
-
1.3
-
-
μs
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© 2010 ROHM Co., Ltd. All rights reserved.
12/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Register List
-
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
Address
b4
b3
b2
b1
b0
D0
Register data
Function
8bit
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
00h
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
01h
0
0
0
0
0
0
0
1
-
02h
0
0
0
0
0
0
1
0
03h
0
0
0
0
0
0
1
1
-
04h
0
0
0
0
0
1
0
0
05h
0
0
0
0
0
1
0
06h
0
0
0
0
0
1
07h
0
0
0
0
0
08h
0
0
0
0
1
REGAPD REG6PD REG5PD
SWREG4 SWREG4
VSEL1
VSEL0
SFTRST Software reset
SWREG4
REG3PD REG2PD REG1PD Power down
PD
REG3
VSEL1
REG3
VSEL0
REG2
VSEL1
REG2
VSEL0
REG1
VSEL1
REG1
VSEL0
Output Voltage
Setting 1
-
REGA
VSEL1
REGA
VSEL0
REG6
VSEL1
REG6
VSEL0
REG5
VSEL1
REG5
VSEL0
Output Voltage
Setting 2
-
-
-
-
-
-
-
-
(reserved)
1
-
-
-
-
-
-
-
-
(reserved)
1
0
-
-
-
-
-
-
-
-
(reserved)
1
1
1
reserved
for TEST
0
0
0
reserved
for TEST
●Register Map
Address 00h <Software reset>
Function
BIT
Name
Initial
0
1
D7
-
-
-
-
D6
-
-
-
-
D5
-
-
-
-
D4
-
-
-
-
D3
-
-
-
-
D2
-
-
-
-
D1
-
-
-
-
D0
SFTRST
0
Reset cancel
Reset
Address 01h <Power down>
Function
BIT
Name
Initial
0
1
D7
-
-
-
-
D6
REGAPD
0
REGA power OFF
REGA power ON
D5
REG6PD
0
REG6 power OFF
REG6 power ON
D4
REG5PD
0
REG5 power OFF
REG5 power ON
D3
SWREG4PD
0
SWREG4 power OFF
SWREG4 power ON
D2
REG3PD
0
REG3 power OFF
REG3 power ON
D1
REG2PD
0
REG2 power OFF
REG2 power ON
D0
REG1PD
0
REG1 power OFF
REG1 power ON
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© 2010 ROHM Co., Ltd. All rights reserved.
13/19
2010.03 - Rev.A
Technical Note
BD6029GU
Address 02h <Output Voltage Setting 1>
BIT
Name
Initial
D7
D6
D5
D4
D3
D2
D1
D0
SWREG4VSEL1
SWREG4VSEL0
REG3VSEL1
REG3VSEL0
REG2VSEL1
REG2VSEL0
REG1VSEL1
REG1VSEL0
0
0
0
0
0
0
0
0
Function
0
1
SWREG4VSEL1
0
0
1
1
SWREG4VSEL0
0
1
0
1
SWREG4 output
-8V
-7.5V
-7V
-(prohibition of use)
REG3VSEL1
0
0
1
1
REG3VSEL0
0
1
0
1
REG3 output
14.5V
15V
13V
-(prohibition of use)
REG2VSEL1
0
0
1
1
REG2VSEL0
0
1
0
1
REG2 output
3.3V
-(prohibition of use)
3.0V
2.7V
REG1VSEL1
0
0
1
1
REG1VSEL0
0
1
0
1
REG1 output
1.8V
1.2V
1.2V
Address 03h <Output Voltage Setting 2>
BIT
Name
Initial
D7
D6
D5
D4
D3
D2
D1
D0
REGAVSEL1
REGAVSEL0
REG6VSEL1
REG6VSEL0
REG5VSEL1
REG5VSEL0
0
0
0
0
0
0
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© 2010 ROHM Co., Ltd. All rights reserved.
Function
0
1
REGAVSEL1
0
0
1
1
REGAVSEL0
0
1
0
1
REGA output
3.3V
-(prohibition of use)
3.0V
1.8V
REG6VSEL1
0
0
1
1
REG6VSEL0
0
1
0
1
REG6 output
3.3V
3.1V
3.0V
3.2V
REG5VSEL1
0
0
1
1
REG5VSEL0
0
1
0
1
REG5 output
3.0V
-(prohibition of use)
1.8V
1.8V
14/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Explanation for Operate
1. Reset
There are two kinds of reset, Software reset and Hardware reset.
(1) Software reset
◦ It shifts to software reset with changing a register (SFTRST) setting “0” → “1”.
◦ I The register is returned to the initials value under the state of Soft Reset,
and it stops accepting all address except for SFTRST.
◦ I It’s possible to release from a state of Soft Reset by setting register “1” → “0”.
(2) Hardware reset
◦ I It shifts to hard reset by changing RST pin “H” → “L”.
◦ I The condition of all registers under Hardware Reset pin is returned to the initial value,
and it stops accepting all address.
◦ I It’s possible to release from a state of hardware reset by setting register “L” → “H”.
(3) Reset Sequence
◦ I When hardware reset was done during software reset, Software reset is canceled when hard reset is canceled.
(Because the initial value of Soft Reset is “0” )
2. Thermal shutdown
The blocks which thermal shutdown function is effective in
SWREG3 (Step up DC/DC converter)
SWREG4 (Inverted DC/DC converter)
REG1
REG2
REG3
REG5
REG6
REGA
A thermal shutdown function works in about 175 oC. (Design reference value)
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© 2010 ROHM Co., Ltd. All rights reserved.
15/19
2010.03 - Rev.A
Technical Note
BD6029GU
3. Sequencer block
The sequencer block does the power control (like VREF is turned on → SWREG3 is turned on → REG3 is turned on)
on the following condition corresponding to resister condition and output voltage of each block.
Block
VREF
SWREG3
REG3
POWER ON Condition
POWER OFF Condition
Any one of REG3PD to REGAPD = H
REG3PD to REGAPD = all L
REG3PD = H and VREF ≥ 1.1V
REG3PD=L
REG3PD = H and VPLUS2 ≥ 8V
REG3PD=L
SWREG4PD = H, VDD3 ≥ 8V and VREF ≥ 1.1V
SWREG4PD=L
REG1
REG1PD = H and VREF ≥ 1.1V
REG1PD=L
REG2
REG2PD = H and VREF ≥ 1.1V
REG2PD=L
REG5
REG5PD = H and VREF ≥ 1.1V
REG5PD=L
SWREG4
REG6
REG6PD = H and VREF ≥ 1.1V
REG6PD=L
REGA
REGAPD = H and VREF ≥ 1.1V
REGAPD=L
REG3PD
SWREG4PD
REG1PD
REG2PD
REG5PD
REG6PD
REGAPD
REG1
REG2
REG5
REG6
REGA
VDD1
VDD2
VDD5
VDD6
AVDD
VREF
VREF>1.1[V]
SWREG4
SWREG3
VPLUS2>8[V]
REG3
VDD3>8[V]
VDD4
VDD3
When a thermal shutdown hangs, the whole block except for VREF turns off the power.
When it reverts from the thermal shutdown, it starts from the sequence after VREF ON in the above pattern.
The start of SWREG4 (CCD negative power supply) requires the rise-up of REG3 (CCD positive power supply).
This requirement is valid for the reversion from the thermal shutdown and the short circuit.
Detection voltage of VREF’s rise-up is 1.1V when static output is 1.2V.
As shown in the former page description, VREF receives a turning on instruction blocked either each and beginsrise up.
Therefore, it is necessary to consider the block started up first at the rise time of VREF.
LDO ON
VREF output
95% up
LDO output
Worst 5ms
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© 2010 ROHM Co., Ltd. All rights reserved.
16/19
2010.03 - Rev.A
Technical Note
BD6029GU
4. I2C BUS
Operation when a signal beyond fSCL=400kHz is input cannot be guaranteed, because this LSI doesn’t correspond to the
H/S(High Speed) mode of the I2C BUS format.
When it uses on the serial-bus-system which the F/S(Fast Speed) mode was mixed in with the H/S mode, please connect
it and remove a connection by using the mutual connection bridge from the H/S mode section to F/S mode section or in
that reverse direction.
However, an optional input signal never spreads to the logic part of IC, because it stops the operation of the input buffer of
SDA and SCL at RST pin=L.
At RST=L, output ”H” fixed
SCL
(SDA)
Level shifter
EN
Logic
RST
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© 2010 ROHM Co., Ltd. All rights reserved.
17/19
2010.03 - Rev.A
Technical Note
BD6029GU
●PCB Pattern of the Power Dissipation Measuring Board
1st layer(component)
2nd layer
3rd layer
4th layer
5th layer
6th layer
7th layer
8th layer(solder)
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© 2010 ROHM Co., Ltd. All rights reserved.
18/19
2010.03 - Rev.A
Technical Note
BD6029GU
●Ordering part number
B
D
6
Part No.
0
2
9
G
Part No.
U
-
Package
GU: VCSP85H4
E
2
Packaging and forming specification
E2: Embossed tape and reel
VCSP85H4 (BD6029GU)
<Tape and Reel information>
(φ0.15)INDEX POST
A
H
G
F
E
D
C
B
A
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
S
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
B
1 2 3 4 5 6 7 8
0.425±0.05
)
0.425±0.05
0.06 S
48-φ0.3±0.05
0.05 A B
Tape
P=0.5×7
4.35±0.05
0.25±0.1
1.0MAX
4.35±0.05
1PIN MARK
1pin
P=0.5×7
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
Reel
19/19
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.03 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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R0039A