240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG Advantech AQD-D3L8GN16-SG Datasheet Rev. 1.1 2013-09-24 1 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG Description Pin Identification Pin Identification AQD-D3L8GN16 is a DDR3 Unbuffered DIMM, non-ECC, high-speed, low power memory module that use 16 pcs Symbol Function of 512Mx8bits DDR3 low voltage SDRAM in FBGA A0~A15, BA0~BA2 Address/Bank input package and a 2048 bits serial EEPROM on a 240-pin DQ0~DQ63 Bi-direction data bus. DQS0~DQS7 Data strobes /DQS0~/DQS7 Differential Data strobes CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) use of system clock. Data I/O transactions are possible CKE0, CKE1 Clock Enable Input. on both edges of DQS. Range of operation frequencies, ODT0, ODT1 On-die termination control line programmable latencies allow the same device to be /S0, /S1 DIMM rank select lines. useful for a variety of high bandwidth, high performance /RAS Row address strobe /CAS Column address strobe /WE Write Enable DM0~DM7 Data masks/high data strobes JEDEC standard 1.35V(1.28V~1.45V) Power supply VDD Core power supply JEDEC standard 1.5V(1.425V~1.575V) Power supply VDDQ I/O driver power supply VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) VREFDQ I/O reference supply printed circuit board. AQD-D3L8GN16 is a Dual In-Line Memory Module and is intended for mounting into 240-pin edge connector sockets. Synchronous design allows precise cycle control with the memory system applications. Features RoHS compliant products. Clock Freq: 800MHZ for 1600Mb/s/Pin. Command/address reference VREFCA Programmable CAS Latency: 6, 7, 8, 9, 10, 11 Programmable Additive Latency (Posted /CAS): VDDSPD supply SPD EEPROM power supply 0,CL-2 or CL-1 clock I2C serial bus address select for Programmable /CAS Write Latency (CWL) SA0~SA2 EEPROM = 8(DDR3-1600) 8 bit pre-fetch SCL I2C serial bus clock for EEPROM Burst Length: 4, 8 SDA I2C serial bus data for EEPROM Bi-directional Differential Data-Strobe VSS Ground /RESET Set DRAMs Known State VTT SDRAM I/O termination supply NC No Connection Internal calibration through ZQ pin On Die Termination with ODT pin Serial presence detect with EEPROM Asynchronous reset 2 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG Dimensions (Unit: millimeter) Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. 3 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG Pin Assignments Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No 01 VREFDQ 41 VSS 81 DQ32 121 VSS 161 NC 201 02 VSS 42 NC 82 DQ33 122 DQ4 162 NC 202 03 DQ0 43 NC 83 VSS 123 DQ5 163 VSS 203 04 DQ1 44 VSS 84 /DQS4 124 VSS 164 NC 204 05 VSS 45 NC 85 DQS4 125 DM0 165 NC 205 06 /DQS0 46 NC 86 VSS 126 NC 166 VSS 206 07 DQS0 47 VSS 87 DQ34 127 VSS 167 NC 207 08 VSS 48 NC 88 DQ35 128 DQ6 168 /RESET 208 09 DQ2 49 NC 89 VSS 129 DQ7 169 CKE1,NC 209 10 DQ3 50 CKE0 90 DQ40 130 VSS 170 VDD 210 11 VSS 51 VDD 91 DQ41 131 DQ12 171 A15 211 12 DQ8 52 BA2 92 VSS 132 DQ13 172 A14 212 13 DQ9 53 NC 93 /DQS5 133 VSS 173 VDD 213 14 VSS 54 VDD 94 DQS5 134 DM1 174 A12 214 15 /DQS1 55 A11 95 VSS 135 NC 175 A9 215 16 DQS1 56 A7 96 DQ42 136 VSS 176 VDD 216 17 VSS 57 VDD 97 DQ43 137 DQ14 177 A8 217 18 DQ10 58 A5 98 VSS 138 DQ15 178 A6 218 19 DQ11 59 A4 99 DQ48 139 VSS 179 VDD 219 20 VSS 60 VDD 100 DQ49 140 DQ20 180 A3 220 21 DQ16 61 A2 101 VSS 141 DQ21 181 A1 221 22 DQ17 62 VDD 102 /DQS6 142 VSS 182 VDD 222 23 VSS 63 CK1,NC 103 DQS6 143 DM2 183 VDD 223 24 /DQS2 64 /CK1,NC 104 VSS 144 NC 184 CK0 224 25 DQS2 65 VDD 105 DQ50 145 VSS 185 /CK0 225 26 VSS 66 VDD 106 DQ51 146 DQ22 186 VDD 226 27 DQ18 67 VREFCA 107 VSS 147 DQ23 187 NC 227 28 DQ19 68 NC 108 DQ56 148 VSS 188 A0 228 29 VSS 69 VDD 109 DQ57 149 DQ28 189 VDD 229 30 DQ24 70 A10/AP 110 VSS 150 DQ29 190 BA1 230 31 DQ25 71 BA0 111 /DQS7 151 VSS 191 VDD 231 32 VSS 72 VDD 112 DQS7 152 DM3 192 /RAS 232 33 /DQS3 73 /WE 113 VSS 153 NC 193 /S0 233 34 DQS3 74 /CAS 114 DQ58 154 VSS 194 VDD 234 35 VSS 75 VDD 115 DQ59 155 DQ30 195 ODT0 235 36 DQ26 76 /S1,NC 116 VSS 156 DQ31 196 A13 236 37 DQ27 77 117 SA0 157 VSS 197 VDD 237 ODT1,NC 38 VSS 78 VDD 118 SCL 158 NC 198 NC 238 39 NC 79 NC 119 SA2 159 NC 199 VSS 239 40 NC 80 VSS 120 VTT 160 VSS 200 DQ36 240 /S1,ODT1,CKE1：Used for dual-rank UDIMMs; NC on single-rank UDIMMs. CK1 and /CK1：Used for dual-rank UDIMMs; not used on single-rank UDIMMs but terminated. 4 Pin Name DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT 8GB , 1Gx 64 Mod ule( 2 Ran k x8) 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG /S0 /S1 /DQS4 DQS4 DM4 /DQS0 DQS0 DM0 DM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS D0 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS DM DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 D8 ZQ /DQS1 DQS1 DM1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS D4 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS D12 ZQ /DQS5 DQS5 DM5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 /CS DQS /DQS D1 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 D9 ZQ /DQS2 DQS2 DM2 /CS DQS /DQS D5 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS D13 ZQ /DQS6 DQS6 DM6 DM DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS D2 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS DM DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 D10 ZQ /DQS3 DQS3 DM3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS D6 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS D14 ZQ /DQS7 DQS7 DM7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 /CS DQS /DQS D3 ZQ ZQ of D0–D15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 D11 ZQ 240 Ohm *16 BA0–BA2: SDRAMs D0–D15 A0-A15: SDRAMs D0–D15 CKE: SDRAMs D8–D15 CKE: SDRAMs D0–D7 /RAS: SDRAMs D0–D15 /CAS: SDRAMs D0–D15 /WE: SDRAMs D0–D15 ODT: SDRAMs D0–D7 ODT: SDRAMs D8–D15 CK: SDRAMs D0–D7 /CK: SDRAMs D0–D7 CK: SDRAMs D8–D15 /CK: SDRAMs D8–D15 D7 ZQ EEPROM SCL BA0~BA2 A0~A15 CKE1 CKE0 /RAS /CAS /WE ODT0 ODT1 CK0 /CK0 CK1 /CK1 /CS DQS /DQS WP A0 A1 A2 SA0 SA1SA2 SDA DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS D15 ZQ EEPROM D0~D15 D0~D15 D0~D15 D0~D15 VDDSPD VDD/VDDQ VREFDQ VSS VREFCA NOTE: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ,DQS,/DQS,ODT,DM,CKE,/S relationships must be maintained as shown. 3. DQ,DM,DQS,/DQS resistors: Refer to associated topology diagram. 4. For each DRAM,a unique ZQ resistor is connected to ground. The ZQ resistor is 240 Ohm +/-1% This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes in specifications at any time without prior notice. Operating Temperature Condition Parameter Symbol 5 Rating Unit Note 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG Operating Temperature TOPER 0 to 85 C Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 1,2 Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.4 ~ 1.975 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.4 ~ 1.975 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.4 ~ 1.975 V 1 Storage temperature TSTG -55~+100 C 1,2 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the Note: device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions Rating Parameter Symbol Voltage Unit Notes Min Typ. Max 1.35V 1.283 1.35 1.45 V 1.5V 1.425 1.5 1.575 1.35V 1.283 1.35 1.45 V Supply voltage for Output VDDQ 1.5V 1.425 1.5 1.575 I/O Reference Voltage (DQ) VREFDQ(DC) 1.35V 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V I/O Reference Voltage (CMD/ADD) VREFCA(DC) 1.5V 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V 1.35V VREF+0.160 V AC Input Logic High VIH(AC) 1.5V VREF+0.175 1.35V VREF-0.160 V AC Input Logic Low VIL(AC) 1.5V VREF-0.175 1.35V VREF+0.09 VDD V DC Input Logic High VIH(DC) 1.5V VREF+0.1 VDD 1.35V VSS VREF-0.09 V DC Input Logic Low VIL(DC) 1.5V VSS VREF-0.1 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. 3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD. Supply voltage VDD 1, 2 1, 2 3 3 IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature) 8GB, 1Gx64 Module(2 Rank x8) 6 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG Parameter Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Symbol DDR3 1600 CL11 Unit IDD0 760 mA IDD1 856 mA IDD2P 592 mA IDD2Q 752 mA IDD2N 800 mA IDD3P 1008 mA IDD3N 992 mA IDD4R 1656 mA IDD4W 1480 mA IDD5 1920 mA IDD6 352 mA IDD7 2480 mA Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: 1.Module IDD was calculated on the specific brand DRAM(4xnm) component IDD and can be differently measured according to DQ loading capacitor. Timing Parameters & Specifications Speed DDR3 1600 7 Unit 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG Parameter Symbol Min Max Average Clock Period tCK 1.25 <1.5 ns CK high-level width tCH 0.47 0.53 tCK CK low-level width tCL 0.47 0.53 tCK tDQSQ - 100 ps DQ output hold time from DQS, /DQS tQH 0.38 - tCK DQ low-impedance time from CK, /CK DQ high-impedance time from CK, /CK Data setup time to DQS, /DQS reference to Vih(ac)Vil(ac) levels Data hold time to DQS, /DQS reference to Vih(ac)Vil(ac) levels DQ and DM input pulse width for each input tLZ(DQ) -450 225 ps tHZ(DQ) - 225 tDS 10 - tDH 45 tDIPW 360 - ps DQS, /DQS Read preamble DQS, /DQS differential Read postamble tRPRE 0.9 - tCK tRPST 0.3 - tCK DQS, /DQS Write preamble tWPRE 0.9 - tCK DQS, /DQS Write postamble tWPST 0.3 - tCK DQS, /DQS low-impedance time tLZ(DQS) -450 225 ps DQS, /DQS high-impedance time tHZ(DQS) - 225 ps tDQSL 0.45 0.55 tCK tDQSH 0.45 0.55 tCK tDQSS -0.27 +0.27 tCK tDSS 0.18 - tCK tDSH 0.18 - tCK tWTR Max (4tck, 7.5ns) - tWR 15 - ns Mode register set command cycle time tMRD 4 - tCK /CAS to /CAS command delay tCCD 4 - nCK DQS, /DQS to DQ skew, per group, per access DQS, /DQS differential input low pulse width DQS, /DQS differential input high pulse width DQS, /DQS rising edge to CK, /CK rising edge DQS, /DQS falling edge setup time to CK, /CK rising edge DQS, /DQS falling edge hold time to CK, /CK rising edge Delay from start of Internal write transaction to Internal read command Write recovery time Auto precharge write recovery + precharge time Active to active command period for 1KB page size tDAL tRRD Max (4tck, 6ns) nCK - DDR3 1600 8 ps ps tWR+tRP/tck Speed ps ns Unit 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG Parameter Active to active command period for 2KB page size Four Activate Window for 1KB page size Four Activate Window for 2KB page size products Symbol Min Max (4tck, 7.5ns) Max tFAW 30 - ns tFAW 40 - ns Power-up and RESET calibration time tZQinitl 512 - tCK Normal operation Full calibration time tZQoper 256 - tCK tZQcs 64 - tCK tXS Max (5tCK, tRFC+10ns) - tXSDLL tDLL(min) - Normal operation short calibration time Exit self refresh to commands not requiring a locked DLL Exit self refresh to commands requiring a locked DLL Internal read to precharge command delay Minimum CKE low width for Self refresh entry to exit timing Exit power down with DLL to any valid command: Exit Precharge Power Down with DLL CKE minimum pulse width (high and low pulse width) Asynchronous RTT turn-on delay (Power-Down mode) Asynchronous RTT turn-off delay (Power-Down mode) ODT turn-on ODT turn-off tRRD Max tRTP (4tck, 7.5ns) tCKESR tCK(min)+1tCK Max tXP (3tCK, 6ns) - tCK - tCKE Max (3tCK, 5ns) tAONPD 2 8.5 ns tAOFPD 2 8.5 ns tAON -225 225 ps tAOF 0.3 0.7 tCK 9 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG SERIAL PRESENCE DETECT SPECIFICATION AQD-CD3L8G16N-SG Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32-59 Function Described Standard Specification CRC:0-116Byte Number of SPD Bytes written / SPD device size / CRC SPD Byte use: 176Byte coverage during module production SPD Byte total: 256Byte SPD Revision Version 1.0 Key Byte / DRAM Device Type DDR3 SDRAM Key Byte / Module Type UDIMM SDRAM Density and Banks 4GB 8banks SDRAM Addressing ROW:16, Column:10 Reserved 1.35V and 1.5V Module Organization 2Rank / x8 Module Memory Bus Width Non ECC, 64bit Fine Timebase Dividend and Divisor 2.5ps Medium Timebase Dividend 0.125ns Medium Timebase Divisor 0.125ns SDRAM Minimum Cycle Time (tCKmin) 1.25ns Reserved CAS Latencies Supported, Least Significant Byte 6, 7, 8, 9,10,11 CAS Latencies Supported, Most Significant Byte 6, 7, 8, 9,10,11 Minimum CAS Latency Time (tAAmin) 13.125ns Minimum Write Recovery Time (tWRmin) 15ns Minimum /RAS to /CAS Delay Time (tRCDmin) 13.125ns Minimum Row Active to Row Active Delay Time 6ns (tRRDmin) Minimum Row Precharge Time (tRPmin) 13.125ns Upper Nibble for tRAS and tRC Minmum Active to Precharge Time (tRASmin) 35ns Minmum Active to Active/Refresh Time (tRCmin) 48.125ns Minmum Refresh Recovery Time (tRFCmin), Least 260ns Significant Byte Minmum Refresh Recovery Time (tRFCmin), Most 260ns Significant Byte Minmum Internal Write to Read Command Delay Time 7.5ns (tWTmin) Minimum Internal Read to Precharge Command Delay 7.5ns Time (tRTPmin) Upper Nibble for tFAW 30ns Minmum Four Active Window Delay Time (tFAWmin) 30ns DLL off Mode, SDRAM Optional Features RZQ/6, RZQ/7 SDRAM Thermal and Refresh Options No ODTs, No ASR Reserved 10 Vendor Part 92 10 0B 02 04 21 02 09 03 52 01 08 0A 00 FC 00 69 78 69 30 69 11 18 81 20 08 3C 3C 00 F0 83 01 00 240Pin DDR3 1.35V 1600 UDIMM 8GB Based on 512Mx8 AQD-D3L8GN16-SG 60 61 62 63 64-116 117 118 119 120-121 122-125 126-127 Module Nominal Height Module Max Thickness Reference Raw Card Used Address Mapping from Edge Connector to DRAM Reserved Module Manufacturer ID Code, Least Significant Byte Module Manufacturer ID Code, Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code 128-145 Module Part Number 146-147 148-149 150-175 176-255 30mm Planar Double Sides R/C B Mirrored Transcend Transcend Taipei - AQD-D3L8GN16-SG Revision Code DRAM Manufacturer ID Code Manufacturer Specific Data Open for customer use By Manufacturer By Manufacturer Undefined 11 0F 11 01 01 00 01 4F 54 00 00 FB, 5F 41 51 44 2D 44 33 4C 38 47 4E 31 36 2D 53 47 20 20 20 00 Variable Variable 00