Datasheet

204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
Advantech
AQD-SD3L8GE16-MG
Datasheet
Rev. 0.0
2013-11-28
1
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
Description
Pin Identification
AQD-SD3L8GE16-MG is a DDR3L SO DIMM, ECC,
Symbol
Function
high-speed, low power memory module that use 18 pcs
A0~A15, BA0~BA2
Address/Bank input
of 512Mx8bits DDR3 low voltage SDRAM in FBGA
DQ0~DQ63
Bi-direction data bus.
DQS0~DQS7
Data strobes
/DQS0~/DQS7
Differential Data strobes
CK0, /CK0,CK1, /CK1
Clock Input. (Differential pair)
Synchronous design allows precise cycle control with the
CKE0, CKE1
Clock Enable Input.
use of system clock. Data I/O transactions are possible
ODT0, ODT1
On-die termination control line
on both edges of DQS. Range of operation frequencies,
/S0, /S1
DIMM rank select lines.
programmable latencies allow the same device to be
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write Enable
DM0~DM7
Data masks/high data strobes
VDD
Core power supply
• JEDEC standard 1.35V(1.28V~1.45V) Power supply
VDDQ
I/O driver power supply
• JEDEC standard 1.5V(1.425V~1.575V) Power supply
VREFDQ
DQ reference supply
package and a 2K bits serial EEPROM on a 204-pin
printed circuit board. AQD-SD3L8GE16-MG is a Dual
In-Line Memory Module and is intended for mounting into
204-pin edge connector sockets.
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• RoHS compliant products.
• VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
Command/address reference
VREFCA
• Clock Freq: 800MHZ for 1600MT/s
• Programmable CAS Latency: 6, 7, 8, 9, 10, 11
VDDSPD
• Programmable Additive Latency (Posted /CAS):
supply
SPD EEPROM power supply
I2C serial bus address select for
0,CL-2 or CL-1 clock
SA0~SA1
EEPROM
• Programmable /CAS Write Latency (CWL)
SCL
I2C serial bus clock for EEPROM
• 8 bit pre-fetch
SDA
I2C serial bus data for EEPROM
• Burst Length: 4, 8
VSS
Ground
/RESET
Set DRAMs Known State
VTT
DRAM I/O termination supply
NC
No Connection
= 8(DDR3-1600)
• Bi-directional Differential Data-Strobe
• Internal calibration through ZQ pin
• On Die Termination with ODT pin
• Serial presence detect with EEPROM
• Asynchronous reset
2
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
Dimensions (Unit: millimeter)
Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
3
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
Pin Assignments
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
No
Name
No
Name
No
Name
No
Name
No
Name
No
01 VREFDQ
41
81
121
161
201
VSS
CB2
/WE
DQ43
02
42
82
122
162
202
VSS
DQ21
CB7
/RAS
DQ47
03
43
83
123
163
203
VSS
/DQS2
CB3
VDD
VSS
04
44
84
124
164
204
DQ4
DM2
VREFCA
VDD
VSS
05
45
85
125
165
DQ0
DQS2
VDD
/CAS
DQ48
06
46
86
126
166
DQ5
VSS
VDD
ODT0
DQ52
07
47
87
127
167
DQ1
VSS
CKE0
/CS0
DQ49
08
48
88
128
168
VSS
DQ22
A15
ODT1
DQ53
09
49
89
129
169
VSS
DQ18
CKE1
/CS1
VSS
10
50
90
130
170
/DQS0
DQ23
A14
A13
VSS
11
51
91
131
171
DM0
DQ19
BA2
VDD
/DQS6
12
52
92
132
172
DQS0
VSS
A9
VDD
DM6
13
53
93
133
173
DQ2
VSS
VDD
DQ32
DQS6
14
54
94
134
174
VSS
DQ28
VDD
DQ36
DQ54
15
55
95
135
175
DQ3
DQ24
A12/BC#
DQ33
VSS
16
56
96
136
176
DQ6
DQ29
A11
DQ37
DQ55
17
57
97
137
177
VSS
DQ25
A8
VSS
DQ50
18
58
98
138
178
DQ7
VSS
A7
VSS
VSS
19
59
99
139
179
DQ8
DM3
A5
/DQS4
DQ51
20
60
100
140
180
VSS
/DQS3
A6
DM4
DQ60
21
61
101
141
181
DQ9
VSS
VDD
DQS4
VSS
22
62
102
142
182
DQ12
DQS3
VDD
DQ38
DQ61
23
63
103
143
183
VSS
DQ26
A3
VSS
DQ56
24
64
104
144
184
DQ13
VSS
A4
DQ39
VSS
25
65
105
145
185
/DQS1
DQ27
A1
DQ34
DQ57
26
66
106
146
186
VSS
DQ30
A2
VSS
/DQS7
27
67
107
147
187
DQS1
VSS
A0
DQ35
VSS
28
68
108
148
188
DM1
DQ31
BA1
DQ44
DQS7
29
69
109
149
189
VSS
CB0
VDD
VSS
DM7
30
70
110
150
190
/RESET
VSS
VDD
DQ45
VSS
31
71
111
151
191
DQ10
CB1
CK0
DQ40
DQ58
32
72
112
152
192
VSS
CB4
CK1
VSS
DQ62
33
73
113
153
193
DQ11
VSS
/CK0
DQ41
DQ59
34
74
114
154
194
DQ14
CB5
/CK1
/DQS5
DQ63
35
75
115
155
195
VSS
/DQS8
VDD
VSS
VSS
36
76
116
156
196
DQ15
DM8
VDD
DQS5
VSS
37
77
117
157
197
DQ16
DQS8
A10/AP
DM5
SA0
38
78
118
158
198
VSS
VSS
NC
VSS
/EVENT
39
79
119
159
199
DQ17
VSS
BA0
DQ42
VDDSPD
40
80
120
160
200
DQ20
CB6
NC
DQ46
SDA
/S1,ODT1,CKE1：Used for dual-rank UDIMMs; NC on single-rank UDIMMs.
CK1 and /CK1：Used for dual-rank UDIMMs; not used on single-rank UDIMMs but terminated.
4
Pin
Name
SA1
SCL
VTT
VTT
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
8GB, 4Gbx18 Module(2 Rank x8)
This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes
in specifications at any time without prior notice.
5
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Operating Temperature
TOPER
0 to 85
°C
Note:
Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
Note
1,2
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD
-0.4 ~ 1.975
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.4 ~ 1.975
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.4 ~ 1.975
V
1
Storage temperature
TSTG
-55~+100
°C
1,2
1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
Note:
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions
Rating
Parameter
Symbol
Voltage
Unit Notes
Min
Typ.
Max
1.35V
1.283
1.35
1.45
V
1.5V
1.425
1.5
1.575
V
1.35V
1.283
1.35
1.45
V
Supply voltage for Output
VDDQ
1.5V
1.425
1.5
1.575
V
I/O Reference Voltage (DQ)
VREFDQ(DC)
1.35V
0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
I/O Reference Voltage (CMD/ADD) VREFCA(DC)
1.5V
0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
1.35V
VREF+0.160
V
AC Input Logic High
VIH(AC)
1.5V
VREF+0.175
V
1.35V
VREF-0.160
V
AC Input Logic Low
VIL(AC)
1.5V
VREF-0.175
V
1.35V
VREF+0.09
VDD
V
DC Input Logic High
VIH(DC)
1.5V
VREF+0.1
VDD
V
1.35V
VSS
VREF-0.09
V
DC Input Logic Low
VIL(DC)
1.5V
VSS
VREF-0.1
V
Note: 1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.
Supply voltage
VDD
6
1, 2
1, 2
3
3
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
IDD Specification parameters Definition - 8GB (2 Rank x8)
Parameter
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Symbol
DDR3 1600 CL11
Unit
IDD0
657
mA
IDD1
756
mA
IDD2P
324
mA
IDD2Q
576
mA
IDD2N
576
mA
IDD3P
684
mA
IDD3N
684
mA
IDD4R
1575
mA
IDD4W
1287
mA
IDD5
2277
mA
IDD6
360
mA
IDD7
2142
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD),
tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT
= 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT =
0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH
between valid commands;Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
≒
Note:
1.Module IDD was calculated on the specific brand DRAM(3xnm) component IDD and can be differently
measured according to DQ loading capacitor.
Timing Parameters & Specifications
7
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
Speed
Parameter
DDR3 1600
Unit
Symbol
Min
Max
Average Clock Period
tCK
8
-
ns
CK high-level width
tCH
0.47
0.53
tCK
CK low-level width
tCL
0.47
0.53
tCK
tDQSQ
-
100
ps
DQ output hold time from DQS, /DQS
tQH
0.38
-
tCK
DQ low-impedance time from CK, /CK
tLZ(DQ)
-450
225
ps
tHZ(DQ)
-
225
25
-
DQS, /DQS to DQ skew, per group,
per access
DQ high-impedance time from CK,
/CK
Data setup time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
Data hold time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
DQ and DM input pulse width for each
input
tDS
(AC135)
tDH
(DC90)
ps
ps
ps
55
tDIPW
360
-
ps
tRPRE
0.9
-
tCK
DQS, /DQS Read preamble
DQS, /DQS differential Read
postamble
DQS, /DQS Write preamble
tRPST
0.3
-
tCK
tWPRE
0.9
-
tCK
DQS, /DQS Write postamble
tWPST
0.3
-
tCK
DQS, /DQS low-impedance time
tLZ(DQS)
-450
225
ps
DQS, /DQS high-impedance time
tHZ(DQS)
-
225
ps
tDQSL
0.45
0.55
tCK
tDQSH
0.45
0.55
tCK
tDQSS
-0.27
0.27
tCK
tDSS
0.18
-
tCK
tDSH
0.18
-
tCK
tWTR
Max
(4tck, 7.5ns)
-
DQS, /DQS differential input low pulse
width
DQS, /DQS differential input high
pulse width
DQS, /DQS rising edge to CK, /CK
rising edge
DQS, /DQS falling edge setup time to
CK, /CK rising edge
DQS, /DQS falling edge hold time to
CK, /CK rising edge
Delay from start of Internal write
transaction to Internal read command
Write recovery time
tWR
15
-
ns
Mode register set command cycle
time
tMRD
4
-
tCK
/CAS to /CAS command delay
tCCD
4
-
tCK
Auto precharge write recovery +
precharge time
Active to active command period for
tDAL
tWR+tRP/tCK
tRRD
Max
8
tCK
-
ns
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
1KB page size
Speed
Parameter
Active to active command period for
2KB page size
Four Activate Window for 1KB page
size
(4tck, 7.5ns)
DDR3 1600
Unit
Min
Max
(4tck, 6ns)
Max
tFAW
30
-
ns
Power-up and RESET calibration time
tZQinitl
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
tCK
tZQcs
64
-
tCK
tXS
Max
(5tCK, tRFC+10ns)
-
tXSDLL
tDLL(min)
-
Normal operation short calibration
time
Exit self refresh to commands not
requiring a locked DLL
Exit self refresh to commands
requiring a locked DLL
Internal read to precharge command
delay
Minimum CKE low width for Self
refresh entry to exit timing
Exit power down with DLL to any valid
command: Exit Precharge Power
Down with DLL
CKE minimum pulse width (high and
low pulse width)
Symbol
tRRD
Max
tRTP
(4tck, 7.5ns)
tCKESR
tCK(min)+1tCK
Max
tXP
(3tCK, 6ns)
-
tCK
-
tCKE
Max
(3tCK, 5ns)
tAONPD
2
8.5
ns
tAOFPD
2
8.5
ns
ODT turn-on
tAON
-225
225
ps
ODT turn-off
tAOF
0.3
0.7
tCK
Asynchronous RTT turn-on delay
(Power-Down mode)
Asynchronous RTT turn-off delay
(Power-Down mode)
9
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
SERIAL PRESENCE DETECT SPECIFICATION
AQD-SD3L4GE16-MG Serial Presence Detect
Byte No.
Function Described
0
Number of SPD Bytes written / SPD device size / CRC
coverage during module production
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
28
29
SPD Revision
Key Byte / DRAM Device Type
Key Byte / Module Type
SDRAM Density and Banks
SDRAM Addressing
Reserved
Module Organization
Module Memory Bus Width
Fine Timebase Dividend and Divisor
Medium Timebase Dividend
Medium Timebase Divisor
SDRAM Minimum Cycle Time (tCKmin)
Reserved
CAS Latencies Supported, Least Significant Byte
CAS Latencies Supported, Most Significant Byte
Minimum CAS Latency Time (tAAmin)
Minimum Write Recovery Time (tWRmin)
Minimum /RAS to /CAS Delay Time (tRCDmin)
Minimum Row Active to Row Active Delay Time
(tRRDmin)
Minimum Row Precharge Time (tRPmin)
Upper Nibble for tRAS and tRC
Minmum Active to Precharge Time (tRASmin)
Minmum Active to Active/Refresh Time (tRCmin)
Minmum Refresh Recovery Time (tRFCmin), Least
Significant Byte
Minmum Refresh Recovery Time (tRFCmin), Most
Significant Byte
Minmum Internal Write to Read Command Delay Time
(tWTmin)
Minimum Internal Read to Precharge Command Delay
Time (tRTPmin)
Upper Nibble for tFAW
Minmum Four Active Window Delay Time (tFAWmin)
30
SDRAM Optional Features
31
SDRAM Thermal and Refresh Options
19
20
21
22
23
24
25
26
27
10
Standard Specification
CRC:0-116Byte
SPD Byte use: 176Byte
SPD Byte total: 256Byte
Version 1.1
DDR3 SDRAM
72b-SO-DIMM
4GB 8banks
ROW:16, Column:10
1.35V and 1.5V
2Rank / x8
ECC, 8bit
2.5ps
0.125ns
0.125ns
1.25ns
6, 7, 8, 9,10,11
6, 7, 8, 9,10,11
13.125ns
15ns
13.125ns
Vendor Part
6ns
30
13.125ns
35ns
48.125ns
69
11
18
81
260ns
20
260ns
08
7.5ns
3C
7.5ns
3C
30ns
30ns
DLL off Mode,
RZQ/6, RZQ/7
ASR / 85℃~95℃ 2X
refresh rate /95℃
00
F0
92
11
0B
08
04
21
02
09
0B
52
01
08
0A
00
FE
00
69
78
69
83
05
204Pin DDR3 1.35V 1600 ECC SODIMM
8GB Based on 512Mx8
AQD-SD3L8GE16-MG
32
33
34-59
60
61
62
63
64-116
117
118
119
120
121
122-125
126
127
128-145
146-147
148
149
150-151
152-163
164-175
176-255
Module Thermal Sensor
SDRAM Device Type
Reserved, General Section
Module Nominal Height
Module Max Thickness
Reference Raw Card Used
Address Mapping from Edge Connector to DRAM
Reserved
Module Manufacturer ID Code, Least Significant Byte
Module Manufacturer ID Code, Most Significant Byte
Module Manufacturing Location
Module ID: Module Manufacturing Date(Year)
Module ID: Module Manufacturing Date(Week)
Module ID : Module Serial Number
Cyclical Redundancy Code
Cyclical Redundancy Code
Module Part Number
Revision Code
DRAM Manufacturer ID Code
DRAM Manufacturer ID Code
Manufacturer Specific Data
Manufacturer’s Specific Data (Working Order Number)
Manufacturer’s Specific Data (SPD Naming Number)
Open for customer use
Thermal Sensor on module
30mm
Raw Card D
Revision 1
Standard
ADATA
ADATA
*Note: 1
*Note: 2
*Note: 3
*Note: 4
CRC-CCITT(LOW)
CRC-CCITT(HIGH)
*Note: 5
Micron Technology
Micron Technology
*Note: 6
*Note: 7
*Note: 8
*Note :
1. Byte 119 -- Manufacturing location by manufacturing location (00:Taiwan /01:China)
2. Byte 120 -- Module manufacturing date by year (YY).
3. Byte 121 -- Module manufacturing date by
week (WW).
4. Bytes 122~125 -- Module Serial Number.
5. Bytes 128~145 -- Manufacturer Part Number by module part number ,
(Unused digits are coded as ASCII blanks (20h)).
6. Bytes 152~163 -- Manufacturer's Specific Data by working order number.
(Unused digits are coded as 00h.)
7. Bytes 164~175 -- Manufacturer's Specific Data by SPD naming number.
(Unused digits are coded as 00h.)
8. Bytes 176~255 --These bytes are undefined and can be used for A-DATA's own purpose.
Digits are coded as 00h except 218=ADh now.
11
80
00
00
0F
11
23
00
00
04
CB
B7
38
00
80
2C
00
-