Datasheet

204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
Advantech
AQD-SD3L4GE16-SG
Datasheet
Rev. 1.0
2013-12-23
1
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
Description
•
On DIMM thermal Sensor
DDR3 1.35V ECC SO-DIMM is high-speed, low power
•
Asynchronous reset
memory module that use 512Mx8bits DDR3 SDRAM in
FBGA package and a 2048 bits serial EEPROM on a
204-pin
printed
circuit
board.
DDR3
1.35V
ECC
SO-DIMM is a Dual In-Line Memory Module and is
intended for mounting into 204-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
•
PCB: Gold 30 µ
•
RoHS compliant products.
•
JEDEC standard 1.35V(1.28V~1.45V) Power supply
•
JEDEC standard 1.5V ± 0.075V Power supply
•
VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
•
Clock Freq: 800MHZ for 1600Mb/s/Pin.
•
Programmable CAS Latency: 5, 6, 7, 8, 9 ,10, 11
•
Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
•
Programmable /CAS Write Latency (CWL)
= 8(DDR3-1600)
•
8 bit pre-fetch
•
Burst Length: 4, 8
•
Bi-directional Differential Data-Strobe
•
Internal calibration through ZQ pin
•
On Die Termination with ODT pin
•
Serial presence detect with EEPROM
2
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
•
Pin Identification
•
Pin Identification
Symbol
Function
A0~A15, BA0~BA2
Address/Bank input
DQ0~DQ63
Data Input / Output.
DQS0~DQS8
Data strobes
/DQS0~/DQS8
Differential Data strobes
CB0~CB7
DIMM ECC check bits
CK0, /CK0,CK1, /CK1
Clock Input. (Differential pair)
CKE0, CKE1
Clock Enable Input.
ODT0, ODT1
On-die termination control line
/CS0, /CS1
DIMM Rank Select Lines.
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DM0~DM8
Data masks/high data strobes
VDD
Voltage power supply
VDDQ
Voltage Power Supply for DQS
VREFDQ/ VREFCA
Power Supply for Reference
VDDSPD
SPD EEPROM Power Supply
I2C serial bus address select for
SA0~SA1
EEPROM
SCL
I2C serial bus clock for EEPROM
SDA
I2C serial bus data for EEPROM
VSS
Ground
/RESET
Set DRAMs Known State
VTT
SDRAM I/O termination supply
NC
No Connection
Dimensions (Unit: millimeter)
3
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
Note:
1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
4
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
Pin Assignments
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
No
Name
No
Name
No
Name
No
Name
No
Name
No
Name
01
VREFDQ 69
CB0
137
VSS
02
VSS
70
VSS
138
VSS
03
VSS
71
CB1
139
/DQS4
04
DQ4
72
CB4
140
DM4
05
DQ0
73
VSS
141
DQS4
06
DQ5
74
CB5
142
DQ38
07
DQ1
75
/DQS8
143
VSS
08
VSS
76
DM8
144
DQ39
09
VSS
77
DQS8
145
DQ34
10
/DQS0
78
VSS
146
VSS
11
DM0
79
VSS
147
DQ35
12
DQS0
80
CB6
148
DQ44
13
DQ2
81
CB2
149
VSS
14
VSS
82
CB7
150
DQ45
15
DQ3
83
CB3
151
DQ40
16
DQ6
84
VREFCA 152
VSS
17
VSS
85
VDD
153
DQ41
18
DQ7
86
VDD
154
/DQS5
19
DQ8
87
CKE0
155
VSS
20
VSS
88
A15
156
DQS5
21
DQ9
89
CKE1
157
DM5
22
DQ12
90
A14
158
VSS
23
VSS
91
BA2
159
DQ42
24
DQ13
92
A9
160
DQ46
25
/DQS1
93
VDD
161
DQ43
26
VSS
94
VDD
162
DQ47
27
DQS1
95
A12
163
VSS
28
DM1
96
A11
164
VSS
29
VSS
97
A8
165
DQ48
30
/RESET
98
A7
166
DQ52
31
DQ10
99
A5
167
DQ49
32
VSS
100
A6
168
DQ53
33
DQ11
101
VDD
169
VSS
34
DQ14
102
VDD
170
VSS
35
VSS
103
A3
171
/DQS6
36
DQ15
104
A4
172
DM6
37
DQ16
105
A1
173
DQS6
38
VSS
106
A2
174
DQ54
39
DQ17
107
A0
175
VSS
40
DQ20
108
BA1
176
DQ55
41
VSS
109
VDD
177
DQ50
42
DQ21
110
VDD
178
VSS
43
/DQS2
111
CK0
179
DQ51
44
DM2
112
CK1
180
DQ60
45
DQS2
113
/CK0
181
VSS
46
VSS
114
/CK1
182
DQ61
47
VSS
115
VDD
183
DQ56
48
DQ22
116
VDD
184
VSS
49
DQ18
117
A10/AP 185
DQ57
50
DQ23
118
NC
186
/DQS7
51
DQ19
119
BA0
187
VSS
52
VSS
120
NC
188
DQS7
53
VSS
121
/WE
189
DM7
54
DQ28
122
/RAS
190
VSS
55
DQ24
123
VDD
191
DQ58
56
DQ29
124
VDD
192
DQ62
57
DQ25
125
/CAS
193
DQ59
58
VSS
126
ODT0
194
DQ63
59
DM3
127
/CS0
195
VSS
60
/DQS3
128
ODT1
196
VSS
61
VSS
129
/CS1
197
SA0
62
DQS3
130
A13
198
/EVENT
63
DQ26
131
VDD
199
VDDSPD 64
VSS
132
VDD
200
SDA
65
DQ27
133
DQ32
201
SA1
66
DQ30
134
DQ36
202
SCL
67
VSS
135
DQ33
203
Vtt
68
DQ31
136
DQ37
204
Vtt
/CS1,ODT1,CKE1：Used for dual-rank ECC SO-DIMMs; NC on single-rank ECC SO-DIMMs.
CK1 and /CK1：Used for dual-rank ECC SO-DIMMs; not used on single-rank ECC SO-DIMMs but terminated.
Block Diagram
5
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
4GB, 512Mx72 Module(1 Rank x8)
/S0
/DQS0
DQS0
DM0
/DQS4
DQS4
DM4
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D0
/DQS1
DQS1
DM1
8
9
10
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D1
/DQS2
DQS2
DM2
16
17
18
19
20
21
22
23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D4
40
41
42
43
44
45
46
47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D5
EEPROM
SCL
/EVENT
A0 A1 A2
/EVENT
D2
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
48
49
50
51
52
53
54
55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D6
/DQS7
DQS7
DM7
DM
24
25
26
27
28
29
30
31
/CS DQS /DQS
0
1
2
3
4
5
6
7
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
/CS DQS /DQS
0
1
2
3
4
5
6
7
/DQS3
DQS3
DM3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/DQS6
DQS6
DM6
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
32
33
34
35
36
37
38
39
/DQS5
DQS5
DM5
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D3
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
56
57
58
59
60
61
62
63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDA
SA0 SA1 SA2
BA0~BA2
A0~A15
CKE0
/RAS
/CAS
/WE
ODT0
CK0
/CK0
BA0–BA2: SDRAMs D0–D8
A0-A15: SDRAMs D0–D8
CKE: SDRAMs D0–D8
/RAS: SDRAMs D0–D8
/CAS: SDRAMs D0–D8
/WE: SDRAMs D0–D8
ODT: SDRAMs D0–D8
CK: SDRAMs D0–D8
/CK: SDRAMs D0–D8
/CS DQS /DQS
0
1
2
3
4
5
6
7
D7
VDDSPD
VDD/VDDQ
VREFDQ
VSS
VREFCA
EEPROM
D0~D8
D0~D8
D0~D8
D0~D8
/DQS8
DQS8
DM8
DM
CB
CB
CB
CB
CB
CB
CB
CB
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D8
NOTE:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ,DQS,/DQS,ODT,DM,CKE,/S relationships must be
maintained as shown.
3. DQ,DM,DQS,/DQS resistors: Refer to associated topology
diagram.
4. For each DRAM, a unique ZQ resistor is connected to ground. The
ZQ resistor is 240ohm +/- 1%.
This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes
in specifications at any time without prior notice.
6
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Operating Temperature
TOPER
0 to 85
°C
Note: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be
supported.
Note
1,2
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD
-0.4 ~ 1.975
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.4 ~ 1.975
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.4 ~ 1.975
V
1
Storage temperature
TSTG
-55~+100
°C
1,2
1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
Note:
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions
Rating
Parameter
Symbol
Voltage
Unit Notes
Min
Typ.
Max
1.35V
1.283
1.35
1.45
V
1.5V
1.425
1.5
1.575
1.35V
1.283
1.35
1.45
V
Supply voltage for Output
VDDQ
1.5V
1.425
1.5
1.575
I/O Reference Voltage (DQ)
VREFDQ(DC)
1.35V
0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
I/O Reference Voltage (CMD/ADD) VREFCA(DC)
1.5V
0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
1.35V
VREF+0.160
V
AC Input Logic High
VIH(AC)
1.5V
VREF+0.175
1.35V
VREF-0.160
V
AC Input Logic Low
VIL(AC)
1.5V
VREF-0.175
1.35V
VREF+0.09
VDD
V
DC Input Logic High
VIH(DC)
1.5V
VREF+0.1
VDD
V
1.35V
VSS
VREF-0.09
DC Input Logic Low
VIL(DC)
1.5V
VSS
VREF-0.1
Note: 1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.
Supply voltage
VDD
7
1, 2
1, 2
3
3
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature)
4GB, 512Mx72 Module(1 Rank x8)
Parameter
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Symbol
DDR3 1600 CL11
Unit
IDD0
759
mA
IDD1
864
mA
IDD2P
333
mA
IDD2Q
423
mA
IDD2N
450
mA
IDD3P
567
mA
IDD3N
558
mA
IDD4R
1747
mA
IDD4W
1564
mA
IDD5
2046
mA
IDD6
198
mA
IDD7
2715
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD),
tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT
= 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT =
0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH
between valid commands;Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
Note:
1.Module IDD was calculated on the specific brand DRAM(4xnm) component IDD and can be differently
measured according to DQ loading capacitor.
8
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
Timing Parameters & Specifications
Speed
Parameter
DDR3 1600
Unit
Symbol
Min
Max
Average Clock Period
tCK
1.25
<1.5
ns
CK high-level width
tCH
0.47
0.53
tCK
CK low-level width
tCL
0.47
0.53
tCK
tDQSQ
-
100
ps
DQ output hold time from DQS, /DQS
tQH
0.38
-
tCK
DQ low-impedance time from CK, /CK
DQ high-impedance time from CK,
/CK
Data setup time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
Data hold time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
DQ and DM input pulse width for each
input
tLZ(DQ)
-450
225
ps
tHZ(DQ)
-
225
tDS
10
-
tDH
45
tDIPW
360
-
ps
tRPRE
0.9
-
tCK
DQS, /DQS to DQ skew, per group,
per access
ps
ps
ps
DQS, /DQS Read preamble
DQS, /DQS differential Read
postamble
DQS, /DQS Write preamble
tRPST
0.3
-
tCK
tWPRE
0.9
-
tCK
DQS, /DQS Write postamble
tWPST
0.3
-
tCK
DQS, /DQS low-impedance time
tLZ(DQS)
-450
225
ps
DQS, /DQS high-impedance time
tHZ(DQS)
-
225
ps
tDQSL
0.45
0.55
tCK
tDQSH
0.45
0.55
tCK
tDQSS
-0.27
+0.27
tCK
tDSS
0.18
-
tCK
tDSH
0.18
-
tCK
tWTR
Max
(4tck, 7.5ns)
-
tWR
15
-
ns
Mode register set command cycle
time
tMRD
4
-
tCK
/CAS to /CAS command delay
tCCD
4
-
nCK
Auto precharge write recovery +
precharge time
tDAL
DQS, /DQS differential input low pulse
width
DQS, /DQS differential input high
pulse width
DQS, /DQS rising edge to CK, /CK
rising edge
DQS, /DQS falling edge setup time to
CK, /CK rising edge
DQS, /DQS falling edge hold time to
CK, /CK rising edge
Delay from start of Internal write
transaction to Internal read command
Write recovery time
tWR+tRP/tck
9
nCK
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
Active to active command period for
1KB page size
Speed
Parameter
Active to active command period for
2KB page size
Four Activate Window for 1KB page
size
Four Activate Window for 2KB page
size products
tRRD
Max
(4tck, 6ns)
DDR3 1600
Unit
Min
Max
(4tck, 7.5ns)
Max
tFAW
30
-
ns
tFAW
40
-
ns
Power-up and RESET calibration time
tZQinitl
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
tCK
tZQcs
64
-
tCK
tXS
Max
(5tCK, tRFC+10ns)
-
tXSDLL
tDLL(min)
-
Normal operation short calibration
time
Exit self refresh to commands not
requiring a locked DLL
Exit self refresh to commands
requiring a locked DLL
Internal read to precharge command
delay
Minimum CKE low width for Self
refresh entry to exit timing
Exit power down with DLL to any valid
command: Exit Precharge Power
Down with DLL
CKE minimum pulse width (high and
low pulse width)
Symbol
ns
tRRD
Max
tRTP
(4tck, 7.5ns)
tCKESR
tCK(min)+1tCK
Max
tXP
(3tCK, 6ns)
-
tCK
-
tCKE
Max
(3tCK, 5ns)
tAONPD
2
8.5
ns
tAOFPD
2
8.5
ns
ODT turn-on
tAON
-225
225
ps
ODT turn-off
tAOF
0.3
0.7
tCK
Asynchronous RTT turn-on delay
(Power-Down mode)
Asynchronous RTT turn-off delay
(Power-Down mode)
10
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
SERIAL PRESENCE DETECT SPECIFICATION
AQD-SD3L4GE16-SG Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Function Described
Standard Specification
CRC:0-116Byte
Number of SPD Bytes written / SPD device size / CRC
SPD
Byte use: 176Byte
coverage during module production
SPD Byte total: 256Byte
SPD Revision
Version 1.0
Key Byte / DRAM Device Type
DDR3 SDRAM
Key Byte / Module Type
ECC SODIMM
SDRAM Density and Banks
4GB 8banks
SDRAM Addressing
ROW:16, Column:10
Module Nominal Voltage
1.35V
Module Organization
1Rank / x8
Module Memory Bus Width
ECC, 72bit
Fine Timebase Dividend and Divisor
2.5ps
Medium Timebase Dividend
0.125ns
Medium Timebase Divisor
0.125ns
SDRAM Minimum Cycle Time (tCKmin)
1.25ns
Reserved
CAS Latencies Supported, Least Significant Byte
5, 6, 7, 8, 9, 10, 11
CAS Latencies Supported, Most Significant Byte
5, 6, 7, 8, 9, 10, 11
Minimum CAS Latency Time (tAAmin)
13.125ns
Minimum Write Recovery Time (tWRmin)
15ns
Minimum /RAS to /CAS Delay Time (tRCDmin)
13.125ns
Minimum Row Active to Row Active Delay Time
6ns
(tRRDmin)
Minimum Row Precharge Time (tRPmin)
13.125ns
Upper Nibble for tRAS and tRC
Minmum Active to Precharge Time (tRASmin)
35ns
Minmum Active to Active/Refresh Time (tRCmin)
48.125ns
Minmum Refresh Recovery Time (tRFCmin), Least
260ns
Significant Byte
Minmum Refresh Recovery Time (tRFCmin), Most
260ns
Significant Byte
Minmum Internal Write to Read Command Delay Time
7.5ns
(tWTmin)
Minimum Internal Read to Precharge Command Delay
7.5ns
Time (tRTPmin)
Upper Nibble for tFAW
30ns
Minmum Four Active Window Delay Time (tFAWmin)
30ns
DLL off Mode,
SDRAM Optional Features
RZQ/6, RZQ/7
SDRAM Thermal and Refresh Options
No ODTs, No ASR
11
Vendor Part
92
10
0B
08
04
21
02
01
0B
52
01
08
0A
00
FE
00
69
78
69
30
69
11
18
81
20
08
3C
3C
00
F0
83
01
204Pin DDR3 1600 1.35V ECC SO-DIMM
4GB Based on 512Mx8
32
33-59
60
61
62
63
64-116
117
118
119
120-121
122-125
126-127
DDR3-MODULE THERMAL SENSOR
Reserved
Module Nominal Height
Module Max Thickness
Reference Raw Card Used
Address Mapping from Edge Connector to DRAM
Reserved
Module Manufacturer ID Code, Least Significant Byte
Module Manufacturer ID Code, Most Significant Byte
Module Manufacturing Location
Module Manufacturing Date
Module Serial Number
Cyclical Redundancy Code
128-145 Module Part Number
146-147
148-149
150-175
176-255
Support TS
30mm
Planar Double Sides
No Jedec Raw Card
Standard
Transcend
Transcend
Taipei
-
AQD-SD3L4GE16-SG
Revision Code
DRAM Manufacturer ID Code
Manufacturer Specific Data
Open for customer use
By Manufacturer
By Manufacturer
Undefined
12
80
00
0F
11
1F
00
00
01
4F
54
00
00
76, B6
41 51 44 2D 53
44
33 4C 34 47 45
31
36 2D 53 47 20
20
00
Variable
Variable
00