STC5455 Synchronous Clock for SETS Data sheet Description Features The RoHS 6/6 compliant STC5455 is a single chip clock synchronization solution for applications in SDH/SETS, SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 option 1 and 2, G.8262 EEC option 1and 2, Telcordia GR1244 and GR253. - Complies with ITU-T G.813 opt1/2, G.8262 EEC opt1/2, Telcordia GR1244 and GR253 (Stratum3/4E/4/SMC) The STC5455 accepts 5 clock reference inputs, three external frame sync inputs (EX_SYNC1, 2, 3) and generates 4 synchronized clock outputs. Synchronized outputs may be programmed for wide variety of frequencies from 1MHz up to 156.25MHz, in 1kHz steps. Reference inputs are individually monitored for activity and quality. Reference selection may be automatic, manual, or hard-wired manual. Two independent timing generators, T0 and T4, may operate in the Freerun, Synchronized, Pseudo Holdover, and Holdover mode. Synchronization is operated in external timing mode while freerun and holdover are operated in self-timing mode. Each timing generator includes a DSPbased PLL. DSP-based PLL technology removes any external component except the oscillator. It provides excellent performance and reliability to STC5455. The STC5455 is clocked by an external oscillator (TCXO or OCXO). Using a well-chosen external oscillator ensures the STC5455 meet the required specifications and standards. Functional Specification - Two timing generators, T0 and T4; T4 locks independently or locks to T0 - Supports Multiple-Master redundant application (T0 timing generator only) - Accepts external oscillator at frequency of 10MHz, 12.8MHz, 19.2MHz, or 20MHz with programming - Accepts 5 clock reference inputs - Provides three 2kHz or 8kHz external frame sync inputs - Each reference input is monitored for activity and quality - Supports automatic frequency detection or manually acceptable frequency. - Automatic, manual, and hard-wired manual reference selection - Outputs 4 synchronized clock outputs, including 2 frame pulse outputs - 4 programmable clock synthesizers - Phase-align locking or hit-less reference switching - Programmable loop bandwidth, from 0.1Hz to 100Hz - Programmable phase skew in synthesizer level - SPI bus interface - Single 3.3V operation - IEEE 1149.1 JTAG boundary scan - Available in TQFP 64 package Synth Frame8K SRCSW F EX_SYNC 1 EX_SYNC 2 EX_SYNC 3 T0 Timing Generator 5 Ref Clk 3 LVCMOS + 2 LVPECL/LVDS Frame2K Synthesizer G1 T4 Timing Generator TCXO OCXO CLK2K CLK1, LVPECL/LVDS 1MHz ~ 156.25MHz Synthesizer G2 1MHz ~ 156.25MHz Ref Monitor CLK8K CLK2 Synthesizer GT4 2.048MHz SPI Interface Figure 1:Functional Block Diagram Preliminary Page 1 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Table of Contents STC5455 Pin Diagram (Top View) .................................................................................................................... 5 STC5455 Pin Description .................................................................................................................................. 6 Register Map ..................................................................................................................................................... 8 Master Clock Frequency .................................................................................................................................. 10 Input and Output Frequencies ......................................................................................................................... 11 Input Frequencies .................................................................................................................................... 11 Auto-Detect Acceptable Input Frequencies ...................................................................................... 11 Manually Acceptable Input Frequencies .......................................................................................... 11 Clock Output Frequencies ....................................................................................................................... 12 Clock Output Jitter .......................................................................................................................................... 13 General Description ......................................................................................................................................... 14 Application ............................................................................................................................................... 14 Overview .................................................................................................................................................. 14 Chip Master Clock .................................................................................................................................... 14 Reference Inputs and External Sync Inputs ............................................................................................. 14 Reference Inputs .............................................................................................................................. 14 External Frame Sync Inputs ............................................................................................................. 14 Timing Generators and Operation Modes ................................................................................................ 15 Phase Synchronization ............................................................................................................................ 15 Clock Outputs .......................................................................................................................................... 15 Redundant Designs ................................................................................................................................. 15 Control Interfaces ..................................................................................................................................... 16 Field Upgradability ................................................................................................................................... 16 Advantage and Performance ................................................................................................................... 16 Detailed Description ......................................................................................................................................... 17 Chip Master Clock .................................................................................................................................... 17 Freerun Clock .......................................................................................................................................... 17 Operation Mode ....................................................................................................................................... 17 PLL Event In ............................................................................................................................................ 18 Frequency and Phase Transients ............................................................................................................ 18 Frequency Transients ....................................................................................................................... 18 Phase Transients ............................................................................................................................. 18 History of Fractional Frequency Offset .................................................................................................... 18 Short-Term History ........................................................................................................................... 18 Long-Term History ............................................................................................................................ 19 Device Holdover History ................................................................................................................... 19 User-Specified History ...................................................................................................................... 19 Phase-Locked Loop Status Details .......................................................................................................... 19 External SYNC Inputs and Reference Inputs Details ............................................................................... 20 External Frame Sync Inputs ............................................................................................................. 20 Acceptable Frequency and Frequency Offset Detection .................................................................. 20 Activity Monitoring ............................................................................................................................ 20 Input Qualification ............................................................................................................................ 21 Automatic Reference Election Mechanism ...................................................................................... 21 Automatic Reference Selection ........................................................................................................ 22 Manual Reference Selection Mode .................................................................................................. 22 Hard-wired Manual Reference Selection ......................................................................................... 22 Clock Outputs Details .............................................................................................................................. 22 Clock Synthesizers ........................................................................................................................... 22 Preliminary Page 2 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Clock Generators ............................................................................................................................. 23 Clock Output Phase Alignment ........................................................................................................ 23 Synthesizer Skew Programming ...................................................................................................... 23 Clock Outputs ................................................................................................................................... 23 Redundant Application ............................................................................................................................. 24 Frame Reference Input .................................................................................................................... 24 Event Interrupts ........................................................................................................................................ 24 Field Upgradability ................................................................................................................................... 24 Processor Interface Descriptions ............................................................................................................. 26 Register Descriptions and Operation ............................................................................................................... 28 General Register Operation ..................................................................................................................... 28 Multibyte register reads .................................................................................................................... 28 Multibyte register writes ................................................................................................................... 28 Noise Transfer Functions ................................................................................................................................. 49 Order Information ............................................................................................................................................. 50 Specification Modification ................................................................................................................................ 51 Application Notes ............................................................................................................................................. 52 General .................................................................................................................................................... 52 Power and Ground ........................................................................................................................... 52 Master Oscillator .............................................................................................................................. 52 Mechanical Specification .................................................................................................................. 53 Revision History ............................................................................................................................................... 54 Preliminary Page 3 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Table of Figures Figure 1: Functional Block Diagram................................................................................................................... 1 Figure 2: Activity Monitor ................................................................................................................................. 20 Figure 3: Reference Qualification Scheme ...................................................................................................... 21 Figure 4: Automatic Reference Elector States................................................................................................. 22 Figure 5: Output Clocks CLK1 ........................................................................................................................ 23 Figure 6: Output Clocks CLK2 ......................................................................................................................... 23 Figure 7: Output Clocks CLK8K and CLK2K ................................................................................................... 23 Figure 8: SPI Bus, Read access (Pin CLKE = Low) ........................................................................................ 26 Figure 9: SPI Bus Timing, Read access (Pin CLKE = High) ........................................................................... 26 Figure 10: SPI Bus Timing, Write access ........................................................................................................ 27 Figure 11: Noise Transfer Functions .............................................................................................................. 49 Figure 12: Power and Ground ........................................................................................................................ 52 Preliminary Page 4 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet NC NC NC NC NC NC GND VCC CLK2 NC VCC GND SDO TDI TDO TCK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 STC5455 Pin Diagram (Top View) GND 1 48 RST NC 2 47 SCLK AGND 3 46 VCC AVCC 4 45 VCC EVENT_INTR 5 44 CS MCLK 6 43 SDI GND 7 42 CLKE VCC 8 41 TMS VCC 9 40 GND GND 10 39 VCC GND 11 38 VCC VCC 12 37 TRST SRCSW 13 36 VCC AVCC 14 35 EX_SYNC3 AGND 15 34 REF3 NC 16 33 EX_SYNC2 Preliminary 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK8K CLK2K CLK1_P CLK1_N GND VCC REF4_P REF4_N REF5_P REF5_N NC EX_SYNC1 REF1 REF2 GND VCC Connor-Winfield STC5455 Page 5 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet STC5455 Pin Description CLK1, REF4 and REF5 are LVPECL/LVDS. Other I/O is LVCMOS. Table 1: Pin Description Pin Name Pin # AVCC 4,14 3.3V analog power input AGND 3,15 Analog ground VCC 8, 9, 12, 22, 32, 36, 38, 39, 45, 46, 54, 57 3.3V digital power input GND 1, 7, 10, 11, 21, 31, 40, 53, 58 Digital ground TRST 37 I JTAG boundary scan reset, active low TCK 49 I JTAG boundary scan clock TMS 41 I JTAG boundary scan mode selection TDI 51 I JTAG boundary scan data input TDO 50 O JTAG boundary scan data output RST 48 I Active low to reset the chip MCLK 6 I Master clock input (TCXO or OCXO) EVENT_INTR 5 O Event interrupt EX_SYNC1 28 I External Frame Sync input 1 EX_SYNC2 33 I External Frame Sync input 2 EX_SYNC3 35 I External Frame Sync input 3 REF1 29 I Reference input 1 REF2 30 I Reference input 2 REF3 34 I Reference input 3 REF4_P 23 I Differential reference input 4 (LVPECL/LVDS) REF4_N 24 I Differential reference input 4 (LVPECL/LVDS) REF5_P 25 I Differential reference input 5 (LVPECL/LVDS) REF5_N 26 I Differential reference input 5 (LVPECL/LVDS) CLK1_P 19 O Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1 LVPECL or LVDS CLK1_N 20 O Clock output CLK1 negative, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1 LVPECL or LVDS CLK2 56 O Clock output CLK2 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G2; 2.048MHz from Synthesizer GT4 (T4); Frame8K or Frame2K from Synthesizer F. LVCMOS. Preliminary I/O Page 6 of 56 Description TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Table 1: Pin Description Pin Name Pin # I/O CLK8K 17 O 8kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0) CLK2K 18 O 2kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0) SRCSW 13 I Hard-wired manual reference pre-selection CS 44 I SPI bus chip select SCLK 47 I SPI bus clk SDI 43 I SPI bus data in SDO 52 O SPI bus data out CLKE 42 I SPI Clock edge selection NC 2, 16, 27, 55, 59, 60, 61, 62, 63, 64 Preliminary Page 7 of 56 Description No connection. Pins are recommended to be tied to ground TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Register Map Table 2: Register Map Addr Reg Name Bits Type Description 0x00 Chip_ID 15-0 R Chip ID = 0x5455 Chip_Rev 7-0 R Chip revision number 0x03 Chip_Sub_Rev 7-0 R Chip firmware revision number 0x07 Fill_Obs_Window 3-0 R/W Activity monitor: Leaky bucket fill observation window 0x08 Leak_Obs_Window 3-0 R/W Activity monitor: Leaky bucket leak observation window 0x09 Bucket_Size 5-0 R/W Activity monitor: Leaky bucket size 0x0A Assert_Threshold 5-0 R/W Activity monitor: Leaky bucket alarm assert threshold 0x0B De_Assert_Threshold 5-0 R/W Activity monitor: Leaky bucket alarm de-assert threshold 0x0C Freerun_Cali 10-0 R/W Freerun calibration, 2’s complement, -102.4 to +102.3ppm, step in 0.1ppm Disqualification_Range 9-0 R/W Reference disqualification range, 0 ~102.3ppm. The value is also specified as pull-in range Qualification_Range 9-0 R/W Reference qualification range, 0 ~102.3ppm. 0x12 Qualification_Soaking_Time 5-0 R/W Reference qualification soaking time, 0~63s 0x13 Ref_Index_Selector 3-0 R/W Select a reference input to access the register Ref_Info and Ref_Acceptable_Freq. 0x14 Ref_Info 15-0 R Frequency offset and frequency info of the reference selected by register Ref_Index_Selector 0x16 Ref_Activity 4-0 R Reference activity for reference 1 to 5 0x18 Ref_Qual 4-0 R Reference 1 ~ 5 qualification 0x1A Interrupt_Event_Status 7-0 R/W Status of interrupt events 0x1B Interrupt__Event_Enable 7-0 R/W Selects which of interrupt events will assert pin EVENT_INTR 0x1C Interrupt_Config 1-0 R/W Pin EVENT_INTR configuration and idle mode 0x1D Hard-wired_Switch_Pre_Selection 7-0 R/W Pre-selected reference number 1 and reference number 2 for hardwired switch mode 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x15 0x1E SRCSW_States 0 R T0/T4_Tag_Select 0 R/W Selects registers between T0 and T4 for register 0x20 - 0x3F 0x20 Control_Mode 7,5-2 R/W Holdover history usage, Revertive, Manual/Auto, OOP, SRCSW 0x21 Loop_Bandwidth 7-0 R/W Loop bandwidth selection 0x22 Auto_Elect_Ref 3-0 R 0x23 Manual_Select_Ref 3-0 R/W 0x1F 1 Indicates the states of pin SRCSW Indicates the reference elected by auto reference elector The reference specified by users for manual selection mode 0x24 Selected_Ref 3-0 R Indicates the PLL current selected reference 0x25 Device_Holdover_History 31-0 R Device Holdover History Long_Term_Accu_History 31-0 R Long term Accumulated History 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C Preliminary Page 8 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Table 2: Register Map Addr Reg Name Bits Type 0x2D Short_Term_Accu_History 31-0 R Description User_Specified_History 31-0 R/W User programmed holdover history 0x35 History_Ramp 7-0 R/W Control long term history and short term history accumulation bandwidth and the locking stage’s frequency ramp control 0x36 Ref_Priority_Table 19-0 R/W REF1-5 selection priority 0x3C PLL_Status 7-0 R PLL status: SYNC, LOS, LOL, OOP, SAP, FEE, DHT, HHA 0x3D Holdover_Accu_Flush 0 W Flush/reset the long-term history and the device holdover history 0x3E PLL_Event_Out 7-0 R/W PLL event out (Reserved) 0x3F PLL_Event_In 7-0 R/W PLL event in: Relock 0x40 EX_SYNC_Edge_Config 2-0 R/W Select framing edge (falling or rising edge) for EX_SYNC1/2/3 0x42 Frame_Phase_Align 19-0 R/W Selects frame reference input and sampling edge on selected reference for frame alignment. (T0 timing generator only) 0x4A Synth_Index_Select 3-0 R/W Select a synthesizer to access registers Synth_Freq_Value and Synth_Skew_Adj 0x4B Synth_Freq_Value 17-0 R/W Selects synthesizer frequency value from 1MHz to 156.25MHz, in 1kHz steps, based on which synthesizer index is selected at the register Synth_Index_Select Synth_Skew_Adj 11-0 R/W Adjust phase skew for the synthesizer with the index selected at register Synth_Index_Select Short term Accumulated History 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x37 0x38 0x43 0x44 0x4C 0x4D 0x4E 0x4F 0x50 CLK1_Signal_Level 0 R/W Select the signal level (LVDS or LVPECL) for clock outputs CLK1 0x51 CLK1_Sel 1-0 R/W Select synthesizer or enable tri-state for CLK1 0x52 CLK2_Sel 1-0 R/W Select synthesizer or enable tri-state for CLK2 0x59 Frame8K_Sel 6-0 R/W 8kHz frame pulse clock output duty cycle selection, signal inversion 0x5A Frame2K_Sel 6-0 R/W 2kHz frame pulse clock output duty cycle selection, signal inversion 0x5B Ref__Acceptable_Freq 14-0 R/W Select integer N for manually acceptable frequency at Nx8kHz; Enable auto detection of reference input frequency 0x5D Frame_Mux 1-0 R/W Select one of frame signal (Frame8K, Frame2K) and forward it to CLK2 selection 0x70 Field_Upgrade_Status 2-0 R 0x5C Indicates the status of field upgrade process 0x71 Field_Upgrade_Data 7-0 R/W 0x72 Field_Upgrade_Count 12-0 R Load 7600 bytes of firmware configuration data Count byte numbers that have been loaded 0x74 Field_Upgrade_Start 7-0 W Write three values consecutively to start the field upgrade process 0x7F MCLK_Freq_Reset 7-0 R/W 0x73 Select the frequency of the external oscillator Note 1: Timing generator T0 and T4 share register 0x20 ~ 0x3F. Register 0x1F selects between T0 and T4 for the sharing registers 0x20 ~0x3F. Preliminary Page 9 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Master Clock Frequency The STC5455 supports four frequencies of master clock: 10MHz, 12.8MHz, 19.2MHz, and 20MHz. See Chip Master Clock for details. Initial default accepted frequency of MCLK is 12.8MHz. Table 3: Master Clock Frequency 10MHz 12.8MHz (Initial default frequency) 19.2MHz 20MHz Preliminary Page 10 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Input and Output Frequencies Input Frequencies Auto-Detect Acceptable Input Frequencies The STC5455 can automatically detect the frequency of the reference input when the user enable the autodetect function at the register Ref Index Selector and Ref Acceptable Freq for REF1~REF5 individually. The acceptable frequency for auto detection is shown in Table 4. Table 4: Auto-Detect Acceptable Ref Input Frequencies Reference Input Frequency 8 kHz 64 kHz 19.44 MHz 38.88 MHz 77.76 MHz REF1 ~ REF5 1.544 MHz 2.048 MHz 6.48 MHz 8.192 MHz 16.384 MHz 25 MHz 50 MHz 125 MHz EX_SYNC 1 EX_SYNC 2 EX_SYNC 3 2kHz or 8kHz external frame sync inputs Manually Acceptable Input Frequencies When the frequency auto-detect function is disabled, STC5455 provides another option which allows the user to select the manually acceptable reference frequency for REF1~REF5 individually, at the integer multiple of 8kHz (Nx8kHz, N is integer from 1 to 32767). Hence the manually acceptable reference frequency range is 8kHz to 262.136MHz, in 8kHz steps. When a manually acceptable reference frequency is used, the user need to access the register Ref Acceptable Freq to set the integer N for associated reference input selected at the register Ref Index Selector. Input Frequency = N x 8kHz, where N = 1~32767 Preliminary Page 11 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Clock Output Frequencies Table 5: Available Clock Output Frequencies CLK CLK Level Synthesizer Clock Output Frequency Range CLK1 LVPECL/LVDS G1 1MHz ~ 156.25MHz, in 1kHz steps CLK2 LVCMOS G2, F or GT4 1MHz ~ 156.25MHz, in 1kHz steps; Frame8K/Frame2K at 8kHz/2kHz; 2.048MHz F Frame8K at 8kHz F Frame2K at 2kHz CLK8K LVCMOS CLK2K Preliminary Page 12 of 56 tm121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Clock Output Jitter Table 6: Clock Output Jitter Frequency RMS jitter2 (Typical) (MHz) (ps) (ps) (UI) 156.25 13 210 0.03 155.52 13 210 0.03 125 13 210 0.03 77.76 13 210 0.02 77.76 19 330 0.03 38.88 16.5 280 0.01 19.44 15 230 0.005 25 13 180 0.005 2.048 11 180 0.0004 1.544 11 160 0.0003 Clock Output CLK1 (LVPECL/LVDS) CLK2 (LVCMOS) pk-pk jitter2 (10-12) (Typical) Note 2: Filter bandwidth is from 12kHz to Frequency/2 Preliminary Page 13 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet General Description Application The STC5455 is a single chip solution for the synchronous clock in SDH (SETS), SONET, and Synchronous Ethernet network elements. The device is fully compliant with ITU-T G.813 (option1 and option2), G.8262 EEC (option1 and option2) Telcordia GR1244, and GR253 (Stratum3/4E/4/SMC). Its highly integrated design implements all necessary reference selection, monitoring, filtering, synthesis, and control functions. An external oscillator (e.g., high precision OCXO or TCXO) completes a system level solution (see Functional Block Diagram, Figure 1). The STC5455 has four options for frequency of external oscillator. The STC5455 supports multiple-master operations for redundant application. Overview The STC5455 accepts 5 reference inputs and generates 4 synchronized clock outputs, including 2 frame pulse clock outputs at 8kHz and 2kHz. Two independent PLL-based timing generators, T0 and T4, provide the essential functions for Synchronous Equipment Timing Sources (SETS). T0 controls synthesizers G1, G2, and synthesizer F. T4 controls synthesizer GT4. Clock outputs CLK1 and CLK2 can be derived from synthesizer G1 and G2, respectively. CLK2 can also be derived from synthesizer F through T0 path or synthesizer GT4 through T4 path. Frame pulse clock outputs are derived from synthesizer F. The STC5455 incorporates a SPI interface, providing access to status registers. Chip Master Clock The STC5455 operates with an external oscillator (e.g., OCXO or TCXO) as its master clock. The device supports four different frequencies of master clock with programming: 10MHz, 12.8MHz, 19.2MHz, and 20MHz. Initial default accepted frequency is 12.8MHz. Reference Inputs and External Sync Inputs REF1~REF3 and 2 LVPECL/LVDS REF4~REF5. The 5 reference inputs are continuouslySpecification activity and qualFunctional ity monitored. The reference inputs may be selected to accept either the auto-detect acceptable reference frequency which can be automatically detected by STC5455 or manually acceptable reference frequency. The activity monitoring is implemented with a programmable leaky bucket algorithm. A reference is designated as “qualified” if it is active and its fractional frequency offset is within the programmed range for a programmed soaking time. An auto reference elector elects the most appropriate one from the reference inputs according to the revertivity status, and each reference’s priority and qualification. Revertivity determines whether a higher priority qualified reference should preempt a qualified current selected reference. If none of the references input is qualified, holdover or freerun mode will be elected depending on the availability of the holdover history. Reference selection may be automatic, manual, or hard-wired manual. In automatic reference selection mode, the most appropriate one elected from the auto reference elector will be the selected reference input. In manual reference selection mode, user may specify any of the reference inputs as the selected reference input for external timing or holdover/freerun for self-timing. In hard-wired manual mode, user can fast switch using control pin SRCSW between two preprogrammed reference inputs. The reference input elected from the auto reference elector will not affect the selected reference input in manual or hard-wired manual mode. In manual reference selection mode, the timing generator T4 may accept T0’s synchronized output as its input. External Frame Sync Inputs The STC5455 has three external frame sync inputs at 2kHz or 8kHz on the pin EX_SYNC1, EX_SYNC2, and EX_SYNC3 respectively. The frequency of the external frame sync inputs are auto-detected. To achieve frame alignment, any one of the three external sync inputs may be selected as frame reference for T0 selected REF1 to REF5 individually. Reference Inputs The STC5455 accepts 5 reference inputs. 3 LVCMOS Preliminary Page 14 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Timing Generators and Operation Modes phase alignment mode may be configured independently for each individual referenceSpecification input. Functional The STC5455 includes two independent timing generators, T0 and T4, to provide the essential functions for SETS. Each timing generator can individually operate in Freerun, Synchronized, Pseudo-Holdover and Holdover mode. A timing generator is in either external-timing mode or self-timing mode. In external timing mode, PLL of the timing generator phase locks to the selected external reference input. In self-timing mode, the PLL simply tunes the clock synthesizers to a given fractional frequency offset. Synchronized mode is in external timing. PLL’s loop bandwidth may be programmed individually to vary the timing generator’s filtering function. Conversely, freerun, pseudo-holdover and holdover modes are all in self-timing. When selected reference input and previous holdover history are unavailable, such as in system’s initialization stage, freerun mode may be entered or used. When selected reference input is unavailable but a long-term holdover history accumulated in previous synchronized mode is available, holdover mode may be entered or used. STC5455 may enter pseudo-holdover using short-term frequency history. In STC5455, the freerun clock is derived from the MCLK (external oscillator) and digitally calibrated to compensate the external oscillator’s accuracy offset. STC5455 also allow users to program and manipulate the holdover history accumulators. A maximum frequency ramp may be programmed to minimize the ramp of fractional frequency offset changing in the case that the new selected reference is not traced to the same source. This feature restrains the frequency transient which may cause the pull-out-of lock of the downstream network elements. Phase Synchronization In synchronized mode, the phase relationship between the selected reference input and the clock output may be phase arbitrary or frame phase align for T0 timing generator. For timing generator T4, the phase relationship is phase arbitrary only. Zero frame phase relationship is produced for T0 timing generator by programming as frame phase align mode. Switching to a new reference input may expect a longer pull-in process in this mode. On the other hand, programming as arbitrary mode, an arbitrary phase relationship incorporates phase rebuild on reference input switching to minimize the downstream clock’s phase transient. In this scenario, the STC5455 can provide hit-less switching if both reference inputs are traced to the same clock source (e.g., PRC). The STC5455 may accept external frame reference to achieve frame alignment in frame phase align mode. The frame reference and the frame edge, and frame Preliminary Clock Outputs The STC5455 outputs 4 synchronized clock outputs: differential output CLK1(LVPECL or LVDS), LVCMOS output CLK2, frame pulse clock outputs CLK8K at 8kHz and CLK2K at 2kHz (LVCMOS). CLK1 can be derived from synthesizer G1 through T0 path. CLK2 can be derived from synthesizer G2 or F through T0 path and also can be derived from synthesizer GT4 through T4 path. See Figure 1 for functional details. Frequency of clock output CLK1 and CLK2 is programmable by programing frequency of the associated synthesizer from 1MHz up to 156.25MHz, in 1kHz steps. The STC5455 allows the user to program the phase skew of each clock synthesizer except synthesizer GT4, up and down 50ns in roughly 0.024ns step to adjust the phase of clock outputs. Frame pulse clock synthesizer F generates frame pulse clock Frame8K/Frame2K at frequency of 8kHz/ 2kHz. The duty-cycle of Frame8K and Frame2K is programmable. Clock outputs CLK8K and CLK2K are directly driven from Frame8K and Frame2K. Redundant Designs Timing generator T0 supports multiple-master operation for redundant applications to allow system protection against the failure of the single unit. In multiple-master configuration, all units work as masters and lock to the same reference input in parallel. In phase align mode, with the selection of frame reference inputs (EX_SYNC1/2/3) and the frame edge, clock outputs of all the units may keep in frame phase alignment. In order to meet same synchronization requirement, each unit should use same parameter setup including loop bandwidth. Multiple-master configuration demands a high quality external oscillator to obtain a precise frame phase alignment. Page 15 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Control Interfaces Controls interfaces of the STC5455 are composed of hardwire control pins and the SPI bus interface. They provide application access to the internal control and status registers. Functional Specification Field Upgradability The STC5455 supports field upgradability which allows the user to load size of 7600 byte firmware configuration data (provided as per request) via bus interface. It provides the user a flexible field solution for different applications. Advantage and Performance The kernel of each timing generator is a DSP-based PLL. In STC5455, all internal modules are either digital or numerical, including the phase detectors, filters, and clock synthesizers. The revolutionary pure-digital design makes the timing generator become an accurate and reliable deterministic system. This modern technology removes any external component except the external oscillator. It provides excellent performance and reliability to STC5455. A well-chosen oscillator demanded to meet all the synchronization requirements. Short-term stability with respect to the desired loop bandwidth is a more important factor than aging projection and thermal response when an appropriate oscillator is selected. Preliminary Page 16 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Detailed Description The STC5455 is a single chip solution for the synchronous clock in SDH (SETS), SONET, and Synchronous Ethernet network elements. The revolutionary pure-digital internal modules, DSP-based PLL and clock synthesizer are used in the device so that the overall characteristics are more stable compared to ones in traditional method. Freerun Clock Functional Specification The STC5455 has an internal freerun clock synthesized from the MCLK. The frequency offset of the internal freerun clock can be calibrated by writing to the register Freerun Cali. It has the stability of the external TCXO/OCXO. The calibration offset may be programmed in 0.1ppm steps from -102.4 to +102.3ppm, in 2’s complement. This feature allow the user can digitally calibrate the freerun clock without physically adjusting the local oscillator. Chip Master Clock The STC5455 operates with an external oscillator (e.g., OCXO or TCXO) as its master clock on the pin MCLK. Generally, user should select an oscillator has great stability and low phase noise as the master clock (MCLK). The device supports four different accepted frequencies of master clock: 10MHz, 12.8MHz, 19.2MHz, and 20MHz. Initial default accepted frequency of MCLK for STC5455 is 12.8MHz. When 10MHz, 19.2MHz, or 20MHz is selected as the frequency of MCLK, the user must write register MCLK Freq Reset three times consecutively, with no intervening read/writes from/to other register. An internal softreset will occur after three writes completed. The accepted frequency of MCLK input returns to 12.8MHz following any regular reset. See register MCLK Freq Reset for details. In the meantime, the STC5455 allows user to read three values at the register MCLK Freq Reset: FRQID, COUNT, and ID Written Value. FRQID Indicates the ID of the frequency of MCLK that the STC5455 currently accept. COUNT Indicates how many times the register MCLK Freq Reset has been written to. ID Written Value Indicates the ID of associated value that is being written to the register MCLK Freq Reset. See the register MCLK Freq Reset for more details. Operation Mode The STC5455 includes two timing generators, T0 and T4 timing generators. Each timing generator has its own PLL and can be individually operate in either external-timing or self-timing mode. In external timing mode, PLL of a timing generator phase-locks to a reference input. In self-timing mode, PLL simply operates with the external oscillator (MCLK). The STC5455 supports four operation modes: freerun (self-timing), synchronized (external-timing), pseudoholdover (self-timing) and holdover (self-timing). Freerun Mode Freerun mode is typically used during system’s initialization stage when none of reference inputs is available and the clock synchronization has not been achieved. The clock output generated from the STC5455 in freerun mode is relative to the internal freerun clock which is synthesized from MCLK. Frequency of the internal freerun clock can be calibrated by writing to the register Freerun Cali. Synchronized Mode In synchronized mode, the built-in PLL of the timing generator locks to the selected reference input. Each timing generator’s loop bandwidth is independently programmable from 0.1Hz to 100Hz by writing to the register Loop Bandwidth. The noise transfer function of the PLL is determined according to the loop bandwidth and has maximum gain under 0.2dB. In synchronized mode, the phase relationship between the reference input and the clock output can be configured as arbitrary or aligned for timing generator T0 at register Frame Phase Align. Timing generator T4 operates only in phase arbitrary mode. Pseudo-Holdover Mode In pseudo-holdover mode, the clock is synthesized from the MCLK and an accumulated short-term his- Preliminary Page 17 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet tory. This history is accumulated by a built in programmable short-term history accumulator consecutively, which indicates the latest updated fractional frequency offset of the synchronous clock output of each timing generator. The user can read the short-term history from register Short Term Accu History. Holdover Mode Holdover mode is used when none of reference inputs is available and the holdover history has been built. In this condition, the frequency offset of the clock output is maintained closely to previous value generated when the selected reference input was valid. User can select either device holdover history or user specified holdover history at the register Control Mode in holdover mode. PLL Event In The STC5455 provides direct communication with the PLL’s timing generator by writing to the register PLL Event In. Following events can be triggered: - Relock. PLL starts a relock process if this event is triggered. In frame phase align mode, PLL relocks to the reference input and the frame edge is re-selected as well. In phase arbitrary mode, PLL relocks to the reference input and restart the phase rebuild process. Frequency and Phase Transients Severe frequency and phase transients of the clock output will cause lost of lock or buffer overflow/underflow on downstream circuit. By providing programmable maximum slew rate and phase rebuild function, both frequency and phase transient of the STC5455’s clock output is controlled to minimize the impact on downstream circuits. Frequency Transients The STC5455 smoothly control the frequency transient on the clock output. During reference input switching or operation mode switching (etc., enter freerun or holdover mode), if the clock output prior to switching has different frequency offset than the desired clock output, it smoothly approach to desired frequency offset with a maximum acceleration/deceleration rate by writing to the register History Ramp. The maximum slew rate can be programmed as 1.0, 1.5, 2.0 ppm/second. With a limited acceleration/ deceleration rate, the pull-in process may last longer. However, it will minimize the frequency transient impact to the downstream clock and ensure meeting Preliminary components frequency impact tolerance. Functional Specification Phase Transients The STC5455 minimize the variation of the phase transient on the clock output when a phase hit occurs on the selected reference input. The overshoot in the clock output’s phase transient response will be a small amount under 2%. During reference input switching or recovering from LOS/LOL condition, the phase transient may also occurred on the clock output. The STC5455 can minimize it with a phase rebuild function. In synchronized mode, the phase relationship between the reference input and the clock output can be programmed to phase arbitrary or frame phase align at the register Frame Phase Align. If phase arbitrary is selected, a phase rebuild function is performed before locking to the new/recovered reference input. Hit-less switching is achieved with this function and the phase hit to downstream circuits is eliminated. If frame phase align is selected, the reference input is in frame phase alignment with the clock output. Only T0 timing generator supports frame phase alignment. History of Fractional Frequency Offset The STC5455 monitors and tracks the fractional frequency offset between the clock output and MCLK. The history data of the frequency offset is used by clock synthesizers to generate desire outputs while the timing generator is pending for reference input availability. Two weighted 3rd order low-pass filter are used internally as two history accumulators: the short term history accumulator and the long term history accumulator. A mature long term history is stored and further updated as device holdover history. It is used when the STC5455 operates in holdover mode. In addition, the STC5455 allows user to program an user specified history as needed of the application. Short-Term History Short-term history is an average frequency offset between the clock output and MCLK which is filtered internally using a weighted 3rd order low-pass filter with the small time constant. The -3dB filter response point can be programmed from 0.16Hz to 1.3Hz by writing to the register History Ramp register. Shortterm history can be read from the register Page 18 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Short_Term_Accu_History. Typically, short-term history is used by clock synthesizer in two conditions: First, it is used in between the transition of two different operation modes; second, it is used if LOS occurs when the STC5455 operates in synchronized mode with manually reference selection.In addition, shortterm history is provided to perform failure diagnostics and evaluations. In external-timing mode, this bit indicates the achievement of synchronization. bit will not be FunctionalThis Specification asserted in self-timing mode. Long-Term History Long-term history is an average frequency offset between the clock output and MCLK which is filtered internally using a weighted 3rd order low-pass filter with the long time constant. The -3 dB filter response point can be programmed from 0.15mHz to 1.3Hz by writing to the register History Ramp. The history value can be read from the register Long Term Accu History. LOL bit In external-timing mode, the bit will be set if the PLL fails to achieve or maintain lock to the selected reference. This bit will not be asserted in self-timing mode. It is also not complementary to the SYNC bit. Both bits will not be asserted when the PLL is in the pull-in process. The pull-in process usually occur when switch to a new selected reference or recover from the LOS/LOL. Device Holdover History Device holdover history is the history data used when the STC5455 runs in holdover mode. It is acquired from the long term history previously described. In synchronized mode, when timing generators PLL has locked to the selected reference input for over 15 minutes, the long term history is stored and further updated as the device holdover history. If LOS or LOL occurs, the device holdover history will stay at the latest updated value until re-enter the synchronized mode and the PLL locks to the replaced selected reference input for another 15 minutes. Set Bit HO_Usage bit of the register Control Mode to select using device holdover history. Its value can be read from the register Device Holdover History. OOP bit This bit indicates that the selected reference is out of the pull-in range. This is meaningful only if in external-timing mode. This bit will not be asserted in selftiming mode. The frequency offset is relative to the digitally calibrated freerun clock. User-Specified History The STC5455 allows user to provide the history data created from their own sophisticated history accumulation algorithms by writing to the register User Specified History. Set bit HO_Usage of the register Control Mode to select using user specified holdover history. Its value can be read from the register User Specified History. Phase-Locked Loop Status Details The register PLL Status contains the detailed status of the PLLs, including the signal activity of the selected reference, the synchronization status, and the availability of the holdover histories. LOS bit In external-timing mode, this bit indicates the loss of signal on the selected reference. This bit will not be asserted in self-timing mode. SAP bit This bit when set indicates that the PLL’s output clocks have stopped following the selected reference because the frequency offset of the selected reference is out of pull-in range (OOP). User can write to the Control Mode register to program whether the PLL shall follow the selected reference outside of the specified pull-in range or just stay within the pull-in range boundary. FEE bit This bit indicates whether an error occurs in the frame edge detection process in phase align mode. DHT bit This bit indicates whether the device holdover history is tracking on the current selected reference (updating by the long-term history). HHA bit This bit indicates the availability of the holdover history, which may be either the user provided history or the device holdover history. SYNC bit Preliminary Page 19 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet External SYNC Inputs and Reference Inputs Details The STC5455 accepts 5 external reference inputs. The reference inputs may be selected to accept either the auto-detect acceptable reference frequency which can be automatically detected or manually acceptable reference frequency. Reference inputs REF4 and REF5 are LVPECL/LVDS and the remaining three are LVCMOS. All 5 reference inputs are monitored continuously for frequency, activity and quality. Each timing generator may select any of the reference inputs when the device is in external timing mode. T4 may accept T0’s output as its input via internal feedback path. External Frame Sync Inputs The STC5455 has three external frame sync inputs at 2kHz or 8kHz on the pin EX_SYNC1, EX_SYNC2, and EX_SYNC3 respectively. The frequency of the external frame sync inputs are auto-detecting. To achieve frame alignment, any one of the three external frame sync inputs may be selected as frame reference for T0 selected REF1 to REF5 individually at the register Frame Phase Align. Sampling edge of the external sync inputs can be configured as falling or rising at the register EX SYNC Edge Config range is integer multiple of 8kHz from 8kHz to 262.136MHz. When Functional a manually acceptable reference Specification frequency is used, the user need to access the register Ref Index Selector and Ref Acceptable Freq. Each input is monitored for frequency offset between input and the internal freerun clock. The frequency offset is shown in the register Ref Info when associate reference index is selected at the register Ref Index Selector. Activity Monitoring Activity monitoring is also a continuous process which is used to identify if the reference input is in normal. It is accomplished with a leaky bucket accumulation algorithm, as shown in Figure 2. The “leaky bucket” accumulator has a fill observation window that may be set from 1 to 16ms, where any hit of signal abnormality (or multiple hits) during the window increments the bucket count by one. The leak observation window is 1 to 16 times the fill observation window. The leaky bucket accumulator decrements by one for each leak observation window that passes with no signal abnormality. Both windows operate in a consecutive, non-overlapping manner. The bucket accumulator has alarm assert and alarm de-assert thresholds that can each be programmed from 1 to 64. Fill Observation Window, 1ms ~ 16ms Acceptable Frequency and Frequency Offset Detection The STC5455 can automatically detect the frequency of the reference input when the user enable the autodetection function at the register Ref Acceptable Freq. The acceptable auto-detect frequencies are: 8kHz, 64kHz, 1.544MHz, 2.048MHz, 19.44MHz, 38.88MHz, 77.76MHz, 6.48MHz, 8.192MHz, 16.384MHz, 25MHz, 50MHz or 125MHz. These frequencies can be detected automatically in the detector. The detector operates continuously to detect the frequency of reference inputs. Any carrier frequency change will be detected within 1ms. Each input is also monitored for frequency offset between input and the internal freerun clock. The frequency offset is a key factor to determine qualification of the reference inputs. See register Ref Index Selector and Ref Info. Applications can write to the following registers to configure the activity monitor: Fill Obs Window, Leak Obs Window, Bucket Size, Assert Threshold, and De Assert Threshold. STC5455 provides another option which allows the user to select the manually acceptable reference frequency for all the reference inputs, at the integer multiple of 8kHz (Nx8kHz, N is integer from 1 to 32767). Hence the manually acceptable reference frequency Setting the bucket size to 0 will bypass the leak bucket accumulator and assert or de-assert the activity alarm based on results of frequency detector and pulse monitor only. A non-zero bucket size must be greater than or equal to the alarm assert threshold Preliminary Ref Frequency Detector Pulse Monitor Leaky Bucket Accumulator Alarm Assert Alarm De-Assert Leak Observation Window, 1~16 x Fill Observation Window Figure 2: Activity Monitor Page 20 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet value. The alarm assert threshold value must be greater than the alarm de-assert threshold value and less than or equal to the bucket size value. Attempted writes of invalid values will be ignored. Therefore, user must carefully plan an appropriate sequence of writes when re-configure the activity monitor. See register Bucket Size, Assert Threshold and De Assert Threshold for details. Alarms appear in the Refs Activity register. A “1” indicates activity, and a “0” indicates an alarm, no activity. Note that if a reference is detected as a different frequency, the leaky bucket accumulator is set to the bucket size value and the reference will become inactive immediately. Input Qualification A selected reference is “qualified” if it passes the activity evaluation and its frequency offset is within the programmed qualification range for over a preprogrammed soaking time. A reference qualification range may be programmed up to 102.3 ppm by writing to register Qualification Range, and a disqualification range set up to 102.3 ppm, by writing to register Disqualification Range. The qualification range must be set less than the disqualification range. Additionally, qualification soaking time may be programmed from 0 to 63 seconds by writing to register Qualification Soaking Time. The pull-in range is the same as the disqualification range. Activity Not Good Activity Alarm Asserted Activity Alarm De-Asserted Activity Alarm Asserted Continuously Within Offset Qualification Range for more than Qualification soaking Time Activity Good Qualified Out of Disqualification Range Figure 3: Reference Qualification Scheme Preliminary The frequency offset of each reference is relative to the internal freerun Functional clock may be Specification read by selecting the reference in the Ref Info Selector register and then reading the offset value from register Ref Info. Figure 3 shows the reference qualification scheme. A reference is qualified if it has no activity alarm and is continuous within the qualification range for more than the qualification soaking time. An activity alarm or frequency offset beyond the disqualification range will disqualify the reference. It may then be re-qualified if the activity alarm is off and the reference is within the qualification range for more than the qualification time. The reference qualification status of each reference may be read from register Ref Qual. Automatic Reference Election Mechanism The STC5455 has an auto reference elector always elect the best candidate from the reference inputs according to the revertivity status, each reference’s priority and qualification. This mechanism operates independent of reference selection mode. In other word, regardless what the current reference selection mode is, the auto reference elector always work in this mechanism. The detail description of the reference selection mode is in following sections. The reference priority is indicated in the reference priority table which is shown in register Ref Priority Table individually for each timing generator. Each reference has one entry in the table, which may be set to value from 0 to 15. ‘0’ revokes the reference from the election, while 1 to 15 set the priority, where ‘1’ has the highest, and ‘15’ has the lowest priority. The highest priority pre-qualified reference then is a candidate selected by the automatic reference elector. If multiple references share the same priority, the one that has been qualified for the longest time will be recommended to be the candidate. If the current highest priority reference input fails, the next-highest priority reference is selected as the candidate. In order to avoid disturbance of the clock output, the candidate reference selected by automatic reference elector should be handled in two different mode. Revertive mode and non-revertive mode. The mode is determined by either enabling or disabling the “revertive” bit of the Control Mode to “1” for revertive or to “0” for non-revertive operation. Page 21 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet In revertive mode, the automatic reference elector will pre-empted the current candidate reference if the new recommended candidate reference has higher priority. In non-revertive mode, the current candidate reference will not be pre-empted by any new candidate until it is disqualified. If there is no candidate reference available, freerun or holdover will be recommended by the automatic reference elector depending on the holdover history availability. Figure 4 shows the operation states for automatic reference elector. Elect Candidate Reference Candidate Reference Available Candidate Reference Available No Candidate Reference Available and HO not Available Elect Freerun Figure 4: Automatic Reference Elector States Automatic Reference Selection The T0 and T4 timing generators may be individually operated automatic reference input selection mode. The mode is selected via the Control Mode registers. In automatic reference selection mode, the selected reference is the same reference elected by the automatic reference elector. The automatically selected reference for each PLL may be read from the Auto Select Ref registers. Manual Reference Selection Mode In manual reference selection mode, the user may select the reference manually. This mode is selected via the Control Mode registers. The reference is Preliminary Hard-wired Manual Reference Selection Besides the manual reference selection mode, the STC5455 provides a special mode to switch between two pre-selected reference directly from a dedicated pin SRCSW. The two pre-selected references are configured at the register Hard-wired Switch Pre Selection. It can make the device enter the freerun or holdover by writing to the register Hard-wired Switch Pre Selection. In this mode, the pin SRCSW operates as a simple switch by setting high or low. Hardwired Manual Reference Selection is for T0 only. Clock Outputs Details No Candidate Reference Available and HO is Available Elect Holdover selected by writing to the Manual Select Ref regisFunctional Specification ters. The user may also has the device enter freerun or holdover manually by writing to the Manual Select Ref registers. Besides, T4 may select T0’s output as the selected reference. The STC5455 generates 1 synchronized differential (LVPECL or LVDS) clock output: CLK1; 3 LVCMOS clock outputs: CLK2, one 8kHz and one 2kHz frame pulse clock outputs. Figure 5, Figure 6, and Figure 7 respectively show the clock output section for CLK1, CLK2, and CLK8K/CLK2K. Each output has individual clock output section consists of synthesizer and clock generator. Clock generator of CLK1 has LVPECL/LVDS driver to produce differential output. Clock generator of CLK2 includes two muxes and a LVCMOS signal driver. Clock generator of frame output CLK8K and CLK2K consist of a LVCMOS driver. Clock Synthesizers The STC5455 has 4 clock synthesizers, which of 3 is disciplined by the timing generator T0: synthesizer G1, G2 and one frame pulse clock synthesizer F; T4 disciplines a clock synthesizer GT4 with frequency fixed at 2.048MHz. Clock synthesizers G1 and G2 produce frequencies from 1MHz to 156.25MHz, in 1kHz steps. Synthesizer F produce Frame8K and Frame2K at fixed 8kHz and 2kHz. Phase skew of these synthesizers (except synthesizer GT4) are all programmable individually up and down 50ns. CLK1 is derived from synthesizer G1. CLK2 can be derived from synthesizer G2, also can be derived from synthesizer GT4 and F. Synthesizer F produces frame pulse clock Frame8K and Frame2K which can program pulse width at the register Frame8K Sel and Frame2K Sel. Page 22 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Clock Generators Clock generator of CLK1 consists of a LVPECL/LVDS signal driver. The signal level of clock outputs CLK1 can be programmed to either LVPECL or LVDS at the register CLK1 Signal Level. Clock generator of CLK2 consists of a Frame mux, CLK2 Sel Mux, and a LVCMOS driver. CLK2 Sel Mux determines which synthesizer is selected for T0 generator to output CLK2. When synthesizer F is selected, Frame Mux selects one of frame clocks (Frame8K or Frame2K) derived from synthesizer F and forward it to CLK2 Sel Mux for frame signal selection of CLK2. Frame Mux is set at the register Frame Mux and the CLK2 Sel Mux is set at the register CLK2 Sel for CLK2. Signal level is driven from LVCMOS driver in CLK2 generator. The clock generator of CLK8K and CLK2K contains a LVCMOS driver. Clock outputs CLK8K and CLK2K output Frame8K and Frame2K clock pulse clock. The duty cycle is programmable at the register Frame8K Sel and Frame2K Sel. CLK1 Generator Synthesizer G1 1MHz ~ 156.25MHz LVPECL /LVDS DRIVER CLK1 Figure 5:Output Clocks CLK1 Synth F Frame8K Frame2K Synthesizer G2 CLK2 Generator Frame Mux CLK2 Sel 1MHz ~ 156.25MHz LVCMOS CLK2 DRIVER Synthesizer GT4 2.048MHz Figure 6:Output Clocks CLK2 Synthesizer F Frame8K Duty Cycle Control CLK8K Generator LVCMOS Driver Frame2K CLK2K Generator Duty Cycle Control LVCMOS Driver CLK8K 8kHz frame pulse CLK2K Synthesizer Skew Programming The STC5455 allows user to program the phase skew of each clock synthesizer except synthesizer GT4, up and down 50ns in roughly 0.024ns steps. Since each of clock outputs is dedicate derived from its synthesizer respectively, adjust phase skew of the synthesizer will provide the associated clock output a phase skew adjustment. Any clock output derived from synthesizer GT4 is not phase skew programmable because of phase skew of synthesizer GT4 is fixed at 0. Phase skew of the synthesizer G1, G2, and F may be programmed at the register Synth Index Select and Synth Skew Adj. Clock Outputs CLK1 is selected at the register CLK1 Sel. Output frequency or phase skew of CLK1 is programmable when frequency or phase skew of synthesizer G1 is programmed at the register Sync Index Select, Synth Freq Value, and Synth Skew Adj. Output frequency is programmable from 1MHz to 156.25MHz, in 1kHz steps. CLK2 is selected when synthesizer G2, GT4, or F is selected at the register CLK2 Sel. Output frequency or phase skew of CLK2 is programmable when frequency or phase skew of synthesizer G2 is programmable at the register Synth Index Select, Synth Freq Value, and Synth Skew Adj. Output frequency of CLK2 is programmable from 1MHz to 156.25MHz, in 1kHz steps, via either synthesizer G2 or GT4 individually. CLK2 can also output frame pulse clock Frame8K or Frame2K of synthesizer F. Frame8K or Frame2K is selected at the register Frame Mux for CLK2 selection. Phase skew of frame pulse clocks is programmable simultaneously at the register Synth Index Select and Synth Skew Adj. CLK8K and CLK2K derived from synthesizer F output Frame8K and Frame2K clock pulse clock. 2kHz frame pulse Figure 7:Output Clocks CLK8K and CLK2K Clock Output Phase Alignment Any of clock outputs (except the one derived from Preliminary synthesizer GT4) which has frequency at the integer Specification multiple of 8kHz is inFunctional phase alignment with the frame pulse output CLK8K if none of synthesizer skew is programmed. Redundant Application Timing generator T0 supports multiple-master operation for redundant applications to allow system Page 23 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet protection against single part failure. Frame Reference Input For multiple-master redundant design, all the timing devices should keep in frame phase alignment. In order to achieve the alignment, the frame edge of reference input is required. If the reference input is not at frequency of 8kHz, an external frame sync input (at pin EX_SYNC1/2/3) is used and some configuration enhancements are required. See register Frame Phase Align for configuration. Event Interrupts Functional Specification The STC5455 events shown following below are interrupt events might occurred. - Qualification status of the reference inputs change - Activity status of the cross reference inputs change - Selected reference of timing generator T0 changes in automatic reference selection - Selected reference of timing generator T4 changes in automatic reference selection - PLL status of timing generator T0 changes Multiple Master Configuration In multiple-master configuration, each unit works as master and locks to the same reference input. Each unit has consistent loop bandwidth settings. To achieve frame phase alignment for outputs of all the masters, each device has to choose same frame edge on the selected reference input. The system may provides every master a common frame reference or simply choose a reference input at 8kHz. Frame reference input and frame edge on each selected reference input is configured at register Frame Phase Align for Ref1~Ref5 respectively. If an error occurs when sampled on the selected frame edge of the selected reference, bit FEE of the register PLL Status will be asserted and the frame pulse clock output CLK8K will replace the selected frame reference input as the temporary frame reference. The error does not impact bit SYNC and LOL of the register PLL Status. User can invoke a re-lock event to PLL by programming the register PLL Event In under this situation. The frame edge will be reselected as well. Multiple master configuration works only in frame phase align mode. By writing to the register Frame Phase Align, user can set T0 timing generator to frame phase align mode with the frame edge selection. In order to meet the same synchronization and frame alignment requirements, each unit should keep the same parameter setup, especially loop bandwidth. Multiple-master mode demands a high quality external oscillator to obtain a precise frame phase alignment. - PLL status of timing generator T4 changes - Out-Event of timing generator T0 asserts - Out-Event of timing generator T4 asserts The interrupt events can be read from the register Interrupt Status. Each bit indicates one events. The associate bit of the register Interrupt Status will not be changed automatically when the event is cleared. Therefore, the user need write ‘1’ to the associate bit to erase the event. The STC5455 has a pin EVENT_ INTR (pin 8) for indicating the event interrupt occurrence. The pin may be wired to user’s micro-controller. User can program the register Interrupt Mask to decide which of interrupt events will send an alarm to the micro-controller by asserting the EVENT_INTR pin. User can program at the Interrupt Configuration register to specify the logic level (active high or low) of the pin EVENT_INTR when it’s trigged by the interrupt event. User may also program the Interrupt Configuration register to define pin states as tri-state or logic inactive when no interrupt event occurs. Field Upgradability The STC5455 supports field upgradability which allows the user to load size of 7600 byte firmware configuration data (provided as per request) via bus interface. Field upgrade can only be performed at least 3ms after reset. 1. User may read Bit READY of the register Field Upgrade Status to check if field upgrade is ready to start. 2. To begin the field upgrade, write to register Field Upgrade Start three times consecutively, with no intervening read/writes from/to other registers, see Preliminary Page 24 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet the register Field Upgrade Start for details. Functional Specification 3. Once the field upgrade process begins, the STC5455 is hold for data loading. Write 7600 bytes firmware configuration data to the register Field Upgrade Data one byte at a time to complete data loading. User can read the same register for the written byte. But no matter how many times the user read, only the last written byte will be read from the register. 4. Read the register Field Upgrade Count for how many bytes of configuration data has been loaded. Bit Load_Compelet of the register Field Upgrade Status will indicate whether the 7600 bytes loading is complete and meanwhile bit CHECKSUM will indicate the loading is failed or succeed. See register description of Field Upgrade Status for details. Preliminary Page 25 of 56 TM121 Rev: P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Processor Interface Descriptions The STC5455 supports SPI bus interface: The SPI interface bus mode uses the CS, SCLK,SDI, SDO pins, with timing as shown in Figure 8, Figure 9 and Figure 10. For read operation, serial data output can be read out from the STC5455 on either the rising or falling edge of the SCLK. The edge selection depends on pin CLKE logic level. Serial Bus Timing CS tCSHLD tCS 1 2 3 4 tCSMIN tCSTRI 5 6 7 A4 A5 8 9 10 11 12 13 14 15 16 SCLK tDs 1 SDI tCL tDh A0 A1 tCH A2 A3 LSB A6 MSB tDHLD tDRDY SDO D0 D1 D3 D2 D4 D5 D7 D6 LSB MSB Figure 8:SPI Bus, Read access (Pin CLKE = Low) CS tCSHLD tCS 1 2 3 4 5 6 7 8 A4 A5 A6 9 10 tCSMIN tCSTRI 11 12 13 14 15 D2 D3 D4 D5 D6 16 SCLK tDs SDI tCL tDh 1 A0 A1 tCH A2 A3 LSB MSB tDHLD tDRDY SDO D0 D1 LSB D7 MSB Figure 9: SPI Bus Timing, Read access (Pin CLKE = High) Preliminary Page 26 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet CS tCSMIN tCSHLD tCS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 MSB LSB SCLK tDs SDI tCL tDh 0 A0 A1 tCH A2 A3 LSB MSB Figure 10:SPI Bus Timing, Write access Table 7: SPI Bus Timing Symbol Preliminary Description Min Max Unit tCS CS low to SCLK high 10 ns tCH SCLK high time 50 ns tCL SCLK low time 50 ns tDs Data setup time 10 ns tDh Data hold time 10 ns tDRDY Data ready tDHLD Data hold 3 tCSHLD CS hold 30 tCSTRI CS off to data tri-state tCSMIN Minimum delay between successive accesses Page 27 of 56 7 TM121 ns ns ns 5 50 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice ns ns Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Register Descriptions and Operation General Register Operation The STC5455 device has 1, 2, 3, and 4 byte registers. One-byte registers are read and written directly. Multiple -byte registers must be read and written in a specific manner and order, as follows: Multibyte register reads A multi byte register read must commence with a read of the least significant byte first. This triggers a transfer of the remaining byte(s) to a holding register, ensuring that the remaining data will not change with the continuing operation of the device. The remaining byte(s) must be read consecutively with no intervening read/writes from/to other registers. Multibyte register writes A multi byte register write must commence with a write to the least significant byte first. Subsequent writes to the remaining byte(s) must be performed in ascending byte order, consecutively, with no intervening read/ writes from/to other registers, but with no timing restrictions. Multibyte register writes are temporarily stored in a holding register, and are transferred to the target register when the most significant byte is written. Chip_ID, 0x00 (R) Address Bit7 Bit6 Bit5 Bit4 0x00 0x55 0x01 0x54 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit2 Bit1 Bit0 Bit2 Bit1 Bit0 Indicates chip’s ID number Chip_Rev, 0x02 (R) Address Bit7 Bit6 Bit5 Bit4 0x02 Revision Number Indicates the revision number of STC5455 Chip_Sub_Rev, 0x03 (R) Address Bit7 Bit6 Bit5 Bit4 0x03 Bit3 Sub-Revision Number Indicates the firmware revision number of STC5455 Fill_Obs_Window, 0x07 (R/W) Address 0x07 Bit7 Bit6 Bit5 Bit4 Not used Bit3 Leaky bucket fill observation window, m = 0 ~ 15 Sets the fill observation window size for the reference activity monitor to (m+1) ms. The window size can be set from 1ms to 16ms. Preliminary Page 28 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Default value: m = 0, (1ms) Leak_Obs_Window, 0x08 (R/W) Address Bit7 Bit6 0x08 Bit5 Bit4 Not used Bit3 Bit2 Bit1 Bit0 Leaky bucket fill observation window, n = 0 ~ 15 Sets the leak observation window size for the reference activity monitor to (n + 1) times the fill observation window size. The size can be set from 1 to 16ms times the fill observation window size. Default value: n = 3, (4 times) Bucket_Size, 0x09 (R/W) Address Bit7 0x09 Bit6 Bit5 Bit4 Not used Bit3 Bit2 Bit1 Bit0 Leaky bucket size, 0 ~ 63 Sets the leaky bucket size for the reference activity monitor. Bucket size equal to 0 will bypass the leaky bucket accumulator, and assert or de-assert the activity alarm based on results of frequency detector and pulse monitor only. The bucket size must be greater than or equal to the alarm assert value. Otherwise, the value will not be written to the register. Default value: 20 Assert_Threshold, 0x0A (R/W) Address Bit7 0x0A Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 Bit0 Leaky bucket alarm assert threshold, 1 ~ 63 Sets the leaky bucket alarm assert threshold for the reference activity monitor. The alarm assert threshold value must be greater than the de-assert threshold value and less than or equal to the bucket size value. Otherwise, the value will not be written to the register. Default value: 15 De_Assert_Threshold, 0x0B (R/W) Address Bit7 0x0B Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 Bit0 Leaky bucket alarm de-assert threshold, 0 ~ 62 Sets the leaky bucket alarm de-assert threshold for the reference activity monitor. The de-assert threshold value must be less than the assert threshold value. Otherwise, the value will not be written to the register. Default value: 10 Preliminary Page 29 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Freerun_Cali, 0x0C (R/W) Address Bit7 Bit6 Bit5 Bit4 0x0C Bit3 Bit2 Bit1 Bit0 Lower 8 bits of Freerun Calibration 0x0D Not used Upper 3 bits of Freerun Calibration Calibrate frequency of internal freerun clock, from -102.4 to +102.3 ppm, in 0.1ppm steps, 2’s complement. Default value: 0 Disqualification_Range, 0x0E (R/W) Address Bit7 Bit6 Bit5 Bit4 0x0E Bit3 Bit2 Bit1 Bit0 Lower 8 bits of Disqualification Range 0x0F Not used Upper 2 bits Disqualification Range Reference disqualification range, from 0 to +102.3 ppm, in 0.1 ppm steps. This also sets the pull-in range. (See the Reference Input Monitoring and Qualification section). New disqualification range must be greater than qualification range in register Qualification_Range. Otherwise, the value will not be written to the register. Default value: 110 (range = 11.0 ppm). Qualification_Range, 0x10 (R/W) Address Bit7 Bit6 Bit5 Bit4 0x10 Bit3 Bit2 Bit1 Bit0 Lower 8 bits of Qualification Range 0x11 Not used Upper 2 bits Qualification Range Reference qualification range, from 0 to +102.3 ppm, in 0.1 ppm steps. New qualification must be less than disqualification range. Otherwise, the value will not be written to the register. Default value: 100 (range = 10.0 ppm). Qualification_Soaking_Time, 0x12 (R/W) Address Bit7 0x12 Bit6 Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 Bit2 Bit1 Bit0 0 ~ 63 s Sets the soaking time for reference qualification, from 0 to 63s, in 1s step. Default value: 10 (10s) Ref_Index_Selector, 0x13 (R/W) Address 0x13 Preliminary Bit7 Bit6 Bit5 Bit4 Not used Page 30 of 56 TM121 Bit3 REF1~REF5 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Select a reference input to access the register Ref_Info and Ref_Acceptable_Freq. Valid values from 1 to 5 are relative to Ref1 to Ref5. Invalid values will not be written to the register. Default value: 1 Ref_Info, 0x14 (R) Address Bit7 Bit6 Bit5 0x14 Bit4 Bit3 Bit2 Bit1 Bit0 Lower 8 bits of frequency offset 0x15 Reference Frequency Upper 4 bits of frequency offset Frequency offset (Bit11~Bit0): - Indicates the frequency offset and frequency of the reference input selected by the register Ref_Index_Selector. Frequency offset is from -204.7 to +204.7 ppm relative to calibrated freerun, in 0.1 ppm steps, 2’s complement. A value of 2048 indicates the reference is out of range. Reference frequency (Bit15~Bit12): - Indicates only the frequency offset of the reference input selected by the register Ref_Index_Selector. Field value of Reference frequency (bit7~bit4) will be 15, which indicates manually acceptable frequency is selected for reference input. Refer to the register Ref_Acceptable_Freq for the manually acceptable frequency setting. The auto-detect reference frequency is determined as follows (“Unknown” indicates a signal is present, but frequency is undetermined): Field Value Frequency 0 No signal 1 8 kHz 2 64 kHz 3 1.544 MHz 4 2.048 MHz 5 19.44 MHz 6 38.88 MHz 7 77.76 MHz 8 6.48MHz 9 8.192MHz 10 16.384MHz 11 25 MHz 12 50 MHz 13 125 MHz 14 Unknown 15 Manually acceptable frequency is being used Ref_Activity, 0x16 (R) Address 0x16 Preliminary Bit7 Bit6 Bit5 Not Used Page 31 of 56 TM121 Bit4 Bit3 Bit2 Bit1 Bit0 Ref 5 Ref 4 Ref 3 Ref 2 Ref 1 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Reference activity indicator. 0 = inactive, 1 = active Default value: 0 Refs_Qual, 0x18 (R) Address Bit7 Bit6 0x18 Bit5 Not Used Bit4 Bit3 Bit2 Bit1 Bit0 Ref 5 Ref 4 Ref 3 Ref 2 Ref 1 Bit4 Bit3 Bit2 Bit1 Bit0 Event 4 Event 3 Event 2 Event 1 Event 0 Reference qualification indicator. 0 = not qualified, 1 = qualified. Default value: 0 Interrupt_Event_Status, 0x1A (R/W) Address Bit7 0x1A Event 7 Bit6 Bit5 Event 6 Event 5 Event0: Reference qualification status 0 = no change, 1 = reference qualification status changed. Event1: Reserved Event2: T0 selected reference in auto-selection mode 0= no change, 1 = T0 selected reference changed Event3: T0 PLL status 0= no change, 1 = T0 PLL status changed Event4: T0 timing generator’s event out 0= no event out, 1= any of T0 PLL event out is asserted or not cleared at the register of PLL_Event_Out Event5: T4 selected reference in auto-selection mode 0= no change, 1 = T4 selected reference changed Event6: T4 PLL status 0= no change, 1 = T0 PLL status changed Event7: T4 timing generator’s event out 0= no event out, 1= any of T4 PLL event out is asserted or not cleared at the register of PLL_Event_Out Interrupts are cleared by writing “1” to the associated bit. Default value: 0 Interrupt_Event_Enable, 0x1B (R/W) Address Bit7 0x1B Event 7 Bit6 Bit5 Event 6 Event 5 Bit4 Bit3 Bit2 Bit1 Bit0 Event 4 Event 3 Event 2 Event 1 Event 0 Selects which of events will assert the pin EVENT_INTR to active state (See register Interrupt_Config). Preliminary Page 32 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet 0 = mask out, 1 = enable Event0: Reference qualification status changed Event1: Reserved Event2: T0 selected reference changed in auto-selection mode Event3: T0 PLL status changed Event4: T0 timing generator’s event out is asserted Event5: T4 selected reference changed in auto-selection mode Event6: T4 PLL status changed Event7: T4 timing generator’s event out is asserted Default value: 0 Interrupt_Config, 0x1C (R/W) Address Bit7 Bit6 0x1C Bit5 Bit4 Bit3 Bit2 Not used Bit1 Bit0 Idle state Signal active state Signal active state Specify the signal active state at pin EVENT_INTR 0 = active low. 1 = active high Idle state Specify the idle state of pin EVENT_INTR when no interrupt event occurs. 0 = tri-state. 1 = logic inactive Default value: 0 Hard-wired_Switch_Pre_Selection, 0x1D (R/W) Address 0x1D Bit7 Bit6 Bit5 Bit4 Bit3 Pre-selected reference number 2 Bit2 Bit1 Bit0 Pre-selected reference number 1 Pre select reference number 1 and reference number 2 in hard-wired manual reference selection mode. This mode is controlled by pin SRCSW. When pin SRCSW is LOW, reference number 1 is pre-selected. When pin SRCSW is HIGH, reference number 2 is pre-selected. It can be configured only when bit7 of Control_Mode register is set to 1 (See register Control_Mode). Field Value Selection 0 Freerun 1~5 Ref1~Ref5 13 Holdover 14~15 Reserved Default value: 0 Preliminary Page 33 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet SRCSW_States, 0x1E (R) Address Bit7 Bit6 Bit5 Bit4 0x1E Bit3 Bit2 Bit1 Bit0 Not used Pin states Indicates states of pin SRCSW. 0 = Low; 1 = High T0/T4_Tag_Select, 0x1F (R/W) Address Bit7 Bit6 Bit5 Bit4 0x1F Bit3 Bit2 Bit1 Bit0 Not used Tag_Select Selects register between T0 and T4 for the sharing registers 0x20 ~ 0x3F. 0 = T0; 1 = T4 Default value: 0 Control_Mode, 0x20 (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x20 Hard-wired_Switch Not used SAP Ref_Sel_Mode Revertive HO_Usage Bit0 Internal Test Mode control for individual timing generator. Internal Test 0 = Normal operation; 1~3= Reserved HO_Usage Determines which holdover history is used. 0 = Device Holdover History (DHH); 1 = User specified history Revertive Selects the revertive mode or non-revertive mode of the auto selector. 0 = Non-revertive; 1 = Revertive Ref_Sel_Mode Determines reference selection mode. 0 = Manual; 1 = Auto This bit may be overrided by bit7 of this register. SAP In manual mode, when the selected reference is out of pull-in range, as specified in register Disqualification Range, SAP determine whether clock output will follow the reference input 0 = Follow, 1 = Stop following at pull-in range boundary Hard-wired_Switch (T0 timing generator only) 0 = Not hard-wired Switch, selects reference in manual selection mode or auto selection mode; 1 = Hard-wired Switch, selects reference in hard-wired manual selection mode by using control pin Preliminary Page 34 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet SRCSW to hard-wired switch between two pre-selected reference inputs. See register Hard-wired_Switch_Pre_Selection. Default value: 0 Loop_Bandwidth, 0x21 (R/W) Address Bit7 Bit6 Bit5 Bit4 0x21 Bit3 Bit2 Bit1 Bit0 Bit2 Bit1 Bit0 Bandwidth select Sets each timing generator’s loop bandwidth: Field Value Bandwidth, Hz 0 103 1 52 2 27 3 13 4 6.7 5 3.4 6 1.7 7 0.84 8 0.42 9 0.21 10 0.10 11~255 Reserved Default value: 6 Auto_Elect_Ref, 0x22 (R) Address Bit7 Bit6 0x22 Bit5 Bit4 Bit3 Not used Auto elected reference Indicates the auto-elect reference. The auto-elect reference is elected according to revertivity status, and each reference’s priority and qualification. Reference auto-elector also elect the reference in manual reference selection mode. Bit 3 ~ Bit 0 Selection 0 Freerun 1 ~5 Sync with Ref 1 ~ Ref 5 6 ~ 12 Reserved 13 Holdover 14 ~15 Reserved Manual_Select_Ref, 0x23 (R/W) Address 0x23 Preliminary Bit7 Bit6 Bit5 Bit4 Not used Page 35 of 56 TM121 Bit3 Bit2 Bit1 Bit0 Manually selected reference Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet When manual reference selection mode is selected: Selects the reference or set to freerun/holdover/pseudo-holdover. Bit 3 ~ Bit 0 Selection 0 Freerun 1~5 Sync with Ref 1 ~ Ref 5 6 ~ 12 Reserved 13 Holdover 14 Pseudo-Holdover 15 Reserved (for T0); Lock to T0 (for T4) When hard-wired manual reference selection mode is selected: The register is read only and indicates the current reference defined by pin SRCSW and the register Hardwired_Switch_Pre_Selection. Default value: 0 Selected_Ref, 0x24 (R) Address Bit7 Bit6 0x24 Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 Current selected reference Indicates the current selected reference or operation mode. Field Value Current selected reference 0 Freerun 1~5 Sync with Ref 1 ~ Ref 5 6 ~ 12 Reserved 13 Holdover 14 Pseudo-Holdover 15 Reserved (for T0); Lock to T0 (for T4) Device_Holdover_History, 0x25 (R) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0x25 Bits 0 - 7 of 32 bit Device Holdover History 0x26 Bits 8 - 15 of 32 bit Device Holdover History 0x27 Bits 16 - 23 of 32 bit Device Holdover History 0x28 Bits 24 - 31 of 32 bit Device Holdover History Bit1 Bit0 The accumulated device holdover history relative to MCLK. 2’s complement. Resolution is 0.745x10-3 ppb. Preliminary Page 36 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Long_Term_Accu_History, 0x29 (R) Address Bit7 Bit6 Bit5 Bit4 Bit3 0x29 Bits 0 - 7 of 32 bit Long Term History 0x2A Bits 8 - 15 of 32 bit Long Term History 0x2B Bits 16 - 23 of 32 bit Long Term History 0x2C Bits 24 - 31 of 32 bit Long Term History Bit2 Bit1 Bit0 Long term accumulated history relative to MCLK. 2’s complement. Resolution is 0.745x10-3 ppb. Short_Term_Accu_History, 0x2D (R) Address Bit7 Bit6 Bit5 Bit4 0x2D Bit3 Bit2 Bit1 Bit0 Bits 0 - 7 of 32 bit Short term History 0x2E Bits 8 - 15 of 32 bit Short term History 0x2F Bits 16 - 23 of 32 bit Short term History 0x30 Bits 24 - 31 of 32 bit Short term History Short term accumulated history relative to MCLK. 2’s complement. Resolution is 0.745x10-3 ppb. User_Specified_History, 0x31 (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0x31 Bits 0 - 7 of 32 bit User Holdover History 0x32 Bits 8 - 15 of 32 bit User Holdover History 0x33 Bits 16 - 23 of 32 bit User Holdover History 0x34 Bits 24 - 31 of 32 bit User Holdover History Bit1 Bit0 Bit1 Bit0 User specified history relative to MCLK. 2’s complement. Resolution is 0.745x10-3 ppb. Default value: 0 History_Ramp, 0x35 (R/W) Address 0x35 Bit7 Bit6 Bit5 Bit4 Bit3 Long Term History Accumulator Bandwidth Bit2 Short Term History Accumulator Bandwidth Ramp Control Holdover history accumulator bandwidth and ramp controls. Preliminary Page 37 of 56 Bits 7 ~ 4 Long Term History -3dB Bandwidth 0 4.9 mHz 1 2.5 mHz TM121 2 1.2 mHz 3 0.62 mHz 4 0.31 mHz Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Bits 7 ~ 4 Long Term History -3dB Bandwidth 5 0.15 mHz 6, 7 Reserved 8 1.3Hz 9 0.64Hz 10 0.32Hz 11 0.16Hz 12 79mHz 13 40mHz 14 20mHz 15 9.9mHz Bits 3 ~ 2 Short Term History -3dB Bandwidth 0 1.3 Hz 1 0.64 Hz 2 0.32 Hz 3 0.16 Hz Bits 1 ~ 0 Ramp control 0 No Control 1 1.0 ppm/sec 2 1.5 ppm/sec 3 2.0 ppm/sec Default value: 27 (1.2mHz; 0.64Hz; 2ppm/sec) Ref_Priority_Table, 0x36 (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x36 Ref 2 Priority Ref 1 Priority 0x37 Ref 4 Priority Ref 3 Priority 0x38 Not used Ref 5 Priority Bit0 Reference priority for automatic reference elector. Lower values have higher priority: Bits 7~4/Bits 3~0 Reference Priority 0 Revoke from auto reference elector 1 ~ 15 Value 1 ~ 15 Default value: 0 Preliminary Page 38 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet PLL_Status, 0x3C (R) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x3C HHA DHT FEE SAP OOP LOL LOS SYNC SYNC Indicates whether synchronization has been achieved 0 = Not synchronized 1 = Synchronized LOS Loss of signal of the selected reference 0 = No Loss 1 = Loss (Indicate loss of signal, freerun, pseudo holdover and holdover) LOL Loss of lock (Failure to achieve or maintain lock) 0 = No loss of lock 1 = Loss of lock (Indicate loss of lock, freerun, pseudo holdover and holdover) OOP Out of pull-in range. Indicate the frequency offset of the selected reference input is out of pull-in range. 1 = Out of pull-in range 0 = In range SAP Indicates whether the output clocks have stopped following the selected reference, caused by out of pull-in range 1 = Stop following at pull-in range boundary 0 = Following FEE Frame edge error. Indicates whether an error occurs when select frame edge in frame phase align mode. Frame edge on the reference input is selected at the register Frame_Phase_Align 1 = Frame edge error occurs 0 = No frame edge error occurs DHT Device Holdover History tracking 1 = Device holdover history is being tracked. 0 = Device holdover history is acquired based on the last available history. HHA Holdover History Availability. Configure Control_Mode register to select which of holdover history is used. Device Holdover History or User Specified History. 1 = Available 0 = Not available Holdover_Accu_Flush, 0x3D (W) Address Bit7 Bit6 Bit5 0x3D Bit4 Bit3 Bit2 Not used Bit1 Bit0 HO flush Writing to this register will perform a flush to the accumulated history. Bit HO flush determines which of histories is flushed. HO flush: 0 = Flush and clear long term history to 0 Preliminary Page 39 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet 1 = Flush/clear both long term history and the device holdover history to 0. PLL_Event_Out, 0x3E (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x3E Event7 Event6 Event5 Event4 Event3 Event2 Event1 Event0 Bit4 Bit3 Bit2 Bit1 Bit0 Event0: Reserved Event1: Reserved Event2: Reserved Event3: Reserved Event4: Reserved Event5: Reserved Event6: Reserved Event7: Reserved Events are cleared by writing “1” to the bit positions Default value: 0 PLL_Event_In, 0x3F (R/W) Address Bit7 Bit6 Bit5 0x3F Not used Relock Writing 1 to trigger the event. If the event is acknowledged by the STC5455, event bit is cleared to be 0. Event0: Relock: PLL relocks the selected reference input. If the device operates in phase-align mode, PLL reselects the frame edge, relocks and frame phase align to the reference input. If the device operates in non phase-align mode, PLL relocks to the reference input and start over phase rebuild process. Event1: Reserved Event2: Reserved Event3: Reserved Event4: Reserved Event5: Reserved Event6: Reserved Event7: Reserved Default value: 0 EX_SYNC_Edge_Config, 0x40 (R/W) Address 0x40 Bit7 Bit6 Bit5 Bit4 Not Used Bit3 Bit2 Bit1 Bit0 EX_SYNC3 edge EX_SYNC2 edge EX_SYCN1 edge Selects sampling edge (falling or rising) of the external frame sync inputs EX_SYNC1, EX_SYNC2, or EX_SYNC3. Preliminary Page 40 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Bit 0/1/2 Edge Select 0 Falling edge 1 Rising edge Default value: 7 Frame_Phase_Align, 0x42 (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x42 Frame Phase Alignment and Edge Selection for Ref2 Frame Reference Selection for Ref2 Frame Phase Alignment and Edge Selection for Ref1 Frame Reference Selection for Ref1 0x43 Frame Phase Alignment and Edge Selection for Ref4 Frame Reference Selection for Ref4 Frame Phase Alignment and Edge Selection for Ref3 Frame Reference Selection for Ref3 Frame Phase Alignment and Edge Selection for Ref5 Frame Reference Selection for Ref5 0x44 Not used Selects frame reference input and the sampling of the selected reference for frame alignment. T4 timing generator does not support frame phase alignment. Frame reference input selection: Selects any one from the three external sync inputs as frame reference for Ref1~Ref5 individually. External sync inputs can take frequency of 2kHz or 8kHz and this frequency is auto-detectable. When none of frame reference inputs is used, set 0 to select its own frame pulse output of CLK8K as frame reference. Bits 1 ~ 0 Bits 5 ~ 4 Frame Reference Select 0 Device’s own Frame8K 1 External frame sync input EX_SYNC1 2 External frame sync input EX_SYNC2 3 External frame sync input EX_SYNC3 Frame phase alignment and edge selection: Selects either frame phase arbitrary mode or frame phase align mode. Selects the sampling edge on the selected reference input in phase align mode. If phase arbitrary mode is selected, any selection of frame reference will be dismissed. Bits 3 ~ 2 Bits 7 ~ 6 Frame phase alignment 0 Frame phase arbitrary mode 1 2 Frame Edge of Selected Reference Select Dismiss frame reference selection Rising edge nearest to the frame pulse on the frame reference input Frame phase align mode 3 Rising edge previous to the frame pulse on the frame reference input Rising edge next to the frame pulse on the frame reference input Default value: 0 Preliminary Page 41 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Synth_Index_Select, 0x4A (R/W) Address Bit7 Bit6 0x4A Bit5 Bit4 Not Used Bit3 Bit2 Bit1 Bit0 Synthesizer index selection for synthesizer frequency and phase skew adjustment Determines which synthesizer is selected for setting frequency value at the register Synth_Freq_Value and adjusting phase skew at the register Synth_Skew_Adj. Field Value Synthesizer Associated CLK Output 0 Synthesizer F CLK8K, CLK2K, CLK2 1 Synthesizer G1 CLK1 2 Synthesizer G2 CLK2 Default value: 0 Synth_Freq_Value, 0x4B (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x4B Bits 0-7 of 18 bits Synthesizer Frequency Selection 0x4C Bits 15-8 of 18 bits Synthesizer Frequency Selection 0x4D Not used Bit0 Bits 17-16 of 18 bits Synthesizer Frequency Selection Selects synthesizer frequency value from 1MHz to 156.25MHz, in 1kHz steps, based on which synthesizer index is selected at register Synth_Index_Select. This register is not writable for synthesizer F and synthesizer GT4 since their frequency are fixed. Frequency of synthesizer F is fixed at 8kHz and 2kHz. Frequency of synthesizer GT4 is fixed at 2.048MHz. Default value varies with synthesizer index selection at the register Synth_Index_Select, refer to table below: Synthesizer Index Selection Associated CLK Output Default Value Synthesizer G1 CLK1 155520 (155.52MHz) Synthesizer G2 CLK2 38880 (38.88MHz) Written values less than 1000 or greater than 156250 are invalid. Synth_Skew_Adj, 0x4E (R/W) Address Bit7 Bit6 Bit5 0x4E 0x4F Preliminary Bit4 Bit3 Bit2 Bit1 Bit0 Lower 8 bits of Synthesizer Phase Skew Adjustment Not used Page 42 of 56 TM121 Higher 4 bits of Synthesizer Phase Skew Adjustment Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Phase skew adjust for synthesizer G1, G2, or F based on the selection at the register Synth_Index_Select. Synthesizer GT4 is not phase skew programmable. The adjustment is from -6400/128 ns to 6396.875/128 ns, which is -50ns ~ 49.976 ns, in 3.125/128 ns steps, 2’s complement. Synthesizer Index Selection Associated CLK Output Synthesizer F CLK8K, CLK2K, CLK2 Synthesizer G1 CLK1 Synthesizer G2 CLK2 Default value: 0 (For all the synthesizers) CLK1_Signal_Level, 0x50 (R/W) Address Bit7 Bit6 Bit5 Bit4 0x50 Bit3 Bit2 Bit1 Bit0 Not used CLK1 Signal Level Selects the signal level for clock outputs CLK1 0 = LVPECL, 1 = LVDS Default value: 0 CLK1_Sel, 0x51(R/W) Address Bit7 Bit6 Bit5 0x51 Bit4 Bit3 Bit2 Bit1 Not used Bit0 CLK1 Synthesizer Select Selects clock output CLK1 derived from synthesizer G1 or put in tri-state. Bits 1 ~ 0 CLK1 Synthesizer Select 0, 2, 3 Put CLK1 in tri-state mode 1 Synthesizer G1 Default value: 0 CLK2_Sel, 0x52 (R/W) Address Bit7 Bit6 Bit5 0x52 Bit4 Bit3 Bit2 Not used Bit1 Bit0 CLK2 Synthesizer Select Selects the clock output CLK2 derived from synthesizer G2 (T0) or synthesizer GT4(T4). Frame8K and Frame2K are produced at synthesizer F. When synthesizer F is selected, sets bit1~bit0 of the register Frame_Mux to select frame pulse clock Frame8K or Frame2K. Signal level of CLK2 is LVCMOS. Preliminary Register Frame_Mux (Bit1~Bit0) Bits 1 ~ 0 CLK2 Synthesizer Select X 0 Put CLK2 in tri-state mode Page 43 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Register Frame_Mux (Bit1~Bit0) Bits 1 ~ 0 CLK2 Synthesizer Select X 1 Synthesizer G2 (T0) 0 2 Reserved 1 2 Synthesizer F Frame8K 2 2 Synthesizer F Frame2K 3 2 CLK2 tie to ground X 3 Synthesizer GT4 (T4) Default value: 0 Frame8K_Sel, 0x59 (R/W) Frame2K_Sel, 0x5A (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x59 Not used Invert Duty Cycle Select for Frame8K or put CLK8K into tri-state 0x5A Not used Invert Duty Cycle Select for Frame2K or put CLK2K into tri-state Bit0 Selects duty cycle of the Frame8K and Frame2K generated from synthesizer F and determine frame edge is rising or falling. Set Bit5~0 to 0 to put CLK8K/CLK2K into tri-state and put Frame8K/Frame2K of synthesizer F to ground. Bit 5 ~ 0 Duty Cycle Select 0 Put CLK8K/CLK2K into tri-state and put Frame8K/Frame2K to ground 1~62 Pulse width 1 to 62 cycle of 155.52MHz 63 50% duty cycle Bits 6 Invert 0 Not inverted (frame on rising edge) 1 Inverted (frame on falling edge) Default value: 0 (Tri-state/ground, not inverted) Ref_Acceptable_Freq, 0x5B (R/W) Address Bit7 Bit6 Bit5 0x5B 0x5C Bit4 Bit3 Bit2 Bit1 Bit0 Lower 8 bits of integer N Select Not used Higher 7 bits of integer N Select Enable frequency auto detect function or set integer N for the manual acceptable reference frequency for individual reference input. Setting this register to 0 is to enable frequency auto detection for reference input which is selected at the register Ref_Index_Selector. The auto-detect acceptable reference input frequencies are shown in Table 3. Select the integer N for the manually acceptable reference frequency at Nx8kHz (N is integer from 1 to 32767) for REF1 ~ REF5. Which of reference inputs is selected for the manually acceptable reference is depending on Preliminary Page 44 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet the index selected at the register Ref_Index_Selector. Setting integer N (from 1 to 32767) at this register allows user to manually select the acceptable reference input frequency at the integer multiple of 8kHz, range from 8kHz to 262.136MHz. For instance, user can select integer N = 19440 to manually accept frequency at 19440x8kHz = 155.52MHz. Field Value Integer N Select 0 Enable auto detection for reference input 1~32767 Integer N for the manual acceptable reference frequency Default value: 0 Frame_Mux, 0x5D (R/W) Address Bit7 Bit6 Bit5 0x5D Bit4 Bit3 Bit2 Not used Bit1 Bit0 Frame mux of CLK2 selection Select one of frame signals (Frame8K, Frame2K) derived from synthesizer F and forward it to output selection of CLK2. Output selection of CLK2 is programmed at the registers CLK2_Sel. Bit1~Bit0 Frame signal select 0 Reserved 1 Frame8K 2 Frame2K 3 Ground Default value: 1 Field_Upgrade_Status, 0x70 (R) Address Bit7 0x70 Bit6 Bit5 Bit4 Not used Bit3 Bit2 Bit1 Bit0 Load_Complete READY Checksum Checksum Checks whether the 7600 bytes firmware configuration data is loaded successfully. 0 = Fail, 1 = Success READY Indicates if field upgrade is ready to begin, normally is set to 1 at 3 milliseconds (3ms) after the reset. 0 = Not ready 1 = Ready Load_Complete Indicates whether the loading of 7600 bytes firmware configuration data is complete. 0 = Not complete 1 = Complete Preliminary Page 45 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Field_Upgrade_Data, 0x71 (R/W) Address Bit7 Bit6 Bit5 0x71 Bit4 Bit3 Bit2 Bit1 Bit0 Field upgrade of firmware configuration data Writes the firmware configuration data (7600 bytes) to this register one byte at a time to complete data loading. Only the last written byte can be read from this register, regardless of how many times of reads performed. Default value: 0 Field_Upgrade_Count, 0x72 (R) Address Bit7 Bit6 0x72 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Lower 8 bits of byte count for firmware configuration data 0x73 Not used Higher 5 bits of byte count for firmware configuration data Reads this register for how many bytes of 7600 bytes firmware configuration data has been loaded through the register Field_Upgrade_Data. Default value: 0 Field_Upgrade_Start, 0x74 (W) Address Bit7 Bit6 Bit5 Bit4 Bit3 0x74 Bit2 Bit1 Bit0 Start field upgrade If bit READY of the register Field Upgrade Status is set to 1, user can write three values to this register consecutively, with no intervening read/writes from/to other registers to start the process of field upgrade. 7600 bytes firmware configuration data can only start loading after the three values are written successfully. Write Sequence Bit 7 ~ 0 First 0x51 Second 0x52 Third 0x53 MCLK_Freq_Reset, 0x7F (R/W) Register Writes: Address Bit7 Bit6 Bit5 0x7F Bit4 Bit3 Bit2 Bit1 Bit0 External oscillator frequency selection Select accepted frequency of MCLK input by writing the associated value to this register three times consecutively, with no intervening read/writes from/to other register. The associated values for the four accepted frequency (10MHz, 12.8MHz, 19.2MHz, 20MHz) are as shown in table below. Three times of consecutive writes Preliminary Page 46 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet will trigger internal soft-reset. Initial default accepted frequency for STC5455 is 12.8MHz. The accepted frequency of MCLK input returns to 12.8MHz following any regular reset. Perform writes at least 50us after the regular reset has done. Written value is shown below: Bit 7 ~ 0 External Oscillator Frequency Selection 0x11 10MHz 0x22 12.8MHz 0x44 19.2MHz 0x88 20MHz Register Read: Address 0x7F Bit7 Bit6 Bit5 FRQID Bit4 Bit3 COUNT Bit2 Bit1 Bit0 ID_Written_Value This register allows the user read back three values as follows: FRQID Indicates the ID of the frequency of MCLK that the STC5455 currently accept. Constant 1 can be read from FRQID initially since the default accepted frequency for the STC5455 is 12.8MHz. The value of FRQID can only be updated when three consecutive valid writes are written to the register MCLK_Freq_Reset completely. Bit 7 ~ 6 FRQID MCLK Frequency 0 10MHz 1 12.8MHz 2 19.2MHz 3 20MHz COUNT Indicates how many times this register has been written to. COUNT is set to 1 when each time a different valid associated value is written to for the first time. COUNT is clear to 0 after three times valid writes are completed. Bit 5 ~ 4 COUNT Counter 0 Not written or invalid 1 Once 2 Twice 3 Three times ID_Written_Value Indicates the ID of the associated value that is being written to this register. The ID is updated when each time a different valid associated value is written to this register for the first time. Preliminary Page 47 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet As described above in Register Writes, the associated value should be written to three times consecutively, with no intervening read/writes from/to other register. If the written value is invalid or the consecutive writes operation is interrupted by reading/writing from/to other register, ID_Written_Value is clear to 0. Bit 3 ~ 0 ID_Written Value Written value to the register (0x7F) 0 Not written 1 0x11 2 0x22 4 0x44 8 0x88 Default value: 0x40 (12.8MHz) Preliminary Page 48 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Noise Transfer Functions User may write to register Loop Bandwidth to set the PLL loop bandwidth for each timing generator. The noise transfer function of the PLL filter is determined by the loop bandwidth. Figure 11 shows the noise transfer functions as the loop bandwidth vary from 100mHz to 103Hz. 20 dB 0 dB Transfer Attenuation -3dB -20 dB -40 dB 0.10 Hz 0.21 Hz 0.42 Hz 0.84 Hz 1.7 Hz 3.4 Hz 6.7 Hz 13 Hz 27 Hz 52 Hz 103 Hz -60 dB -80 dB 10 mHz 100 mHz 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz Noise Frequency Figure 11: Noise Transfer Functions Preliminary Page 49 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Order Information All STC5455 parts are RoHS 6/6 compliant. The product revision number is provided by register Chip_Rev (0x02) and Chip_Sub_Rev (0x03). The revision number has format of A.B.C. The latest revision is 3.1.1. It is backward compatible with previous revisions. Register address is shown below: Chip_Rev, 0x02 (R) Address Bit7 Bit6 0x02 Bit5 Bit4 Bit3 Bit2 A Bit1 Bit0 Bit1 Bit0 B Chip_Sub_Rev, 0x03 (R) Address Bit7 Bit6 Bit5 Bit4 0x03 Part Number STC5455 rev 3.1.1 Preliminary Bit3 Bit2 C Description Industrial Temperature Range Model (-40°C ~ +85 °C) Page 50 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Specification Modification This section lists the changes to STC5455 specification from previous revision. Current revision is STC5455 rev 3.1.1. • • • • Add a frame mux to allow user to select Frame8K or Frame2K for clock output CLK2. See register Frame_Mux and CLK2_Sel. Synthesizer GT4 is no longer frequency and phase skew programmable. Its frequency is fixed at 2.048MHz. Change synthesizer G4 to synthesizer G2. Remove LVCMOS level for REF4 and REF5. Preliminary Page 51 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Application Notes This section describes typical application use of the STC5455 device. The General section applies to all application variations. General Power and Ground Well-planned noise-minimizing power and ground are essential to achieving the best performance of the device. The device requires 3.3V digital power and analog power input. It is desirable to provide individual 0.1uF bypass capacitors, located close to the chip, for each of the power input leads, subject to board space and layout constraints. Ground should be provided by as continuous a ground plane as possible. A separated analog ground plane is recommended. Note: Un-used reference inputs must be grounded. 3.3V digital power inputs VCC MCLK OCXO/ TCXO STC5455 Digital ground 3.3V analog power inputs Analog ground AVCC GND AGND Figure 12: Power and Ground Master Oscillator An external 3.3V LVCMOS level clock (generally driven from TCXO or OCXO) is supplied at pin MCLK as master clock. TCXO or OCXO should be carefully chosen as required by application. It is recommended that the oscillator is placed close to the STC5455. Frequency of the master oscillator has four options, see description of the register MCLK Freq Reset for details. Preliminary Page 52 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Mechanical Specification Preliminary Page 53 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Revision History The following table summarizes significant changes made in each revision. Additions reference current pages. Revision P1 Change Description Pages Initial datasheet at Preliminary status P1.1 Add mechanical specifications 51 P1.2 Correct SDI of SPI Bus Timing, Write access 27 P1.3 Update Functional diagram 1 Remove LVCMOS level for REF4 and REF5 1, 6, 14, 20, Add register Frame_Mux 9, 45 Change register CLK8K_Sel and CLK2K_Sel to Frame8K_Sel and CLK2K_Sel 9, 44 Change name of register Ref_Freq to Ref_Acceptable_Freq 11, 20, 31, 44, Add description of frame mux 23 Update CLK3~CLK8, CLK8K and CLK2K detail diagram in Figure 6, 7 23 Correct tCH and tCL, LSB to MSB and MSB to LSB in serial bus timing figure 27 Correct description of tCSHLD and tCSTRI in serial bus timing table 27 Update register description of Bucket_Size, Ref_Info, Interrupt_Event_Sts, PLL_Event_Out, PLL_Event_In, CLK2_Sel, Synth_Index_Select, Synth_Freq_Value, Synth_Skew_Adj, Control_Mode Preliminary 26, 27 Correct Min value of tCH and tCL to 50ns in serial bus timing table 29, 31, 32, 39, 40, 41, 42, 43, Correct default value of register Frame8K_Sel and Frame2K_Sel 44 Update order information 50 Add section of Specification Modification 51 Change synthesizer G4 to G2 All pages Miscellaneous All pages Page 54 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Preliminary Page 55 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011 STC5455 Synchronous Clock for SETS Data sheet Information furnished by Connor-Winfield is believed to be accurate and reliable. However, no responsibility is assumed by Connor-Winfield for its use, nor for any infringements of patents or other rights of third parties that my result from its use. Specifications subject to change without notice. For more information, contact: Preliminary 2111 Comprehensive DR Aurora, IL. 60505, USA 630-851-4722 630-851-5040 FAX www.conwin.com Page 56 of 56 TM121 Rev:P1.3 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Date: October 24, 2011