Calculating Skew Margin for 217/218

Aeroflex Colorado Springs Application Note
AN-LVDS-012-01
Calculating Skew Margin for a UT54LVDS217 and UT54LVDS218 Link
Table 1: Cross Reference of Applicable Products
Manufacturer Part
SMD #
Number
3.0V SERIALIZER
UT54LVDS217
5962-01534
Product Name:
3.0V DESERIALIZER
UT54LVDS218
5962-01535
Device
Type
01, 02
Internal PIC
01, 02
WD11,
WD13
WD12,
WD14
1.0 Overview
Receiver Input Skew Margin (RSKM) is defined as the total available margin after accounting for transmitter
pulse (TPPosN), receiver strobe (RSPosN), jitter, and interconnect media dependent factors. To ensure
proper functionality of a LVDS link, the system designer must consider the factors that can cause errors
during the high speed data transmission between the UT54LVDS217 Serializer and UT54LVDS218
Deserializer.
This application note provides jitter, TPPosN, RSPosN data, and an example calculation for receiver skew
margin (RSKM). NOTE: The data in this application note is not guaranteed and intended to be used as a
REFRENCE ONLY.
Tx CLK IN
PLL
UT54LVDS218
100 Ω
100 Ω
100 Ω
100 Ω
LVDS-TO-PARALLEL TTL
TxIN0
TxIN1
TxIN
TxIN3
TxIN4
TxIN5
TxIN6
TxIN7
TxIN8
TxIN9
TxIN10
TxIN11
TxIN12
TxIN13
TxIN14
TxIN15
TxIN16
TxIN17
TxIN18
TxIN19
TxIN20
TTL PARALLEL-TO-LVDS
UT54LVDS217
PLL
PowerDown
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT10
RxOUT11
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT16
RxOUT17
RxOUT18
RxOUT19
RxOUT20
Rx CLK OUT
PowerDown
Figure 1. Standard UT54LVDS217 and UT54LVDS218 Configuration
Creation Date: June 20, 2011
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2.0 RSKM Factors
RSKM(LeftSide)
RSKM(RightSide)
Ideally the receiver strobe would occur directly in the middle of the strobe position window (RSPosN(MIN) and
RSPosN(MAX)) and sample data correctly. Due to several factors that decrease the width of the sampling window, a
skew margin is required to ensure valid data is sampled correctly by the UT54LVDS218 receiver. Figure 2 details the
main factors that reduce the receiver strobe position window. The values calculated for variables A, B, C, and D must
be divided in half and distributed on each side of the ideal strobe position.
Figure 2. UT54LVDS218 RSKM diagram
A = Transmitter Pulse Variation (from ideal) TPPosN(MAX) - TPPosN(MIN)
A  TPPosN ( MAX )  TPPosN ( MIN )
B = Cable Skew, (typically 10-40ps per foot), and ISI (Inter symbol interference) both are media dependant.
B = SKEW * Cable Length
C = Set up and hold times for UT54LVDS218. (RSPosN(MIN)) and (RSPosN(MAX))
C = RSPOSn0(MAX) to RSPosN(MAX)
D = Total Source Clock Jitter, from UT54LVDS217
D = (See Figure 3)
Creation Date: June 20, 2011
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Modification Date:
3.0 EXAMPLE Calculating Bit0
This example estimates the skew budget for bit 0 transferred from the UT54LVDS217 to the UT54LVDS218
operating at 25MHz. Please reference Application note AN-LVDS-011 “UT54LVDS217 Transmitter Pulse
Position (TPPosN) and UT54LVDS218 Receiver Strobe Position (RSPosN) Estimate Over Frequency” for
TPPosN and RSPosN values at different frequencies.
Calculate Bit Width:
25MHz 
1
 40.00ns
25MHz
There are 7 bits in the bit stream:
Bit Width 
40.0ns
 5.7143ns  5714.3 ps
7
Using the “Estimated RSPosN” and “Estimated TPPosN” figures in application note AN-LVDS-011 we obtain the
estimated pulse and strobe positions for the UT54LVDS218 and UT54LVDS217 operating at 25MHz.
A:
TPPon0(MAX)@25MHz = 0.08ns
TPPos0(MIN)@25MHz = -0.05ns
From AN-LVDS-011
From AN-LVDS-011
TPPon0(MAX)-TPPos0(MIN) = (0.08ns)-(-0.05ns) =0.13ns
A 0.13ns

 0.65ns  650 ps
2
2
B: Assume the UT54LVDS217 and UT43LVDS218 are connected using a 1 meter cable and the cable characteristics
are listed as 13ps SKEW/foot and ISI=0.
B = (13ps)*(3.2808 foot) = 42.65ps SKEW from the 1 meter cable
B 42.65

 21.32 ps
2
2
NOTE: B will change depending on system interconnect media.
Calculate the amount of skew per foot, inch, mm, meter, etc for the interconnect layer. Cable Skew
changes depending on the cables or PCB traces in the system. Contact the cable manufacturer or figure
out your PCB trace parasitics and use that number here. This example assumed a 1 meter cable with
13ps SKEW/foot.
C:
RSPOSn0(MAX)@25MHz = RSPosN(MAX) for Bit0 = 2.77ns = 2770ps From AN-LVDS-011
RSPOSn0(MIN)@25MHz = RSPosN(MIN) for Bit0 = 1.72ns = 1720ps From AN-LVDS-011
Creation Date: June 20, 2011
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D: For this example assume temperature is 25°C, VDD=3.3V, the Serializers jitter is estimated using Figure 4 below.
Please note that jitter for the UT54LVDS217 varies little over temperature, so the data at 25°C provides a sufficient
estimate.
217 Jitter (25MHz ) 
Jitter (20MHz )  Jitter (32.4 MHz ) (303.7 ps )  (179.8 ps )

 241.75 ps 1720ps
2
2
D 241.75 ps

 120.87 ps
2
2
Estimated UT54LVDS217 Clock Jitter
Temp =25C
2500
Jitter (ps)
2000
2.7V
1500
3.0V
1000
3.3V
500
3.6V
0
0
20
40
60
80
Frequency (MHz)
Figure 3. Estimated Serializer clock jitter at 25°C
Creation Date: June 20, 2011
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Plugging variables A, B, C, and D to the RSKM budget, Figure 4:
A
= 650ps
2
B
= 21.32ps
2
C
= 1720ps to 2770ns
2
D
= 120.87ps
2
RSKM ( LeftSide)  927.81 ps
RSKM ( RightSide)  2152.11 ps
Figure 4. EXAMPLE Bit0 RSKM calculation diagram
4.0 Summary
Estimating for TPPosN and RSPosN for various clock frequencies aids the system designer in calculating the
skew budget for the 217/218 system, as well as cable selection. Using data presented in AN-LVDS-011,
UT54LVDS217 jitter data, and interconnect media factors, RSKM can be estimated. Estimating the receiver
skew margin available in a system helps ensure proper functionality of a LVDS link between the
UT54LVDS217 Serializer and UT54LVDS218 Deserializer.
Creation Date: June 20, 2011
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