DS90CR218A +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz General Description Features The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. When operating at the maximum input clock rate of 85 Mhz, the LVDS data is received at 595 Mbps per data channel for a total data throughput of 1.785 Gbit/sec (233 Mbytes/sec). The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces. n n n n n n n n n n n n Block Diagram Connection Diagrams 12 to 85 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption ± 1V common-mode range (around +1.2V) Narrow bus reduces cable size and cost Up to 1.785 Gbps throughput Up to 223 Mbytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Low profile 48-lead TSSOP package DS90CR218A 10108027 Order Number DS90CR218AMTD See NS Package Number MTD48 10108022 DS90CR218A © 2006 National Semiconductor Corporation DS101080 www.national.com DS90CR218A +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link- 12 MHz to 85 MHz October 2006 DS90CR218A Typical Application 10108023 www.national.com 2 DS90CR218A ESD Rating If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.5V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) Junction Temperature Recommended Operating Conditions Min Nom Max Units −65˚C to +150˚C Supply Voltage (VCC) Lead Temperature (Soldering, 4 sec.) 3.0 3.3 3.6 V −10 +25 +70 ˚C Operating Free Air +260˚C Temperature (TA) Maximum Package Power Dissipation @ +25˚C Receiver Input Range MTD48 (TSSOP) Package: DS90CR218A > ± 300mA Latch Up Tolerance @ 25˚C +150˚C Storage Temperature Range > 7kV > 700V (HBM, 1.5kΩ, 100pF) (EIAJ, 0Ω, 200pF) −0.3V to +4V CMOS/TTL Input Voltage 15 mW/˚C above +25˚C 0 2.4 Supply Noise Voltage (VCC) 1.89 W V 100 mVPP Package Derating Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA VCL Input Clamp Voltage ICL = −18 mA IIN Input Current VIN = 0.4V, 2.5V or VCC IOS Output Short Circuit Current VOUT = 0V 2.7 VIN = GND −10 3.3 V 0.06 0.3 V −0.79 −1.5 V +1.8 +15 µA −120 mA 0 −60 µA LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM = +1.2V +100 −100 mV mV VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V ± 10 ± 10 µA µA RECEIVER SUPPLY CURRENT ICCRW ICCRZ Receiver Supply Current Worst Case Receiver Supply Current Power Down CL = 8 pF, Worst Case Pattern (Figures 1, 2) f = 33 MHz 49 60 mA f = 40 MHz 53 65 mA f = 66 MHz 78 100 mA f = 85 MHz 90 115 mA PWR DWN = Low Receiver Outputs Stay Low during Powerdown Mode 140 400 µA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD). 3 www.national.com DS90CR218A Absolute Maximum Ratings (Note 1) DS90CR218A Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter CLHT CMOS/TTL Low-to-High Transition Time (Figure 2) CHLT CMOS/TTL High-to-Low Transition Time (Figure 2) RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 8) RSPos1 RSPos2 Min Typ Max Units 2.0 3.5 ns 1.8 3.5 ns 0.49 0.84 1.19 ns Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns 10.57 10.92 11.27 ns RSPos6 Receiver Input Strobe Position for Bit 6 RSKM RxIN Skew Margin (Note 4) (Figure 9) f = 85 MHz f = 85 MHz 0.49 ns f = 12MHz 2.01 ns RCOP RxCLK OUT Period (Figure 3) 11.76 RCOH RxCLK OUT High Time (Figure 3) RCOL RxCLK OUT Low Time (Figure 3) RSRC RxOUT Setup to RxCLK OUT (Figure 3) 3.5 f = 85 MHz T 83.33 4 5 6.5 ns 3.5 5 6 ns RHRC RxOUT Hold to RxCLK OUT (Figure 3) 3.5 RCCD RxCLK IN to RxCLK OUT Delay @ 25˚C, VCC = 3.3V (Note 5)(Figure 4) 5.5 RPLLS RPDD ns ns ns 7 9.5 ns Receiver Phase Lock Loop Set (Figure 5) 10 ms Receiver Powerdown Delay (Figure 7) 1 µs Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the receiver input setup and hold time (internal data sampling window). This margin do not take into account the Transmitter Pulse Position (TPPOS) variance and is measured using the ideal TPPOS. This margin allows LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and source clock jitter less than 250 ps. Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 217/287 transmitter and 218A/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. AC Timing Diagrams 10108002 FIGURE 1. “Worst Case” Test Pattern www.national.com 4 DS90CR218A AC Timing Diagrams (Continued) 10108005 10108006 FIGURE 2. DS90CR218A (Receiver) CMOS/TTL Output Load and Transition Times 10108010 FIGURE 3. DS90CR218A (Receiver) Setup/Hold and High/Low Times 10108012 FIGURE 4. DS90CR218A (Receiver) Clock In to Clock Out Delay 5 www.national.com DS90CR218A AC Timing Diagrams (Continued) 10108014 FIGURE 5. DS9OCR218A (Receiver) Phase Lock Loop Set Time 10108016 FIGURE 6. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs 10108018 FIGURE 7. Receiver Powerdown Delay www.national.com 6 DS90CR218A AC Timing Diagrams (Continued) 10108028 FIGURE 8. Receiver LVDS Input Strobe Position 7 www.national.com DS90CR218A AC Timing Diagrams (Continued) 10108020 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos Ideal — Calculated Transmitter output pulse position RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 6) + ISI (Inter-symbol interference) (Note 7) + TPPOS variance (Tx dependent) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 6: Cycle-to-cycle jitter is less than 250 ps at 85MHz Note 7: ISI is dependent on interconnect length; may be zero FIGURE 9. Receiver LVDS Input Skew Margin Applications Information DS90CR218A Pin Descriptions — Channel Link Receiver Pin Name RxIN+ I/O No. I 3 Positive LVDS differential data inputs. Description RxIN− I 3 Negative LVDS differential data inputs. RxOUT O 21 TTL level data outputs. RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT. PWR DWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. VCC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL VCC I 1 Power supply for PLL. PLL GND 1 2 Ground pin for PLL. LVDS VCC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and shorter cable lengths ( < 2m), the media electrical performance is less critical. For higher speed/long distance applications the media’s performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at distances as great as 5 meters and with the maximum data transfer of 1.785 Gbit/s. Additional applications information can be found in the following National Interface Application Notes: www.national.com AN = #### 8 Topic AN-1041 Introduction to Channel Link AN-1108 Channel Link PCB and Interconnect Design-In Guidelines AN-1109 Multi-Drop Channel-Link Operation AN-806 Transmission Line Theory AN-905 Transmission Line Calculations and Differential Impedance AN-916 Cable Information all be HIGH; if the clock input is also floating/terminated, data outputs will remain in the last valid state. A floating/ terminated clock input will result in a HIGH clock output. (Continued) CABLES A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The ideal cable/ connector interface would have a constant 100Ω differential impedance throughout the path. It is also recommended that cable skew remain below 90ps (@ 85 MHz clock rate) to maintain a sufficient data sampling window at the receiver. BOARD LAYOUT To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid to the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise canceling of the differential signals. The board designer should also try to maintain equal length on signal traces for a given differential pair. As with any high-speed design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the differential pair. Care should be taken to ensure that the differential trace impedance match the differential impedance of the selected physical media (this impedance should also match the value of the termination resistor that is connected across the differential pair at the receiver’s input). Finally, the location of the CHANNEL LINK TxOUT/RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs. All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance and EMI. In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance ground provides a common-mode return path for the two devices. Some of the more commonly used cable types for point-topoint applications include flat ribbon, flex, twisted pair and Twin-Coax. All are available in a variety of configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point applications while TwinCoax is good for short and long applications. When using ribbon cable, it is recommended to place a ground line between each differential pair to act as a barrier to noise coupling between adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All extended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless of the cable type. This overall shield results in improved transmission parameters such as faster attainable speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI. UNUSED INPUTS All unused outputs at the RxOUT outputs of the receiver must then be left floating. The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent results. However, the best overall performance has been seen when using Twin-Coax cable. Twin-Coax has very low cable skew and EMI due to its construction and double shielding. All of the design considerations discussed here and listed in the supplemental application notes provide the subsystem communications designer with many useful guidelines. It is recommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution. TERMINATION Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK chipset will normally require a single 100Ω resistor between the true and complement lines on each differential pair of the receiver input. The actual value of the termination resistor should be selected to match the differential mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 10 shows an example. No additional pull-up or pull-down resistors are necessary as with some other differential technologies such as PECL. Surface mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively terminate the differential lines. RECEIVER FAILSAFE FEATURE These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, data outputs will 10108024 FIGURE 10. LVDS Serialized Link Termination 9 www.national.com DS90CR218A Applications Information DS90CR218A Applications Information (Continued) CLOCK JITTER The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example, a 85 MHz clock has a period of 11.76 ns which results in a data bit width of 1.68 ns. Differential skew (∆t within one differential pair), interconnect skew (∆t of one differential pair to another) and clock jitter will all reduce the available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew budget. DECOUPLING CAPACITORS Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are 0.1 µF, 0.01 µF and 0.001 µF. An example is shown in Figure 11. The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the number of bypass capacitors, the PLL VCC should receive the most filtering/ bypassing. Next would be the LVDS VCC pins and finally the logic VCC pins. COMMON-MODE vs. DIFFERENTIAL MODE NOISE MARGIN The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100 mV threshold therefore providing approximately 200 mV of differential noise margin. Common-mode protection is of more importance to the system’s operation due to the differential data transmission. LVDS supports an input voltage range of Ground to +2.4V. This allows for a ± 1.0V shifting of the center point due to ground potential differences and common-mode noise. 10108025 FIGURE 11. CHANNEL LINK Decoupling Configuration www.national.com 10 inches (millimeters) unless otherwise noted Order Number DS90CR218AMTD Dimensions in millimeters only NS Package Number MTD48 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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