Standard Products UT54LVDS217 Serializer Data Sheet May 8, 2007 FEATURES INTRODUCTION The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. 15 to 75 MHz shift clock support Low power consumption Power-down mode <216μW (max) Cold sparing all pins Narrow bus reduces cable size and cost Up to 1.575 Gbps throughput Up to 197 Megabytes/sec bandwidth 325 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge strobe Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 300 krad(Si) and 1 Mrad(Si) - Latchup immune (LET > 100 MeV-cm2/mg) Packaging options: - 48-lead flatpack Standard Microcircuit Drawing 5962-01534 - QML Q and V compliant part TRANSMIT CLOCK IN The UT54LVDS217 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size. All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS. TTL PARALLEL-TO-LVDS TTL PARALLEL -TO-LVDS 21 CMOS/TTL INPUTS At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec). PLL POWER DOWN Figure 1. UT54LVDS217 Serializer Block Diagram 1 DATA (LVDS) CLOCK (LVDS) PIN DESCRIPTION TxIN4 1 48 TxIN3 VDD 47 TxIN5 2 3 46 TxIN2 GND TxIN6 GND 4 5 TxIN7 6 45 44 43 TxIN1 TxIN0 N/C TxIN8 7 42 VDD TxIN9 8 9 41 LVDS GND TxOUT0- 40 TxOUT0+ TxIN10 10 11 39 TxOUT1- GND 38 TxOUT1+ TxIN11 TxIN12 12 13 LVDS VDD LVDS GND UT54LVDS217 Pin Name Description I/O No. TxIN I 21 TTL level input TxOUT+ O 3 Positive LVDS differential data output TxOUT- O 3 Negative LVDS differential data output TxCLK IN I 1 TxCLK OUT+ O 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN Positive LVDS differential clock output TxCLK OUT- O 1 Negative LVDS differential clock output PWR DWN I 1 14 37 36 35 TxIN13 15 34 TxOUT2+ TxIN14 16 I 4 GND 17 33 32 VDD TTL level input. Assertion (low input) TRISTATEs the clock and data outputs, ensuring low current at power down. Power supply pins for TTL inputs and logic TxCLK OUTTxCLK OUT+ GND I 5 Ground pins for TTL inputs and logic TxIN15 31 LVDS GND PLL VDD I 1 Power supply pins for PLL TxIN16 18 19 30 PLL GND PLL GND I 2 Ground pins for PPL TxIN17 VDD 20 21 29 PLL VDD LVDS VDD I 1 Power supply pin for LVDS output PLL GND PWR DWN LVDS GND I 3 Ground pins for LVDS outputs VDD TxIN18 22 TxIN19 23 28 27 26 GND 24 25 Figure 2. UT54LVDS217 Pinout UT54LVDS217 TxIN TxOUT2- TxCLK IN TxIN20 LVDS CABLE MEDIA DEPENDENT DATA (LVDS) UT54LVDS218 RxOUT 0 1 2 0 1 2 CMOS/ TTL 18 19 20 18 19 20 CLOCK (LVDS) TxCLK RxCLK GND PCB PCB SHIELD Figure 3. UT54LVDS217 Typical Application ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.3 to 4.0V VI/O Voltage on any pin4 -0.3 to (VDD + 0.3V) TSTG Storage temperature -65 to +150°C PD Maximum power dissipation TJ Maximum junction temperature2 +150°C Thermal resistance, junction-to-case3 10°C/W DC input current ±10mA ΘJC II 2W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175°C during burn-in and lifetest. 3. Test per MIL-STD-883, Method 1012. 4. For cold spare mode (VDD = VSS), VI/O may be 0.3V to the maximum recommended operating VDD + 0.3V. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD, PLLVDD, LVDS VDD Positive supply voltage 3.0 to 3.6V TC Case temperature range -55 to +125°C VIN DC input voltage 0V to VDD 3 DC ELECTRICAL CHARACTERISTICS1 SYMBOL (VDD = 3.3V-0.3V; -55°C < TC < +125°C) PARAMETER CONDITION MIN MAX UNIT CMOS/TTL DC SPECIFICATIONS VIH High-level input voltage 2.0 VDD V VIL Low-level input voltage GND 0.8 V IIH High-level input current VIN = 3.6V; VDD = 3.6V -10 +10 μA IIL Low-level input current VIN = 0V; VDD = 3.6V -10 +10 μA VCL Input clamp voltage ICL = -18mA -1.5 V ICS Cold Spare Leakage current VIN = 3.6V; VDD = VSS -20 +20 μA 250 400 mV 35 mV 1.410 V 35 mV LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) VOD5 Differential Output Voltage RL = 100Ω (See Figure 14) ΔVOD5 Change in VOD between complimentary output states RL = 100Ω (See Figure 14) Offset Voltage + Vol-⎞ -------------------------RL = 100Ω, ⎛⎝ Vos = Voh ⎠ VOS5 1.120 2 ΔVOS5 Change in VOS between complimentary output states RL = 100Ω IOZ4 Output Three-State Current PWR DWN = 0V VOUT = 0V or VDD -10 +10 μΑ ICSOUT Cold Spare Leakage Current VIN=3.6V, VDD = VSS -20 +20 μΑ IOS2,3 Output Short Circuit Current VOUT+ or VOUT- = 0V 5mA mA Transmitter supply current with loads RL = 100Ω all channels (figure 5) CL = 5pF, f = 50MHz 65.0 mA Power down current DIN = VSS PWR DWN = 0V, f = 0Hz 60.0 μA Supply Current ICCL4 ICCZ4,6 Notes: 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground. 2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, for a maximum duration of one second. 3. Guaranteed by characterization. 4. Devices are tested @ 3.6V only. 5. Clock outputs guaranteed by design. 6. Post 100Krad and 300Krad, ICCZ = 200μA. 4 AC SWITCHING CHARACTERISTICS1 (VDD = 3.0V to 3.6V; TA = -55°C to +125°C) SYMBOL PARAMETER MIN MAX UNIT LLHT2 LVDS Low-to-High Transition Time (Figure 5) 1.5 ns LHLT2 LVDS High-to-Low Transition Time (Figure 5) 1.5 ns TPPos02 Transmitter Output Pulse Position for Bit 0 (Figure 13) f=75MHz -0.18 0.270 ns TPPos12 Transmitter Output Pulse Position for Bit 1(Figure 13) f=75MHz 1.72 2.17 ns TPPos22 Transmitter Output Pulse Position for Bit 2 (Figure 13) f=75MHz 3.63 4.08 ns TPPos32 Transmitter Output Pulse Position for Bit 3 (Figure 13) f=75MHz 5.53 5.98 ns TPPos42 Transmitter Output Pulse Position for Bit 4 (Figure 13) f=75MHz 7.44 7.89 ns TPPos52 Transmitter Output Pulse Position for Bit 5 (Figure 13) f=75MHz 9.34 9.79 ns TPPos62 Transmitter Output Pulse Position for Bit 6 (Figure 13) f=75MHz 11.25 11.70 ns 0.45 ns 13.3 66.7 ns TCCS3 Channel to Channel skew (Figure 7) TCIP TxCLK IN Period (Figure 8) TCIH4 TxCLK IN High Time (Figure 8) 0.35Tcip 0.65Tcip ns TCIL4 TxCLK IN Low Time (Figure 8) 0.35Tcip 0.65Tcip ns TSTC2 TxIN Setup to TxCLK IN (Figure 8) 15MHz 75MHz THTC2 TxIN Hold to TxCLK IN (Figure 8) 15MHz 75MHz TCCD TxCLK IN to TxCLK OUT Delay (Figure 9) TPLLS TPDD 1.0 0.5 ns 0.7 0.5 ns 2.5 ns Transmitter Phase Lock Loop Set (Figure 10) 10 ms Transmitter Powerdown Delay (Figure 12) 100 ns Notes: 1. Recommend transistion time for TXCLK In is 1.0 to 6.0 ns (figure 6). 2. Guaranteed by characterization. 3. Channel to channel skew is defined as the difference between TPPOS max limit and TPPOS minimum limit. 4. Guaranteed by design. 0.5 T TxCLK IN TxIN Figure 4. Test Pattern AC TIMING DIAGRAMS Vdiff=(TxOUT+) - (TxOUT-) 80% 20% Vdiff TxOUT+ 5pF 80% 20% LLHT 100Ω LHLT TxOUT- Figure 5. UT54LVDS217 Output Load and Transition Times 90% 90% 10% 10% TXCLK IN TCIT TCIT Figure 6. UT54LVDS217 Input Clock Transition Time TCCS TxOUT0 Vdiff= 0V TxOUT1 TxOUT2 TxCLK OUT TIME Notes: 1. Measurements at VDIFF = 0V 2. TCCS measured between earliest and latest LVDS edges. 3. TxCLK Differential Low-High Edge. Figure 7. UT54LVDS217 Channel-to-Channel Skew TCIP VDD/2 Sample on L-H Edge VDD/2 VDD/2 TxCLK IN TCIH TCIL TSTC TxIN 0-20 VDD/2 THTC HOLD SETUP VDD/2 Figure 8. UT54LVDS217 Setup/Hold and High/Low Times TxCLK IN VDD/2 TCCD TxCLK OUT Vdiff= 0V Figure 9. UT54LVDS217 Clock-to-Clock Out Delay VDD VDD/2 POWER DOWN VDD VDD/2 VDD TPLLS TxCLK IN TxCLK OUT / Vdiff = OV RxCLK IN Figure 10. UT54LVDS217 Phase Lock Loop Set Time TxCLK OUT / RxCLK IN Previous Cycle TxOUT2 / RxIN2 TxOUT1 / Next Cycle TxIN15-1 TxIN14-1 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN8-1 TxIN7-1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN6 TxIN5 TxIN4 TxIN3 RxIN1 TxOUT0 / RxIN0 TxIN1-1 TxIN0-1 TxIN2 TxIN1 TxIN0 Figure 11. UT54LVDS217 Parallel TTL Data Inputs Mapped to LVDS Outputs POWER DOWN VDD/2 TxCLK IN TPDD THREE-STATE TxOUT Figure 12. Transmitter Powerdown Delay TCLK TxCLK OUT / Differential Previous Cycle TxOUT2 / (Single ended) TxOUT1 / Next Cycle TxIN15-1 TxIN14-1 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN8-1 TxIN7-1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN6 TxIN5 TxIN4 TxIN3 Single ended TxOUT0 / Single ended TxIN1-1 TxIN0-1 TxIN2 TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 Figure 13. LVDS Output Pulse Position Measurement TxIN1 TxIN0 DOUT+ 20pF DIN D Generator RL = 100Ω 50Ω Driver Enabled 20pF DOUT- Figure 14. Driver VOD and VOS Test Circuit or Equivalent Circuit VOD PACKAGING 5 6 4 6 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. 5. ID mark symbol is vendor option. 6. With solder, increase maximum by 0.003. Figure 15. 48-Lead Flatpack 11 ORDERING INFORMATION UT54LVDS217 Serializer: UT 54LVDS217 - * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (U) = 48-lead Flatpack (dual-in-line) Access Time: Not applicable Device Type: UT54LVDS217 Serializer Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C. Radiation neither tested nor guaranteed. 12 UT54LVDS217 Serializer: SMD 5962 - 01534 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 48 lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 01 = 50MHz LVDS Serializer (contacat factory) 02 = 75MHz LVDS Serializer Drawing Number: 01534 Total Dose (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) (G) = 5E5 rad(Si) (H) = 1E6 rad(Si) Federal Stock Class Designator: No Options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 13 Aeroflex Colordo Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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