Aeroflex Colorado Springs Application Note AN-LVDS-011-01 UT54LVDS217 Transmitter Pulse Position (TPPosN) and UT54LVDS218 Receiver Strobe Position (RSPosN) Estimate Over Frequency Table 1: Cross Reference of Applicable Products Manufacturer Part SMD # Number 3.0V SERIALIZER UT54LVDS217 5962-01534 Product Name: 3.0V DESERIALIZER UT54LVDS218 5962-01535 Device Type 01, 02 01, 02 Internal PIC WD11, WD13 WD12, WD14 1.0 Overview The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock (Tx CLK IN) 21 bits of input data are sampled and transmitted. The UT54LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a rate of 525Mbps per LVDS data channel. Using a 75MHz clock, the data throughput is 1.575 Gbps. This application note provides estimates of Transmitter Strobe Position, TPPosN, and Receiver Strobe Position, RSPosN, for 25 to 75 MHz. TPPosN and RSPosN values for various frequencies are necessary for estimating system timing requirements and calculating Receiver Input Skew Margin, RSKM. See APP-LVDS-012 for an example of how to calculate RSKM. Tx CLK IN PLL UT54LVDS218 100 Ω 100 Ω 100 Ω 100 Ω LVDS-TO-PARALLEL TTL TxIN0 TxIN1 TxIN TxIN3 TxIN4 TxIN5 TxIN6 TxIN7 TxIN8 TxIN9 TxIN10 TxIN11 TxIN12 TxIN13 TxIN14 TxIN15 TxIN16 TxIN17 TxIN18 TxIN19 TxIN20 TTL PARALLEL-TO-LVDS UT54LVDS217 PLL PowerDown Figure 1. Standard UT54LVDS217 and UT54LVDS218 Configuration Creation Date: May 26, 2011 Page 1 of 13 Modification Date: RxOUT0 RxOUT1 RxOUT2 RxOUT3 RxOUT4 RxOUT5 RxOUT6 RxOUT7 RxOUT8 RxOUT9 RxOUT10 RxOUT11 RxOUT12 RxOUT13 RxOUT14 RxOUT15 RxOUT16 RxOUT17 RxOUT18 RxOUT19 RxOUT20 Rx CLK OUT PowerDown 2.0 TPPosN and RSPosN Data The UT54LVDS217 Serializer, 217, and the UT54LVDS218 Deserializer, 218, are ideal for applications where a high speed, low power, and low harness mass is required. The recommended operating frequencies for these devices are 25MHz to 75MHz. Both the 217 and 218 datasheets and corresponding SMDs contain AC Switching Characteristics for 75MHz only. 75MHz operation presents the worst case, or narrowest pulse and strobe position windows. Many system designers require an estimate of TPPosN and RSPosN performance at frequencies less than 75MHz. Figures 2 – 15 are intended to provide estimates of TPPosN and RSposN. Using the data contained in Tables 2, 3, 4, and 5 trend lines can be extrapolated from the 25MHz and 75MHz data. These graphs which allow a system designer to estimate how the min/max TPPosN and min/max RSPosN shift with respect to the input clock frequency. Data in Tables 2 - 7 is NOT GUARANTEED Figure 2. UT54LVDS217 TPPosN Timing Diagram from Datasheet Creation Date: May 26, 2011 Page 2 of 13 Modification Date: Table 2. UT54LVDS217 the Transmitter Output Pulse Positions at 25MHz UT54LVDS217 TRANSMITTER SWITCHING CHARACTERISTICS SYMBOL TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 PARAMETER Transmitter Output Pulse Position for Bit 0 Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 f=25MHz f=25MHz f=25MHz f=25MHz f=25MHz f=25MHz MIN MAX UNIT -0.05 5.67 11.37 17.05 22.81 28.49 34.18 0.08 5.84 11.57 17.25 23.03 28.73 34.49 ns ns ns ns ns ns ns Table 3. UT54LVDS217 the Transmitter Output Pulse Positions at 50MHz UT54LVDS217 TRANSMITTER SWITCHING CHARACTERISTICS SYMBOL TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 PARAMETER Transmitter Output Pulse Position for Bit 0 Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 f=50MHz f=50MHz f=50MHz f=50MHz f=50MHz f=50MHz MIN MAX UNIT -0.13 0.02 3.04 3.23 5.67 5.82 8.52 8.72 11.56 11.73 14.19 14.34 17.30 17.47 ns ns ns ns ns ns ns Table 4. UT54LVDS217 the Transmitter Output Pulse Positions at 75MHz (From device datasheet) UT54LVDS217 TRANSMITTER SWITCHING CHARACTERISTICS SYMBOL TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 PARAMETER Transmitter Output Pulse Position for Bit 0 Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 Creation Date: May 26, 2011 f=75MHz f=75MHz f=75MHz f=75MHz f=75MHz f=75MHz Page 3 of 13 MIN MAX UNIT -0.18 1.72 3.63 5.53 7.44 9.34 11.25 0.27 2.17 4.08 5.98 7.89 9.79 11.7 ns ns ns ns ns ns ns Modification Date: Estimated TPPos0 0.3 0.25 0.2 0.15 (ns) 0.1 0.05 TPPos0MIN TPPos0MAX 0 -0.05 0 15 30 45 60 75 90 -0.1 -0.15 -0.2 -0.25 frequency (MHz) Figure 3. Estimated TPPos0 over frequency Estimated TPPos1 7 6 5 4 (ns) TPPos1MIN TPPos1MAX 3 2 1 0 0 15 30 45 60 75 90 frequency (MHz) Figure 4. Estimated TPPos1 over frequency Creation Date: May 26, 2011 Page 4 of 13 Modification Date: Estimated TPPos2 12 10 (ns) 8 TPPos2MIN 6 TPPos2MAX 4 2 0 0 15 30 45 60 75 90 frequency (MHz) Figure 4. Estimated TPPos2 over frequency Estimated TPPos3 20 18 16 14 (ns) 12 TPPos3MIN 10 TPPos3MAX 8 6 4 2 0 0 15 30 45 60 75 90 frequency (MHz) Figure 6. Estimated TPPos3 over frequency Creation Date: May 26, 2011 Page 5 of 13 Modification Date: Estimated TPPos4 24 22 20 (ns) 18 16 TPPos4MIN 14 TPPos4MAX 12 10 8 6 0 15 30 45 60 75 90 frequency (MHz) Figure 7. Estimated TPPos4 over frequency Estimated TPPos5 32 27 22 (ns) TPPos5MIN TPPos5MAX 17 12 7 0 15 30 45 60 75 90 frequency (MHz) Figure 8. Estimated TPPos5 over frequency Creation Date: May 26, 2011 Page 6 of 13 Modification Date: Estimated TPPos6 40 35 (ns) 30 TPPos6MIN 25 TPPos6MAX 20 15 10 0 15 30 45 60 75 90 frequency (MHz) Figure 9. Estimated TPPos6 over frequency Creation Date: May 26, 2011 Page 7 of 13 Modification Date: Figure 10. UT54LVDS218 RSPosN Timing Diagram from Datasheet Creation Date: May 26, 2011 Page 8 of 13 Modification Date: Table 5. UT54LVDS218 the Receiver Input Strobe Positions at 25MHz UT54LVDS218 RECEIVER SWITCHING CHARACTERISTICS SYMBOL RSPos0 RSPos1 RSPos2 RSPos3 RSPos4 RSPos5 RSPos6 PARAMETER Receiver Input Strobe Position for Bit 0 Receiver Input Strobe Position for Bit 1 Receiver Input Strobe Position for Bit 2 Receiver Input Strobe Position for Bit 3 Receiver Input Strobe Position for Bit 4 Receiver Input Strobe Position for Bit 5 Receiver Input Strobe Position for Bit 6 f=25MHz f=25MHz f=25MHz f=25MHz f=25MHz f=25MHz MIN MAX UNIT 1.72 7.43 13.15 18.88 24.58 30.28 36.00 2.77 8.49 14.22 19.93 25.64 31.35 37.08 ns ns ns ns ns ns ns Table 6. UT54LVDS218 the Receiver Input Strobe Positions at 50MHz UT54LVDS218 RECEIVER SWITCHING CHARACTERISTICS SYMBOL RSPos0 RSPos1 RSPos2 RSPos3 RSPos4 RSPos5 RSPos6 PARAMETER Receiver Input Strobe Position for Bit 0 Receiver Input Strobe Position for Bit 1 Receiver Input Strobe Position for Bit 2 Receiver Input Strobe Position for Bit 3 Receiver Input Strobe Position for Bit 4 Receiver Input Strobe Position for Bit 5 Receiver Input Strobe Position for Bit 6 f=50MHz f=50MHz f=50MHz f=50MHz f=50MHz f=50MHz MIN MAX UNIT 0.88 2.05 3.74 4.90 ns ns ns ns ns ns ns 6.60 7.77 9.46 10.62 12.31 13.47 15.17 16.34 18.03 19.19 Table 7. UT54LVDS218 the Receiver Input Strobe Positions at 75MHz (From device datasheet) UT54LVDS218 RECEIVER SWITCHING CHARACTERISTICS SYMBOL RSPos0 RSPos1 RSPos2 RSPos3 RSPos4 RSPos5 RSPos6 PARAMETER Receiver Input Strobe Position for Bit 0 Receiver Input Strobe Position for Bit 1 Receiver Input Strobe Position for Bit 2 Receiver Input Strobe Position for Bit 3 Receiver Input Strobe Position for Bit 4 Receiver Input Strobe Position for Bit 5 Receiver Input Strobe Position for Bit 6 Creation Date: May 26, 2011 f=75MHz f=75MHz f=75MHz f=75MHz f=75MHz f=75MHz Page 9 of 13 MIN MAX UNIT 0.5 2.41 4.31 6.22 8.12 10.03 11.93 1.24 3.15 5.05 6.96 8.86 10.77 12.67 ns ns ns ns ns ns ns Modification Date: Estimated RSPos0 3 2.5 (ns) 2 RSPos0MIN 1.5 RSPos0MAX 1 0.5 0 0 15 30 45 60 75 90 frequency (MHz) Figure 11. Estimated RSPos0 over frequency Estimated RSPos1 9 8 7 (ns) 6 RSPos1MIN 5 RSPos1MAX 4 3 2 1 0 15 30 45 60 75 90 frequency (MHz) Figure 12. Estimated RSPos1 over frequency Creation Date: May 26, 2011 Page 10 of 13 Modification Date: Estimated RSPos2 14 (ns) 12 10 RSPos2MIN RSPos2MAX 8 6 4 0 15 30 45 60 75 90 frequency (MHz) Figure 13. Estimated RSPos2 over frequency Estimated RSPos3 22 20 18 16 (ns) 14 RSPos3MIN 12 RSPos3MAX 10 8 6 4 2 0 15 30 45 60 75 90 frequency (MHz) Figure 14. Estimated RSPos3 over frequency Creation Date: May 26, 2011 Page 11 of 13 Modification Date: Estimated RSPos4 27 (ns) 22 RSPos4MIN 17 RSPos4MAX 12 7 0 15 30 45 60 75 90 frequency (MHz) Figure 15. Estimated RSPos4 over frequency Estimated RSPos5 29 24 (ns) RSPos5MIN RSPos5MAX 19 14 9 0 15 30 45 60 75 90 frequency (MHz) Figure 16. Estimated RSPos5 over frequency Creation Date: May 26, 2011 Page 12 of 13 Modification Date: Estimated RSPos6 36 (ns) 31 26 RSPos6MIN RSPos6MAX 21 16 11 0 15 30 45 60 75 90 frequency (MHz) Figure 17. Estimated RSPos6 over frequency 3.0 Summary Having estimates for TPPosN and RSPosN for various clock frequencies aids the system designer in figuring system timing requirements and calculating RSKM at frequencies in the range of 25 to 75MHz. See APP-LVDS-012 for an example of how to calculate RSKM. Creation Date: May 26, 2011 Page 13 of 13 Modification Date: