UT54ACS3G99S Triple ManyGate - Aeroflex Microelectronic Solutions

Standard Products
UT54ACS3G99S Triple ManyGate™
Configurable Logic Gate
Product Brief
June 2015
The most important thing we build is trust
Features
Introduction
Voltage Supply: 3.0V to 5.5V
Advanced CMOS technology
Schmitt Trigger Inputs
Tri-State Outputs
ESD rating HBM: 2000V, Class 2
Operational environment:
• Total dose: 1 Mrad(Si)
• Latchup immune (LET <= 100 MeV-cm2/mg)
Packaging:
• 20-lead flatpack (dual line)
Standard Microelectronics Drawing (SMD)
• QML Q, V Pending
The UT54ACS3G99S is Cobham Semiconductor Solutions’
(formerly Aeroflex) triple configurable multiple function logic
device with 3-state outputs and Schmitt inputs. The output-enable pin is active LOW (/OE). The 16 combinations of
4-bit inputs determines the output state when /OEx = Vss.
When /OEx = VDD the outputs are disabled.
The UT54ACS3G99S is configurable to logic functions, such
as: AND, OR, NAND, NOR, XOR, XNOR gate, inverter, buffer,
and MUX
/OE1
A1
B1
C1
/OE3
Y1
D1
A3
B3
C3
/OE2
Y3
D3
A2
B2
C2
Y2
D2
Figure 1. UT54ACS3G99S Logic Diagram
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1
Pin Definition/Description
Pin Definition/Description
Y2
Table 1.
Name
Description
/OEn
Active LOW output
enable
C3
2, 11, 16
An
A input
D3
3, 12, 17
Bn
B input
4, 13, 18
Cn
C input
5, 14, 19
Dn
D input
1, 6, 15
Yn
3-State Output
/OE2
VDD
Power supply pin
/OE1
Ground pin
VSS
20
10
VSS
2
19
3
B3
7, 8, 9
20
4
5
6
Y3
7
/OE3
8
9
UT54ACS3G99S
A3
Pin No.
1
18
17
16
15
14
13
VDD
D2
C2
B2
A2
Y1
D1
C1
12
B1
10
11
A1
Figure 2. UT54ACS3G99S Pinout Diagram
2
Functional Truth Tables and Operational Modes
Table 2. Combinatorial Truth Table An, Bn, Cn, Dn to n=1,2,3 of Storage Element Yn Output
Dn
Cn
Bn
An
OUTPUT to DIN
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
L
L
H
H
H
L
H
L
L
L
L
H
L
H
L
L
H
H
L
H
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
L
H
H
L
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
L
L
H
H
H
H
L
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Applications Information
Applications Information
Table 3. Equivalent Logic Functions Created from Table 2
PRIMARY Logic FUNCTION
COMPLEMENTARY Logic FUNCTION
3-state buffer
3-state inverter
3-state 2-in-1 data selector MUX
3-state 2-in-1 data selector MUX, inverted out
3-state 2-input AND
3-state 2-input NOR, both inputs inverted
3-state 2-input AND, one input inverted
3-state 2-input NOR, one input inverted
3-state 2-input AND, both inputs inverted
3-state 2-input NOR
3-state 2-input NAND
3-state 2-input OR, both inputs inverted
3-state 2-input NAND, one input inverted
3-state 2-input OR, one input inverted
3-state 2-input NAND, both inputs inverted
3-state 2-input OR
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Applications Information
Figure 3 20-lead Ceramic Flatpack
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UT*********
UT54ACS3G99S Synchronous Many Gate™ Logic Gate
UT54ACS3G99S Synchronous Many Gate™ Logic Gate
-*
*
*
*
Lead Finish: (NOTE 1 & 2)
(A)=Hot Solder Dipped
(C)=Gold
(X)=Factory option (gold or solder)
Screening Level: (NOTE 3)
(C) = HiRel flow (-55°C to +125°C)
(P) = Prototype flow (+25°C only)
Case Outline:
(U) = 20-lead Flatpack (dual-in-line)
Access Time
(-)
Device Type: ACS3GS99S
NOTES
1.
2.
3.
4.
Lead finish (A,C, or X) must be specified.
If an “X” is specified when ordering, then the part marking will match
the lead finish and will be either “A” (solder) or “C” (gold).
Prototype flow per Aeroflex Manufacturing Flows Document. Tested
at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor
guaranteed.
HiRel Temperature Range flow per Aeroflex Manufacturing Flows
Document. Devices are tested at -55°C, room temp, and +125°C.
Radiation neither tested nor guaranteed.
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UT54ACS3G99S Synchronous Many Gate™ Logic Gate: SMD
5
5962
UT54ACS3G99S Synchronous Many Gate™ Logic Gate: SMD
-
XXXXX
**
*
*
*
Lead Finish: (NOTE 1)
A
=
Solder
C
=
Gold
X
=
Optional
Case Outline: (NOTE 2)
(X)
=
20-lead ceramic bottom-brazed dual-in-line Flatpack
Screening Level:
(Q)
=
QML Class Q
(V)
=
QML Class V
Device Type:
(01) =
Drawing Number:
TBD
Total Dose:
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
NOTES
1.
2.
3.
Lead finish (A,C, or X) must be specified.
If an “X” is specified when ordering, part marking will match the lead
finish and will be either “A” (solder) or “C” (gold).
Total dose radiation must be specified when ordering. QML Q and
QML V not available without radiation hardening. For prototype
inquiries, contact factory.
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UT54ACS3G99S Synchronous Many Gate™ Logic Gate: SMD
This product is controlled for export under the U.S. Department of Commerce (DoC). A license may be
required prior to the export of this product from the United States.
Cobham Semiconductor Solutions
4350 Centennial Blvd
Colorado Springs, CO 80907
E: [email protected]
T: 800 645 8862
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi – Rel
Aeroflex Colorado Springs Inc., DBA Cobham Semiconductor Solutions, reserves the right to make changes to any products and services described
herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current
before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service
described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.
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