Standard Products UT54ACTQ16244 RadHard CMOS 16-bit Buffer/Line Driver, TTL Inputs, and Three-State Outputs Datasheet May 16, 2012 www.aeroflex.com/radhard LOGIC SYMBOL FEATURES OE1 16 non-inverting buffers with three-state outputs Guaranteed simultaneously switching noise level and dynamic threshold performance Separate control logic for each byte and nibble 0.6m Commercial RadHardTM CMOS - Total dose: 100K rad(Si) - Single Event Latchup immune High speed, low power consumption Output source/sink 24mA Standard Microcircuit Drawing 5962-06243 - QML compliant part Package: - 48-lead flatpack, 25 mil pitch (.390 x .640) (1) EN1 OE2 (48) OE3 (25) OE4 (24) EN2 EN3 EN4 I0 I1 The 16-bit wide UT54ACTQ16244 buffer/line driver is built using Aeroflex’s Commercial RadHardTM epitaxial CMOS technology and is ideal for space applications. This high speed, low power UT54ACTQ16244 buffer/line driver is designed to improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The UT54ACTQ16244 can be used as four 4-bit (nibble) buffers, two 8-bit (byte) buffers, or one 16-bit buffer. The device provides true outputs and symmetrical OE (activelow) output-enable inputs. The device is nibble controlled with each nibble functioning identically, but independent of each other. The control pins can be shorted together to obtain full 16-bit operation. 11 1 (3) (44) (5) (43) I3 (41) I4 (40) I5 (38) I6 (37) I7 (36) I8 (35) I9 (33) I10 (32) I11 (30) I12 (29) I13 (27) I14 (26) I15 (6) I2 DESCRIPTION (2) (47) (46) 1 1 2 3 (8) (9) (11) (12) (13) (14) (16) (17) 1 4 (19) O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 (20) O13 (22) O14 (23) O15 FUNCTION TABLE PIN DESCRIPTION Pin Names Description ENABLE OE1, OE2, OE3, OE4 Inputs I0-I3, I4-I7, I8-I11, I12-I15 Outputs O0-O3, O4-07, O8-O11, O12-O15 OEn Output Enable Input (Active Low) L L L I0-I15 Inputs L H H Outputs H X Z O0-O15 1 PINOUTS 48-Lead Flatpack Top View OE1 1 48 OE2 O0 2 47 I0 O1 3 46 VSS O2 4 5 45 44 I1 VSS I2 O3 6 43 I3 VDD 7 42 VDD O4 O5 VSS 8 9 10 41 40 39 I4 I5 VSS O6 11 38 I6 O7 12 37 I7 O8 13 36 I8 O9 VSS 14 15 35 34 I9 VSS O10 16 33 I10 O11 17 32 I11 VDD O12 O13 VSS 18 19 20 21 31 30 29 28 VDD I12 I13 VSS O14 O15 OE4 22 23 24 27 26 25 I14 I15 OE3 2 LOGIC DIAGRAM (1) OE1 (25) OE3 (47) (2) O0 I8 I1 (46) (3) O1 I2 (44) (5) I3 (43) (6) I0 (36) (13) O8 I7 (35) (14) O9 O2 I10 (33) (16) O10 O3 I11 (32) (17) O11 (30) (19) O12 (48) OE2 OE4 (24) (41) (8) O4 I12 I5 (40) (9) O5 I13 (29) (20) O13 I6 (38) (11) O6 I14 (27) (22) O14 I7 (37) (12) O7 I15 (26) (23) O15 I4 3 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E5 rad(Si) SEL Immune >108 MeV-cm2/mg SEU Onset Let N/A3 MeV-cm2/mg Neutron Fluence2 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Not tested, inherent of CMOS technology. 3. This device contains no memory storage elements which can be upset. ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER LIMIT (Mil only) UNITS VI/O Voltage any pin during operation -.3 to VDD +.3 V VDD Supply voltage -0.3 to 6.0 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 310 mW Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C tINRISE Maximize input rise or fall time (VIN transitioning betweenVIL (max) and VIH (min)) 20 ns tINFALL 4 DC ELECTRICAL CHARACTERISTICS 1 (-55C < TC < +125C) SYMBOL PARAMETER CONDITION MIN MAX UNIT 0.8 V VIL Low level input voltage2 VDD from 4.5 to 5.5V VIH High level input voltage2 VDD from 4.5 to 5.5V 2.0 IIN Input leakage current3 VDD from 4.5V to 5.5V -1 1 A -10 10 A -600 600 mA V V VIN = VDD or VSS IOZ Three-state output leakage current3 VDD from 4.5V to 5.5V VIN = VDD or VSS IOS Short-circuit output current 4, 5 VO = VDD or VSS VDD from 4.5V to 5.5V VOL1 Low-level output voltage3, 6 IOL= 24mA -55C, 25C 0.36 IOL= 24mA +125C 0.5 IOL= 100A -55C, 25C, 0.2 VDD = 4.5V to 5.5V +125C VIN = 0.8V to 2.0V VOL2 Low-level output voltage3, 6, 7 IOL= 50mA -55C, 25C 0.8 +125C 1.0 V VIN = 2.0V or 0.8V VDD = 5.5V VIN = 0.8V to 2.0V VOH1 High-level output voltage3, 6 IOH= -24mA -55C, 25C VDD - 0.64 IOH= -24mA +125C VDD - 0.8 IOH= -100A -55C, 25C, VDD - 0.2 VDD = 4.5V to 5.5V V +125C VIN = 0.8V to 2.0V VOH2 High-level output voltage3, 6, 7 IOH= -50mA -55C, 25C VDD - 1.1 V VIN = 2.0V or 0.8V VDD = 5.5V +125C VDD - 1.3 VIN = 0.8V to 2.0V VIC+ Positive input clamp voltage For input under test, IIN = 18mA 0.4 1.5 V -1.5 -0.4 V VDD = 0.0V VIC- Negative input clamp voltage For input under test, IIN =-18mA VDD = open 5 Ptotal CL = 20pF 1.0 mW/ MHz Pre-Rad -55 C to +125 C 10 160 A OEn = VDD Post-Rad 25oC OEn = VDD 160 Quiescent Supply Current Delta, For input under test VIN = VDD - 2.1V Power dissipation 8, 9, 10 VDD from 4.5V to 5.5V IDDQ Standby Supply Current VDD VIN = VDD or VSS VDD = 5.5V Pre-Rad 25oC o IDDQ OEn = VDD o TTL input level For other inputs 1.6 mA 15 pF 15 pF 1000 -1000 mV mV VOH +1000 VOH -1300 mV VIN = VDD or VSS VDD = 5.5V CIN Input capacitance 11 = 1MHz @ 0V VDD from 4.5V to 5.5V COUT Output capacitance11 = 1MHz @ 0V VDD from 4.5V to 5.5V VOLP Low level VSS bounce noise12 VOLV VOHP VOHV High level VDD bounce noise12 VIH = 3.0V, VIL = 0.0V, TA=+25oC, VDD = 5.0V See figure "Quiet Output Under Test" mV Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 3.Guaranteed; tested on a sample of pins per device. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Supplied as a design limit, but not guaranteed or tested. 6. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF-MHz. 7. Transmission driving tests are performed at VDD = 5.5V, only one output loaded at a time with a duration not to exceed 2ms. The test is guaranteed, if not tested, for VIN=VIH minimum or VIL maximum. 8. Guaranteed by characterization. 9. Power does not include power contribution of any CMOS output sink current. 10. Power dissipation specified per switching output. 11.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 12. This test is for qualification only. VSS and VDD bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture. 6 AC ELECTRICAL CHARACTERISTICS1 (VDD = 5V 10%; -55C < TC < +125C) SYMBOL PARAMETER MIN MAX UNIT tPLH Propagation delay In to On 2 8.0 ns tPHL Propagation delay In to On 2 8.0 ns tPZL Output enable time OEn to On 2 8.0 ns tPZH Output enable time OEn to On 2 8.0 ns tPLZ Output disable time OEn to On 2 9.5 ns tPHZ Output disable time OEn to On 2 9.5 ns tSKEW2 Output-to-output skew - 1.0 ns tDSKEW3 Differential skew between outputs 1.6 ns Part-to-Part output skew 500 ps tSKEWPP2,4 Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs low-to-high. 3. Differential skew is defined as a comparison of any two output transitions high-to-low vs. low-to-high and low-to-high vs high-to low. 4. Guaranteed by characterization, but not tested. 7 Propagation Delay 3.0V 1.5V 0V Input tPLH tPHL VOH VDD/2 VOL Output Enable Disable Times Control Input 5V Output Normally Low 5V Output Normally High tPZLn tPLZn .2VDD + .2V VDD/2-0.2 tPHZn tPZHn VDD/2+0.2 3.0V 1.5V 0V VDD/2 .2VDD .8VDD .8VDD - .2V VDD/2 Bounce Noise VOH Active Inputs VOL Quiet Outputs Under Test VOHP VOLP VOH VOL VOLV VOHV Test Load or Equivalent1 VDD VDD 100ohms 40pf 100ohms VSS Notes 1. Equivalent test circuit means that DUT performance will be correlated and remain guaranteed to the applicable test circuit, above, whenever a test platform change necessitates a deviation from the applicable test circuit. 8 PACKAGE NOTE: 1. Seal ring is connected to VSS. 2. Units are in inches. 3. All exposed metalized areas must be gold plated 100 to 225 microinches thick. Dyer electroplated nickel undercoating 100 to 350 microinches per MIL-PRF-38535. Figure 1. 48-Lead Flatpack 9 ORDERING INFORMATION UT54ACTQ16244: SMD 5962 R 06243 ** * * * Lead Finish: (NOTES 1 & 2) (A) = Hot solder dip (C) = Gold (X) = Factory option (gold or solder) Case Outline: (X) = 48 lead BB FP Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 16-bit Buffer/Line Driver (4.5V - 5.5V) Drawing Number: 06243 Total Dose: (NOTE 3) (R) = 1E5 rad(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3.Total dose radiation must be specified when ordering. QML Q not available without radiation hardeningTotal dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 10 UT54ACTQ16244 UT54 **** ***** * * * Lead Finish: (NOTES 1 & 2) (A) = Hot solder dip (C) = Gold (X) = Factory option (gold or solder) Screening: (NOTES 3 & 4) (C) = Mil Temp (P) = Prototype Package Type: (U) = 48-lead BB FP Part Number: (16244) = 16-bit Buffer Line Driver I/O Type: (ACTQ)= TTL compatible I/O Level with Quiet Outputs Aeroflex Core Part Number Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is Gold "C" only. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither tested nor guaranteed. 11 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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