Standard Products UT54ACS2S99S Dual, Sequential, ManyGate™ Configurable Logic Gate Product Brief June 2015 The most important thing we build is trust Features Introduction Voltage Supply: 3.0V to 5.5V Advanced CMOS technology Schmitt Trigger Inputs Tri-State Outputs ESD rating HBM: 2000V, Class 2 Operational environment: • Total dose: 1 Mrad(Si) • Latchup immune (LET <= 100 MeV-cm2/mg) Packaging: • 20-lead flatpack (dual line) Standard Microelectronics Drawing (SMD) • QML Q, V Pending The UT54ACS2S99S is Cobham Semiconductor Solutions’ (formerly Aeroflex) Dual, Sequential, ManyGate Configurable Logic Gate with Schmitt Trigger inputs and Tri-State outputs. The output-enable pin /OE1(2) is active LO. The logic state of the 4 inputs determines the output state when /OE1(2) is LO. When /OE1(2) is HI, the outputs are disabled. Setting /CLR1(2) to LO drives output Y1(2) LO. Setting /PRE1(2) to LO drives the output on Y1(2) HI. The combinatorial logic function for each block, as shown in Figure 1, is determined by the input logic configuration as per Tables 2-11. The D-Flip Flop D input is transferred to the Q output (Y1) on the positive-going CLK1 edge (1F99S). The D-Transparent Latch D input is latched at the Q output (Y2) when CLK2 is LO (1L99S). Configuring the respective combinatorial logic blocks as a non-inverting buffer provides either a single D-Flip flop (1F99S), or transparent latch (1L99S). Figure 1. UT54ACS2S99S Options Block Diagrams; Left: 1F99 D-Flip Flop Gate1; Right: 1L99 Transparent Latch Gate2 -1 - Cobham Semiconductor Solutions Aeroflex.com/Logic June 2015 1 Pin Definition/Description Pin Definition/Description Table 1. &/5 3, 13 /OEn Description 35( Active LOW output enable An A input &/. 6, 16 Bn B input $ Cn C input Dn D input 9, 19 nQ 3-State Output 1 /CLRn Clear active LOW 2 /PREn Preset active LOW & 4, 14 CLKn Clock 20 VDD Power supply pin 10 VSS Ground pin 11, 12 NC Electrically unconnected on package ' 4 966 % 8, 18 2( 5, 15 7, 17 2 Name 87$&666 Pin No. 9'' 4 ' & % $ &/. 2( 1& 1& Figure 2. UT54ACS2S99S Pinout Diagram Functional Truth Tables and Operational Modes Table 2. Combinatorial Truth Table An, Bn, Cn, Dn to input (DIN) of Storage Element Dn Cn Bn OUTPUT to DIN An L L L L L L L L H H L L H L L L L H H H L H L L L L H L H L L H H L H L H H H H H L L L H H L L H L H L H L H H L H H L H H L L H H H L H H H H H L L H H H H L -2- Cobham Semiconductor Solutions Aeroflex.com/Logic June 2015 Applications Info For 1F99 and 1L99 Options Table 3. Functional State Table for 1F99S D-Flip Flop Inputs 1. Output /OE1 /PRE /CLR CLK A1, B1, C1, D1 1Q L L H X X H L H L X X L L L L X X H1 L H H ↑ Per Table 2 DIN L H H L X Q0 H X X X X Z The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum. In addition, this configuration is non-stable; that is, it will not persist when either preset or clear returns to its inactive (high) level. Table 4. Functional State Table for 1L99S Transparent Latch Combination of Inputs 3 Output /OE2 CLK2 (A2, B2, C2, D2) 2Q L H Per Table 2 DIN L L X Q0 H X X Z Applications Info For 1F99 and 1L99 Options Table 5. Equivalent Logic Functions Created from Table 2 PRIMARY Logic FUNCTION COMPLEMENTARY Logic FUNCTION 3-state buffer 3-state inverter 3-state buffer 3-state inverter 3-state 2-in-1 data selector MUX 3-state 2-in-1 data selector MUX, inverted out 3-state 2-input AND 3-state 2-input NOR, both inputs inverted 3-state 2-input AND, one input inverted 3-state 2-input NOR, one input inverted 3-state 2-input AND, both inputs inverted 3-state 2-input NOR 3-state 2-input NAND 3-state 2-input OR, both inputs inverted 3-state 2-input NAND, one input inverted 3-state 2-input OR, one input inverted 3-state 2-input NAND, both inputs inverted 3-state 2-input OR -3- Cobham Semiconductor Solutions Aeroflex.com/Logic June 2015 Applications Info For 1F99 and 1L99 Options . Figure 3. 20-lead Ceramic Flatpack -4- Cobham Semiconductor Solutions Aeroflex.com/Logic June 2015 4 UT54ACS2S99S Synchronous Many Gate™ Logic Gate UT54ACS2S99S Synchronous Many Gate™ Logic Gate UT********* - * * * * Lead Finish: (NOTE 1 & 2) (A)= Hot Solder Dipped (C)= Gold (X)= Factory option (gold or solder) Screening Level: (NOTE 3) (C) = HiRel flow (-55°C to +125°C) (P) = Prototype flow (+25°C only) Case Outline: (U) = 20-lead Flatpack (dual-in-line) Access Time (-) Device Type: ACS2S99S NOTES 1. 2. 3. 4. Lead finish (A,C, or X) must be specified. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55°C, room temp, and +125°C. Radiation neither tested nor guaranteed. -5- Cobham Semiconductor Solutions Aeroflex.com/Logic June 2015 5 5962- UT54ACS2S99S Synchronous Many Gate™ Logic Gate: SMD UT54ACS2S99S Synchronous Many Gate™ Logic Gate: SMD XXXXX ** * * * Lead Finish: (NOTE 1) A = Solder C = Gold X = Optional Case Outline: (NOTE 2) (X) = 20-lead ceramic bottom-brazed dual-in-line Flatpack Screening Level: (Q) = QML Class Q (V) = QML Class V Device Type: (01) = Drawing Number: TBD Total Dose: R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) NOTES 1. 2. 3. Lead finish (A,C, or X) must be specified. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. -6- Cobham Semiconductor Solutions Aeroflex.com/Logic June 2015 UT54ACS2S99S Synchronous Many Gate™ Logic Gate: SMD This product is controlled for export under the U.S. Department of Commerce (DoC). A license may be required prior to the export of this product from the United States. Cobham Semiconductor Solutions 4350 Centennial Blvd Colorado Springs, CO 80907 E: [email protected] T: 800 645 8862 Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi – Rel Aeroflex Colorado Springs Inc., DBA Cobham Semiconductor Solutions, reserves the right to make changes to any products and services described herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. -7- Cobham Semiconductor Solutions Aeroflex.com/Logic