UT54ALVC2525 Clock Driver - Aeroflex Microelectronic Solutions

Standard Products
UT54ALVC2525 Clock Driver
1 to 8 Minimum Skew
Data Sheet
October 2012
INTRODUCTION
The UT54ALVC2525 is a low-voltage, minimum skew, oneto-eight clock driver. The UT54ALVC2525 distributes a single
clock to eight, high-drive, outputs with low skew across all
outputs during both the tPLH and tPHL transitions making it
ideal for signal generation and clock distribution. The output
pins act as a single entity and will follow the state of the CLK
pin.
FEATURES
2.0V to 3.6V Power supply operation
Guaranteed pin-to-pin and part-to-part skew
Eight LVTTL outputs with high drive strength
 Operational environment:
- Total-dose tolerance: 100 to 300 krad(Si), or
1 Mrad(Si)
- SEL Immune to a LET of 111 MeV-cm2/mg
HiRel temperature range: -55oC to +125oC
 Packaging options:
- 14-Lead Ceramic Flatpack
 Standard Microcircuit Drawing: 5962-06233
- QML Q and V
O0
O2
NC
GND
VDD
O4
O6
1
2
3
4
5
6
7
UT54ALVC2525
14
13
12
11
10
9
8
O1
O3
CLK
VDD
GND
O5
O7
00
Figure 2. 14-Lead Ceramic Flatpack Pinouts
CLK
07
Figure 1: UT54ALVC2525 Block Diagram
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PIN DESCRIPTION
Flatpack
Pin No.
Name
I/O
Type
12
CLK
I
LVTTL
3
1, 2, 6, 7, 8, 9,
13, 14
5, 11
N/C
--
--
On
O
LVTTL
Eight output clocks.
VDD
PWR
Power
Power supply for internal circuitry and output buffers.
4, 10
VSS
PWR
Power
Ground
Description
Primary reference clock input. This pin must be driven by an LVTTL or
LVCMOS clock source.
No connect.
OPERATIONAL ENVIRONMENT
The UT54ALVC2525 incorporates special design, layout, and process features which allows operation in a limited HiRel environment.
Parameter
Limit
Units
Total Ionizing Dose (TID)
>1E6
rads(Si)
Single Event Latchup (SEL) 1, 2
>111
MeV-cm2/mg
Onset Single Event Upset (SEU) LET (@2.0V)3, 5
52
MeV-cm2/mg
Onset Single Event Upset (SEU) LET (@3.0V)4, 5
66
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Dose Rate Upset
TBD
rads(Si)/sec
Dose Rate Survivability
TBD
rads(Si)/sec
Notes:
1. The UT54ALVC2525 is latchup immune to particle LETs >111 MeV-cm2/mg.
2. SEL temperature and voltage conditions of TC = +125oC, VDD = 3.6V.
3. SEU temperature and voltage conditions of TC = +25oC, VDD = 2.0V. Tested at 200MHz.
4. SEU temperature and voltage conditions of TC = +25oC, VDD = 3.0V. Tested at 200MHz.
5. For the UT54ALVC2525 SET performance at select operating frequency data ranges, please contact the factory.
2
ABSOLUTE MAXIMUM RATINGS:1
(Referenced to VSS)
Symbol
Description
Limits
Units
-0.3 to 4.0
V
VDD
Core Power Supply Voltage
VIN
Voltage Any Clock Input
-0.3 to VDD + 0.3
V
Voltage Any Clock Output
-0.3 to VDD + 0.3
V
+10
mA
1
W
-65 to +150
C
+150
C
20
C/W
>3000
V
VOUT
II
DC Input Current
PD
Maximum Power Dissipation
TSTG
TJ
JC
ESDHBM
Storage Temperature
Maximum Junction Temperature 2
Thermal Resistance, Junction to Case
ESD Protection (Human Body Model) - Class II
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life.
RECOMMENDED OPERATING CONDITIONS:
Symbol
Description
Limits
Units
VDD
Core Operating Voltage
2.0 to 3.6
V
VIN
Voltage Clock Input
0 to VDD
V
Voltage Any Clock Output
0 to VDD
V
-55 to +125
C
VOUT
TC
Case Operating Temperature
3
DC ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = 2.0V to 3.6V; TC = -55C to +125C)
Symbol
VDD
Min.
High level input voltage
2.0V
2.75V
3.0V
3.6V
1.25
1.5
1.75
2.0
Low level input voltage
2.0V
2.75V
3.0V
3.6V
0.7
0.8
0.8
0.8
V
Low level output voltage
IOL = 12mA
IOL = 12mA
IOL = 12mA
IOL = 12mA
2.0V
2.75V
3.0V
3.6V
0.45
0.4
0.4
0.4
V
VOH
High level output voltage
IOH = -12mA
IOH = -12mA
IOH = -12mA
IOH = -12mA
2.0V
2.75V
3.0V
3.6V
1.5
2.2
2.4
3.0
IOS2
Short-circuit output current
VOUT = VDD and VSS
2.0V
3.6V
-200
-300
200
300
mA
Input leakage current
VIN = VDD or VSS
3.6V
-1
1

Quiescent Supply Current
VIN = VDD or VSS
2.0V
1.0
1.0
mA
VIH1
VIL1
VOL
IIL
IDDQ
Description
Conditions
3.6V
PTOTAL3
CIN4
COUT4
Max.
Units
V
V
Total power dissipation
CL = 20pF
2.0V
2.75V
3.0V
3.6V
Input capacitance
f = 1MHz
0V
15
pF
Output capacitance
f = 1MHz
0V
15
pF
1.2
2.7
3.5
5.2
mW/MHz
Notes:
* Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. Functional tests are conducted in accordance with MIL-STD-883 with the following test conditions: VIH=VIH(min) +20%, -0% VIL=VIL(max)+0%, -50%, as
specified herein for the LVTTL and LVCMOS inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to
VIH(min), VIL (max).
2. Supplied as a design limit. Neither guaranteed nor tested.
3. When measuring the dynamic supply current, all outputs are loaded in accordance with the equivalent test load defined in figure 3.
4. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and the VSS at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
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AC ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = 2.0V to 3.6V; TC = -55C to +125C)
Symbol
Description
Condition
tR, tF3
Input rise/fall time
VIH (min) - VIL (max)
tPHL1,2
Propagation delay:
CLK to On,
high-to-low transition
Measured as transition time between
VIN = VDD÷2 to VOUT = VDD÷2
Propagation delay:
CLK to On,
low-to-high transition
Measured as transition time between
VIN = VDD÷2 to VOUT = VDD÷2
tOSHL
2,4,5
Maximum skew:
common edge,
output-to-output,
high-to-low transition
Measured as VOn = VDD ÷2 to VOm = VDD÷2
where n,m = 0 to 7; n not equal to m @ fCLK =
200MHz
tOSLH
2,4,5
Maximum skew:
common edge,
output-to-output,
low-to-high transition
VDD
Min.
3.6V
Max.
Unit
20
ns/V
2.0V
2.75V
3.0V
3.6V
3.5
3.0
2.75
2.25
7.5
5.5
5.25
4.75
ns
2.0V
2.75V
3.0V
3.6V
3.25
2.75
2.5
2.0
7.25
5.25
5.0
4.5
ns
2.0V
3.6V
0.15
0.25
ns
Measured as VOn= VDD ÷2 to VOm= VDD÷2
where n,m = 0 to 7; n not equal to m @ fCLK =
200MHz
2.0V
3.6V
0.15
0.25
ns
Output rise/fall time
Measured as transition time between
20% * VOL and 80% * VOH @ fCLK = 100MHz
2.0V
3.6V
2.4
2.0
ns
tPART4,5
Part-part skew
Skew between the same output of any two devices
under identical settings and conditions
(VDD, temp, air flow, frequency, etc).
2.0V
3.6V
0.1
0.15
ns
tPBAL1,4
Propagation delay balance:
difference between same output,
low-to-high and
high-to-low transitions
2.0V
2.75V
3.0V
3.6V
0.43
0.3
0.26
0.21
ns
tPLH1,2
tORISE &3
tOFALL
Measured as transition time between
VIN = VDD÷2 to VOUT = VDD÷2
Notes:
* Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. Test load = 40pF, terminated to VDD÷2. All outputs are equally loaded. Reference Figure 3 for clock output loading.
2. Reference Figure 4 for AC timing diagram.
3. Supplied only as a design guideline, neither tested nor guaranteed.
4. Guaranteed by characterization, but not tested.
5. Test load = 40pF, terminated to VDD÷2. All outputs are equally loaded. Reference Figure 5 for clock output loading.
5
VDD
VDD
Qn
150
100
DUT
150
100
CL
Figure 3.
Test Load Circuit for Dynamic Power Supply Current and AC Measurements
Note: This is not the recommended termination for normal user operation.
CLK
VDD /2
O0
VDD /2
O7
VDD /2
tPHL
tPLH
tOSHL
tOSLH
Figure 4. AC Timing Diagram
VDDQn
150
DUT
150
CL
Figure 5. Test Load Circuit for tOSHL and tOSLH Measurements
6
PACKAGING
1. All exposed metallized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MIL-PRF-38535.
4. Dimension symbol is in accordance with MIL-PRF-38533.
5. Lead position and colanarity are not measured.
6. ID mark symbol is vendor option.
Figure 6. 14-Pin Flatpack Package
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ORDERING INFORMATION
UT54ALVC2525:
UT54ALVC2525 - *
*
*
Lead Finish (Notes 1 & 2):
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening (Notes 3,4)
(C) = HiRel Temperature Range flow (-55C to +125C)
(P) = Prototype flow
Package Type:
(U) = 14-Lead Ceramic Flatpack
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed.
4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation
neither tested nor guaranteed.
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UT54ALVC2525: SMD
5962 * 06233
** * * *
Lead Finish (Notes 1 & 2):
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(X) = 14-Lead Ceramic Flatpack
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Type:
(01) = UT54ALVC2525 (Note 3)
(02) = UT54ALVC2525 (Note 4)
Drawing Number:
06233
Total Dose: (Note 5)
(-) = No Radiation Guarantee
(R) = 1E5 rads(Si)
(F) = 3E5 rads(Si)
(G) = 5E5 rads(Si)
(H) = 1E6 rads(Si)
Federal Stock Class Designator: No options
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold)
3.Available to a maximum RHA level of H.
4.Available to a maximum RHA level of R. Device is irradiated at a dose rate = 50-300 rads(Si)/s in accordance with MIL-STD-883, Method 1019, Condition A,
and is guaranteed to a maximum total dose specified. The effective dose rate after extended room temperature anneal = 1 rads(Si)/s per MIL-STD-883, Method
1019, Condition A, section 3.11.2. The total dose specification for these devices only applies to a low dose rate environment.
5.Total dose radiation must be specified when ordering. QML Q and QML V are not available without radiation hardening.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
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