Standard Products UT699E 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor Datasheet March 2015 www.aeroflex.com/LEON INTRODUCTION The UT699E is an enhanced version of the UT699 featuring a seven stage pipelined monolithic, high-performance, faulttolerant SPARCTM V8/LEON 3FT Processor. L1 cache has been increased to 16kB for both instruction and data caches. Performance is increased to 1.2 DMIPS / MHz. RMAP protocol is supported for all four SpaceWire ports. Other enhancements include cache snooping. The UT699E provides a 32-bit master/ target PCI interface, including a 16 bit user I/O interface for off-chip peripherals. A compliant 2.0 AMBA bus interface integrates the on-chip LEON 3FT, SpaceWire, Ethernet, memory controller, cPCI, CAN bus, and programmable interrupt peripherals. FEATURES Backward compatible with the UT699 Supports up to 100MHz clock rate Separate instruction and data cache architecture High-performance pipelined IEEE-754 FPU Enhanced pipeline with 1.2 DMIPS / MHz performance Implemented on 130nm CMOS technology Internally configured clock network Power saving 1.2V core power supply 3.3V I/O compatibility On-board programmable timers and interrupt controllers SEU hardened-by-design flip-flops and memory cells 10/100 Base-T Ethernet port for VxWorks development Integrated PCI 2.2 compatible core Four integrated multi-protocol SpaceWire nodes that support the RMAP protocol Two CAN 2.0 compliant bus interfaces Multifunctional memory controller The UT699E is SPARC V8 compliant; therefore, developers may use industry standard compilers, kernels, and development tools. A full software development suite is available including a C/C++ cross-compiler system based on GCC and the Newlib embedded C-library. Software developed for the UT699 will be 100% compatible with the UT699E. BCC includes a small run-time kernel with interrupt support and Pthreads library. For multi-threaded applications, a SPARCTM compliant port of the eCos real-time kernel, RTEMS 4.10, and VxWorks 6.x is supported. -55oC to +105oC temperature range Operational environment: - Intrinsic total-dose: 100 krad(Si) - SEL Immune ≤ 110 MeV-cm2/mg Packaging options: - 484-pin Ceramic Land Grid, Column Grid and Ball Grid Array packages Standard Microcircuit Drawing 5962-13237 - QML Q, Q+, and V (Pending) Applications - Nuclear power plant controls - Critical transportation systems - High-altitude avionics - Medical electronics - X-Ray cargo scanning - Spaceborne computer - System controller boards - Avionics processing boards 36-00-00-001 Ver. 1.5.0 1 Aeroflex Microelectronics Solutions - HiRel 1.0 Introduction The UT699E LEON 3FT processor is based upon the industry-standard SPARC V8 architecture. The system-on-chip incorporates the SPARC V8 core and the peripheral blocks indicated below. The core and peripherals communicate internally via the AMBA (Advanced Microcontroller Bus Architecture) interconnect. This bus is comprised of the AHB (Advanced High-speed Bus) which is used for high-speed data transfer, and the APB (Advanced Peripheral Bus) which is used for low-speed data transfer. IEEE754 FPU LEON 3FT Debug Support Unit MUL/DIV 4x4K D-cache MMU 4x4K I-cache Serial/JTAG Debug Link 4x SpW PCI Bridge CAN-2.0 AHB interface AMBA AHB AHB Ctrl AMBA APB AHB/APB Bridge Memory Controller UART Timers IrqCtrl I/O port Ethernet MAC 8/16/32-bits memory bus 512 MB PROM 256 MB I/O Up t o1GB SRAM Up to 1GB SDRAM Figure 1. UT699E Functional Block Diagram The LEON 3FT architecture includes the following peripheral blocks: • LEON3 SPARC V8 integer unit with 16kB instruction cache and 16kB of data cache • IEEE-754 floating point unit • Debug support unit • UART, JTAG, SpaceWire, and PCI debug links • 8/16/32-bit memory controller with EDAC for external PROM and SRAM • 32-bit SDRAM controller with EDAC for external SDRAM • Timer unit with three 32-bit timers and watchdog • Interrupt controller for 15 interrupts in two priority levels • 16-bit general purpose I/O port (GPIO) which can be used as external interrupt sources • Up to four SpaceWire links with RMAP on all channels • Up to two CAN controllers • Ethernet with support for MII • cPCI interface with 8-channel arbiter 36-00-00-001 Ver. 1.5.0 2 Aeroflex Microelectronics Solutions - HiRel 2.0 Pin Identification and Description Pin Function I IS O I/O OD PCI-I PCI-O PCI-I/O PCI-3 Description CMOS input CMOS input Schmitt CMOS output CMOS bi-direct CMOS open drain PCI input PCI output PCI bi-direct PCI three-state 2.1. System Signals Pin Name Function Pin Number Reset Value Description 484 CLGA SYSCLK I Y20 -- Main system clock RESET IS L19 -- System reset ERROR1 OD K19 -- Processor error mode indicator. This is an active low output. WDOG1 OD J19 -- Watchdog indicator. This is an active low output. Notes: 1. This pin is actively driven low and must be tied to VDD through a pull-up resistor. 2.2 Address Bus Pin Name Direction Pin Number Reset Value Description 484 CLGA ADDR[0] O W5 low Bit 0 of the address bus ADDR[1] O Y5 low Bit 1 of the address bus ADDR[2] O W6 low Bit 2 of the address bus ADDR[3] O AA5 low Bit 3 of the address bus ADDR[4] O Y6 low Bit 4 of the address bus ADDR[5] O AB5 low Bit 5 of the address bus ADDR[6] O W7 low Bit 6 of the address bus ADDR[7] O AA6 low Bit 7 of the address bus ADDR[8] O Y7 low Bit 8 of the address bus 36-00-00-001 Ver. 1.5.0 3 Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA ADDR[9] O AA7 low Bit 9 of the address bus ADDR[10] O AB6 low Bit 10 of the address bus ADDR[11] O W8 low Bit 11 of the address bus ADDR[12] O AB7 low Bit 12 of the address bus ADDR[13] O Y8 low Bit 13 of the address bus ADDR[14] O AA8 low Bit 14 of the address bus ADDR[15] O W9 low Bit 15 of the address bus ADDR[16] O AB8 low Bit 16 of the address bus ADDR[17] O Y9 low Bit 17 of the address bus ADDR[18] O W10 low Bit 18 of the address bus ADDR[19] O AB9 low Bit 19 of the address bus ADDR[20] O Y10 low Bit 20 of the address bus ADDR[21] O AA9 low Bit 21 of the address bus ADDR[22] O W11 low Bit 22 of the address bus ADDR[23] O AA10 low Bit 23 of the address bus ADDR[24] O Y11 low Bit 24 of the address bus ADDR[25] O AB10 low Bit 25 of the address bus ADDR[26] O AB11 low Bit 26 of the address bus ADDR[27] O AA11 low Bit 27 of the address bus 2.3 Data Bus Pin Name Direction Pin Number Reset Value Description 484 CLGA DATA[0] I/O W12 high-z Bit 0 of the data bus DATA[1] I/O W13 high-z Bit 1 of the data bus DATA[2] I/O Y12 high-z Bit 2 of the data bus DATA[3] I/O AA13 high-z Bit 3 of the data bus DATA[4] I/O AA12 high-z Bit 4 of the data bus 36-00-00-001 Ver. 1.5.0 4 Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA DATA[5] I/O AB13 high-z Bit 5 of the data bus DATA[6] I/O W14 high-z Bit 6 of the data bus DATA[7] I/O AA14 high-z Bit 7 of the data bus DATA[8] I/O Y13 high-z Bit 8 of the data bus DATA[9] I/O W15 high-z Bit 9 of the data bus DATA[10] I/O AB15 high-z Bit 10 of the data bus DATA[11] I/O Y14 high-z Bit 11 of the data bus DATA[12] I/O AB14 high-z Bit 12 of the data bus DATA[13] I/O W16 high-z Bit 13 of the data bus DATA[14] I/O AA18 high-z Bit 14 of the data bus DATA[15] I/O Y15 high-z Bit 15 of the data bus DATA[16] I/O AB16 high-z Bit 16 of the data bus DATA[17] I/O AA15 high-z Bit 17 of the data bus DATA[18] I/O AB17 high-z Bit 18 of the data bus DATA[19] I/O AA16 high-z Bit 19 of the data bus DATA[20] I/O AA19 high-z Bit 20 of the data bus DATA[21] I/O W17 high-z Bit 21 of the data bus DATA[22] I/O AB18 high-z Bit 22 of the data bus DATA[23] I/O Y16 high-z Bit 23 of the data bus DATA[24] I/O Y17 high-z Bit 24 of the data bus DATA[25] I/O AA17 high-z Bit 25 of the data bus DATA[26] I/O W18 high-z Bit 26 of the data bus DATA[27] I/O AB19 high-z Bit 27 of the data bus DATA[28] I/O Y19 high-z Bit 28 of the data bus DATA[29] I/O AB20 high-z Bit 29 of the data bus DATA[30] I/O Y18 high-z Bit 30 of the data bus DATA[31] I/O AA20 high-z Bit 31 of the data bus 36-00-00-001 Ver. 1.5.0 5 Aeroflex Microelectronics Solutions - HiRel 2.4 Check Bits Pin Name Direction Pin Number Reset Value Description 484 CLGA CB[0] I/O V19 high-z Bit 0 of EDAC checkbits CB[1] I/O AA21 high-z Bit 1 of EDAC checkbits CB[2] I/O Y21 high-z Bit 2 of EDAC checkbits CB[3] I/O W19 high-z Bit 3 of EDAC checkbits CB[4] I/O Y22 high-z Bit 4 of EDAC checkbits CB[5] I/O W20 high-z Bit 5 of EDAC checkbits CB[6] I/O W22 high-z Bit 6 of EDAC checkbits CB[7] I/O W21 high-z Bit 7 of EDAC checkbits 2.5 Memory Control Signals Pin Name Direction Pin Number Reset Value Description 484 CLGA WRITE O V21 high PROM and I/O write enable strobe OE O U19 high PROM and I/O output enable IOS O T20 high I/O area chip select ROMS[0] O V22 high PROM chip select ROMS[1] O U20 high PROM chip select RWE[0] O U22 high SRAM write enable strobe RWE[1] O T19 high SRAM write enable strobe RWE[2] O T22 high SRAM write enable strobe RWE[3] O T21 high SRAM write enable strobe RAMOE[0] O V20 high SRAM output enable RAMOE[1] O R21 high SRAM output enable RAMOE[2] O R20 high SRAM output enable RAMOE[3] O R22 high SRAM output enable RAMOE[4] O R19 high SRAM output enable RAMS[0] O P22 high SRAM chip select 36-00-00-001 Ver. 1.5.0 6 Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA RAMS[1] O P20 high SRAM chip select RAMS[2] O P21 high SRAM chip select RAMS[3] O P19 high SRAM chip select RAMS[4] O N19 high SRAM chip select READ O K20 high SRAM, PROM, and I/O read indicator BEXC I K22 -- Bus exception BRDY I K21 -- Bus ready 2.6 SDRAM Pin Name Direction Pin Number Reset Value Description 484 CLGA SDCLK O AB12 high SDRAM clock SDRAS O N22 high SDRAM row address strobe SDCAS O N20 high SDRAM column address strobe SDWE O N21 high SDRAM write enable SDCS[0] O M21 high SDRAM chip select SDCS[1] O M22 high SDRAM chip select SDDQM[0] O L21 high SDRAM data mask SDDQM[1] O M20 high SDRAM data mask SDDQM[2] O L20 high SDRAM data mask SDDQM[3] O L22 high SDRAM data mask 2.7 CAN 2.0 Interface Pin Name Direction Pin Number Reset Value Description 484 CLGA CAN_RXD[0] I J20 -- CAN receive data CAN_TXD[0] O J22 high CAN transmit data 36-00-00-001 Ver. 1.5.0 7 Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA CAN_RXD[1] I J21 -- CAN receive data CAN_TXD[1] O H22 high CAN transmit data 2.8 Debug Support Unit (DSU) Pin Name Direction Pin Number Reset Value Description 484 CLGA DSUACT O H19 low DSUmode indicator DSUBRE I H20 -- DSU break DSUEN I G19 -- DSU enable DSURX I G20 -- DSU UART receive data DSUTX O G21 high DSU UART transmit data 2.9 JTAG Interface Pin Name Direction Pin Number Reset Value Description 484 CLGA TRST I F20 -- JTAG reset TMS I F21 -- JTAG test mode select TCK I G22 -- JTAG clock TDI I F22 -- JTAG test data input TDO O F19 -- JTAG test data output 2.10 Ethernet Interface Pin Name Direction Pin Number Reset Value Description 484 CLGA EMDC O E22 low ERX_CLK I D22 -- 36-00-00-001 Ver. 1.5.0 8 Ethernet media interface clock Ethernet RX clock Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA EMDIO I/O D20 high-z Ethernet media interface data ERX_COL I E21 -- Ethernet collision error ERX_CRS I E20 -- Ethernet carrier sense detect ERX_DV I D21 -- Ethernet receiver data valid ERX_ER I C21 -- Ethernet reception error ERXD[0] I C22 -- Ethernet receive data ERXD[1] I B21 -- Ethernet receive data ERXD[2] I C20 -- Ethernet receive data ERXD[3] I B20 -- Ethernet receive data ETXD[0] O C19 low Ethernet transmit data ETXD[1] O C18 high Ethernet transmit data ETXD[2] O B18 low Ethernet transmit data ETXD[3] O B19 high Ethernet transmit data ETX_CLK I A19 -- ETX_EN O A18 low Ethernet transmit enable ETX_ER O A20 low Ethernet transmit error. Always driven low. Ethernet TX clock 2.11 General Purpose I/O Pin Name Direction Pin Number Reset Value Description 484 CLGA GPIO[0] I/O B17 high-z Bit 0 of general purpose I/O GPIO[1] I/O C17 high-z Bit 1 of general purpose I/O GPIO[2] I/O A17 high-z Bit 2 of general purpose I/O GPIO[3] I/O D17 high-z Bit 3 of general purpose I/O GPIO[4] I/O C16 high-z Bit 4 of general purpose I/O GPIO[5] I/O D16 high-z Bit 5 of general purpose I/O GPIO[6] I/O C15 high-z Bit 6 of general purpose I/O GPIO[7] I/O D15 high-z Bit 7 of general purpose I/O 36-00-00-001 Ver. 1.5.0 9 Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA GPIO[8] I/O C7 high-z Bit 8 of general purpose I/O GPIO[9] I/O B5 high-z Bit 9 of general purpose I/O GPIO[10] I/O D7 high-z Bit 10 of general purpose I/O GPIO[11] I/O A5 high-z Bit 11 of general purpose I/O GPIO[12] I/O D6 high-z Bit 12 of general purpose I/O GPIO[13] I/O C5 high-z Bit 13 of general purpose I/O GPIO[14] I/O C6 high-z Bit 14 of general purpose I/O GPIO[15] I/O D5 high-z Bit 15 of general purpose I/O 2.12 SpaceWire Interface Pin Name Direction Pin Number Reset Value Description 484 CLGA SPW_CLK I A11 -- SpaceWire clock SPW_RXS[0] I A16 -- SpaceWire receive strobe SPW_RXD[0] I A15 -- SpaceWire receive data SPW_TXS[0] O B16 low SpaceWire transmit strobe SPW_TXD[0] O B15 low SpaceWire transmit data SPW_RXS[1] I A14 -- SpaceWire receive strobe SPW_RXD[1] I A13 -- SpaceWire receive data SPW_TXS[1] O B14 low SpaceWire transmit strobe SPW_TXD[1] O B13 low SpaceWire transmit data SPW_RXS[2] I A9 -- SpaceWire receive strobe SPW_RXD[2] I A8 -- SpaceWire receive data SPW_TXS[2] O B9 low SpaceWire transmit strobe SPW_TXD[2] O B8 low SpaceWire transmit data SPW_RXS[3] I A7 -- SpaceWire receive strobe SPW_RXD[3] I A6 -- SpaceWire receive data SPW_TXS[3] O B7 low 36-00-00-001 Ver. 1.5.0 10 SpaceWire transmit strobe Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA SPW_TXD[3] O B6 low SpaceWire transmit data 2.13 UART Interface Pin Name Direction Pin Number Reset Value Description 484 CLGA RXD I C12 -- UART receive data TXD O C11 high UART transmit data 2.14 PCI Address and Data Bus Pin Name Direction Pin Number Reset Value Description 484 CLGA PCI_AD[0] PCI-I/O AA2 high-z Bit 0 of PCI address and data bus PCI_AD[1] PCI-I/O AA3 high-z Bit 1 of PCI address and data bus PCI_AD[2] PCI-I/O Y1 high-z Bit 2 of PCI address and data bus PCI_AD[3] PCI-I/O Y2 high-z Bit 3 of PCI address and data bus PCI_AD[4] PCI-I/O Y3 high-z Bit 4 of PCI address and data bus PCI_AD[5] PCI-I/O W1 high-z Bit 5 of PCI address and data bus PCI_AD[6] PCI-I/O W2 high-z Bit 6 of PCI address and data bus PCI_AD[7] PCI-I/O W3 high-z Bit 7 of PCI address and data bus PCI_AD[8] PCI-I/O V2 high-z Bit 8 of PCI address and data bus PCI_AD[9] PCI-I/O V3 high-z Bit 9 of PCI address and data bus PCI_AD[10] PCI-I/O U1 high-z Bit 10 of PCI address and data bus PCI_AD[11] PCI-I/O U2 high-z Bit 11 of PCI address and data bus PCI_AD[12] PCI-I/O U3 high-z Bit 12 of PCI address and data bus PCI_AD[13] PCI-I/O T1 high-z Bit 13 of PCI address and data bus PCI_AD[14] PCI-I/O R2 high-z Bit 14 of PCI address and data bus PCI_AD[15] PCI-I/O R1 high-z Bit 15 of PCI address and data bus 36-00-00-001 Ver. 1.5.0 11 Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA PCI_AD[16] PCI-I/O J1 high-z Bit 16 of PCI address and data bus PCI_AD[17] PCI-I/O K2 high-z Bit 17 of PCI address and data bus PCI_AD[18] PCI-I/O K1 high-z Bit 18 of PCI address and data bus PCI_AD[19] PCI-I/O G1 high-z Bit 19 of PCI address and data bus PCI_AD[20] PCI-I/O H3 high-z Bit 20 of PCI address and data bus PCI_AD[21] PCI-I/O H2 high-z Bit 21 of PCI address and data bus PCI_AD[22] PCI-I/O F1 high-z Bit 22 of PCI address and data bus PCI_AD[23] PCI-I/O F2 high-z Bit 23 of PCI address and data bus PCI_AD[24] PCI-I/O E1 high-z Bit 24 of PCI address and data bus PCI_AD[25] PCI-I/O E2 high-z Bit 25 of PCI address and data bus PCI_AD[26] PCI-I/O F3 high-z Bit 26 of PCI address and data bus PCI_AD[27] PCI-I/O D1 high-z Bit 27 of PCI address and data bus PCI_AD[28] PCI-I/O D2 high-z Bit 28 of PCI address and data bus PCI_AD[29] PCI-I/O E3 high-z Bit 29 of PCI address and data bus PCI_AD[30] PCI-I/O D3 high-z Bit 30 of PCI address and data bus PCI_AD[31] PCI-I/O C1 high-z Bit 31 of PCI address and data bus 2.15 PCI Control Signals Pin Name Direction Pin Number Reset Value Description 484 CLGA PCI_RST PCI-I C3 -- PCI reset input PCI_CLK PCI-I C2 -- PCI clock input PCI_C/BE[0] PCI-I/O V1 high-z PCI bus command and byte enable PCI_C/BE[1] PCI-I/O P2 high-z PCI bus command and byte enable PCI_C/BE[2] PCI-I/O H1 high-z PCI bus command and byte enable PCI_C/BE[3] PCI-I/O G2 high-z PCI bus command and byte enable PCI_PAR PCI-I/O P1 high-z PCI parity checkbit PCI_FRAME1 PCI-3 L1 high-z PCI cycle frame indicator 36-00-00-001 Ver. 1.5.0 12 Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA PCI_IRDY1 PCI-3 L2 high-z PCI initiator ready indicator PCI_TRDY1 PCI-3 M1 high-z PCI target ready indicator PCI_STOP1 PCI-3 N1 high-z PCI target stop request PCI_DEVSEL1 PCI-3 M2 high-z PCI device select PCI_PERR1 PCI-3 N2 high-z PCI parity error indicator PCI_IDSEL PCI-I G3 -- PCI_REQ PCI-O A4 high-z PCI request to arbiter in point to point configuration PCI_GNT PCI-I B2 -- PCI bus access indicator in point to point configuration PCI_HOST PCI-I AB3 -- PCI host enable input (Connect to SYSEN in PCI bus) PCI initialization device select Notes: 1. This pin must be tied to VDD through a pull-up resistor as specified in the PCI Local Bus Specification Revision 2.1 Section 4.3.3. 2.16 PCI Arbiter Pin Name Direction Pin Number Reset Value Description 484 CLGA PCI_ARB_REQ[0] PCI-I B4 -- PCI arbiter bus request PCI_ARB_REQ[1] PCI-I AB4 -- PCI arbiter bus request PCI_ARB_REQ[2] PCI-I Y4 -- PCI arbiter bus request PCI_ARB_REQ[3] PCI-I T3 -- PCI arbiter bus request PCI_ARB_REQ[4] PCI-I P3 -- PCI arbiter bus request PCI_ARB_REQ[5] PCI-I M3 -- PCI arbiter bus request PCI_ARB_REQ[6] PCI-I K3 -- PCI arbiter bus request PCI_ARB_REQ[7] PCI-I C4 -- PCI arbiter bus request PCI_ARB_GNT[0] PCI-O B3 high-z PCI arbiter bus grant PCI_ARB_GNT[1] PCI-O AA4 high-z PCI arbiter bus grant PCI_ARB_GNT[2] PCI-O W4 high-z PCI arbiter bus grant PCI_ARB_GNT[3] PCI-O R3 high-z PCI arbiter bus grant 36-00-00-001 Ver. 1.5.0 13 Aeroflex Microelectronics Solutions - HiRel Pin Name Direction Pin Number Reset Value Description 484 CLGA PCI_ARB_GNT[4] PCI-O N3 high-z PCI arbiter bus grant PCI_ARB_GNT[5] PCI-O L3 high-z PCI arbiter bus grant PCI_ARB_GNT[6] PCI-O J3 high-z PCI arbiter bus grant PCI_ARB_GNT[7] PCI-O A3 high-z PCI arbiter bus grant 2.17 Power and Ground Pins Pin Number Pin Name Description 484 CLGA VDD B1, B10, B12, B22, E7, E9, E14, E16, F6, F10, F13, F17, G5, G9, G14, H6, H8, H10, H13, H15, J7, J16, J18, K5, K8, K15, K17, L6, M6, N5, N8, N15, N17, P7, P16, P18, R6, R8, R10, R13, R15, T5, T9, T14, U6, U9, U11, U12, U14, U17, V10, V13, AA1, AA22 I/O supply voltage VSS A1, A12, A22, B11, C8, C10, C13, D4, D9, D14, D18, E4, E6, E10, E13, E17, E19, F4, G4, G8, G11, G12, G15, G17, H4, H7, H16, H18, J2, J4, J9, J14, K4, K10, K13, L7, L11, L12, L17, M7, M11, M12, M17, N4, N10, N13, P4, P9, P14, R4, R7, R16, R18, T2, T4, T8, T15, T17, U4, U10, U13, V4, V5, V8, V11, V12, V15, V18, AB1, AB22 I/O supply ground VDDC A2, A21, D10, D13, E5, E11, E12, E18, F8, F15, G7, G10, G13, G16, G18, H5, H9, H11, H12, H14, H17, J6, J8, J15, K7, K16, L4, L8, L15, L18, M4, M8, M15, M18, N7, N16, P6, P8, P15, R5, R9, R11, R12, R14, R17, T7, T10, T13, T16, T18, U8, U15, V6, V17, AB2, AB21 Core supply voltage VSSC A10, C9, C14, D11, D12, E8, E15, F5, F7, F9, F11, F12, F14, F16, F18, G6, H21, J5, J10, J11, J12, J13, J17, K6, K9, K11, K12, K14, K18, L5, L9, L10, L13, L14, L16, M5, M9, M10, M13, M14, M16, M19, N6, N9, N11, N12, N14, N18, P5, P10, P11, P12, P13, P17, T6, T11, T12, U5, U7, U16, U18, U21, V7, V9, V14, V16 Core supply ground Unused D8 This pin may be left floating or tied to VSS Unused D19 This pin must be tied to VSS 36-00-00-001 Ver. 1.5.0 14 Aeroflex Microelectronics Solutions - HiRel 2.20 Bootstrap Signals The states of the following signals are latched in upon the rising edge of reset in order to configure the UT699E for the indicated operation. Pin Name GPIO[1:0] GPIO[2] GPIO[7:4] GPIO[15:12] 36-00-00-001 Ver. 1.5.0 Function Sets the data width of the PROM area 00: 8 bits 01: 16 bits 10: 32 bits 11: Not used Enable EDAC checking of the PROM area 0: EDAC disabled 1: EDAC enabled Set the SpW clock divisor link bits in the SpW Clock Divisor Register Sets the least significant address nibble of the IP and MAC address for the Ethernet Debug Communication Link (EDCL) 15 Aeroflex Microelectronics Solutions - HiRel 3.0 AC and DC Electrical Specifications 3.1 Absolute Maximum Ratings1 Symbol Description Min Max Units VDDC Core supply voltage -0.3 1.85 V VDD I/O supply voltage -0.3 5.2 V VIN Input voltage any pin VSS - 0.3 VDD + 0.3 V PD2 Maximum power dissipation permitted @ TC = 105oC -- 4 W Junction temperature -- 150 -- 5 -65 150 2000 -- TJ ΘJC Thermal resistance, junction to case TSTG Storage temperature ESDHBM 484 CLGA/CCGA/CBGA ESD protection (human body model) Class 2 o o C C/W o C V Notes: 1. Stresses greater than those listed in the following table can result in permanent damage to the device. These parameters cannot be violated. 2. Per MIL-STD-883, Method 1012, Section 3.4.1, PD = (TJ(max)-Tc(max))/ΘJC 36-00-00-001 Ver. 1.5.0 16 Aeroflex Microelectronics Solutions - HiRel 3.2 Recommended Operating Conditions (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Min Max Units VDDC Core supply voltage 1.1 1.3 V VDD I/O supply voltage 3.0 3.6 V VIN Input voltage any pin 0 VDD V TC Case operating temperature -55 105 o tR Rise time, all CMOS and PCI inputs (0.1VDD to 0.9VDD) -- 20 ns tF Fall time, all CMOS and PCI inputs (0.9VDD to 0.1VDD) -- 20 ns C 3.3 Operational Environmet The UT699E processor includes the following SEU mitigation features: * Cache memory error-detection of up to 4 errors per tag or 32-bit word * Autonomous and software transparent error handling * No timing impact due to error detection or correction PARAMETER LIMIT UNITS Total Ionizing Dose (TID) 1 1E5 rad (Si) Single Event Latchup Immune (SEL) 2 <110 MeV-cm2/mg Single Event Upset (SEU) 3, 4 Inherent register upset rate 5.2E-7 errors/device-day Single Event Upset (SEU) 3, 4 Multiple-bit error (MBE) rate which overcomes internal error detection & correction architecture 2.8E-11 MBE/device-day Notes: 1. TID irradation per MIL-STD-883, Test Method 1019, condition A. Post irradiation electrical testing performed at room temperature. 2. Worst case temperature and voltage of TC = +105oC, VDD = 3.6V, VDDC = 1.3V. 3. Contact factory for error rate information. 4. The error rate calculation was performed using SpaceRad 6.0 for a Geosynchronous orbit in the Adams 90% worst-case environment with 100mil Al shielding. 36-00-00-001 Ver. 1.5.0 17 Aeroflex Microelectronics Solutions - HiRel 3.4 Power Supply Operating Characteristics (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description IDDCS Standby core power supply quiescent current Conditions VDDC = 1.3V, VDD= 3.6V All clock inputs at 0MHz TC = -55oC Standby I/O power supply quiescent current Units 8 o and 25 C Post Irradiation (R) IDDS Max VDDC = 1.3V, VDD = 3.6V All clock inputs at 0MHz TC = 105oC 100 TC = 25oC 50 TC = -55oC 0.7 and 25oC TC = 105oC mA mA 2 3.5 DC Characteristics for LVCMOS3 Inputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Conditions Min Max Units VIH1 High-level input voltage 0.7VDD -- V VIL1 Low-level input voltage -- 0.3VDD V VT+ Positive going threshold voltage for Schmitt inputs -- 0.7VDD V VT- Negative going threshold voltage for Schmitt inputs 0.3VDD -- V VH Hysteresis voltage for Schmitt inputs 0.4 -- V IIN Input leakage current VIN = VDD -- 1 μA VIN = VSS -1 -- f = 1MHz; VDD = 0V, VDDC = 0V -- 16 CIN2 Input pin capacitance pF Notes: 1. JTAG inputs are not tested. 2. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance. 36-00-00-001 Ver. 1.5.0 18 Aeroflex Microelectronics Solutions - HiRel 3.6 DC Characteristics for LVCMOS3 Outputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description VOL11 Low-level output voltage (All outputs except those listed below and in Section 3.8) VOH11,2 VOL2 VOH2 VOL3 VOH3 IOZ IOS3 COUT4 Min Max Units IOL = 100μA -- 0.25 V IOL = 4mA -- 0.4 VDD-0.25 -- IOH = -4mA 2.4 -- IOL = 100μA -- 0.25 IOL = 12mA -- 0.4 IOH = -100μA VDD-0.25 -- IOH = -12mA 2.4 -- Low-level output voltage (WRITE, OE, IOS, ROMS[1:0], RWE [3:0], RAMOE [4:0], RAMS[4:0], SDCS[1:0], SDRAS, SDCAS, SDWE, SDCLK, READ, SDDQM[3:0], ADDR[27:0], DATA[31:0] and CB[7:0]) IOL = 100μA -- 0.25 IOL = 24mA -- 0.4 High-level output voltage (WRITE, OE, IOS, ROMS[1:0], RWE [3:0], RAMOE [4:0], RAMS[4:0], SDCS[1:0], SDRAS, SDCAS, SDWE, SDCLK, READ, SDDQM[3:0], ADDR[27:0], DATA[31:0] and CB[7:0]) IOH = -100μA VDD-0.25 -- IOH = -24mA 2.4 -- VO = VDD -10 10 VO = VSS -10 10 VO = VDD; VDD = 3.6V -- 130 VO = VSS; VDD = 3.6V -65 -- -- 16 High-level output voltage (All outputs except those listed below and in Section 3.8) Low-level output voltage (GPIO[15:0], SPW_TXD[3:0], SPW_TXS[3:0], TXD) High-level output voltage (GPIO[15:0], SPW_TXD[3:0], SPW_TXS[3:0], TXD) Three-state output current Short-circuit output current (All outputs except PCI outputs) Output pin capacitance Conditions IOH = -100μA f = 1MHz; VDD = 0V, VDDC = 0V V V V V V μA mA pF Notes: 1. JTAG outputs are not tested. 2. Except open-drain output. 3. Guaranteed by design. 4. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance. 36-00-00-001 Ver. 1.5.0 19 Aeroflex Microelectronics Solutions - HiRel 3.7 AC Electrical Characteristics for LVCMOS3 Inputs and Outputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Conditions Min Max Units fCLK System clock frequency -- 100 MHz tHIGH System clock high time 4 -- ns tLOW System clock low time 4 -- ns tDSD1 System clock to SDRAM clock propagation delay 2.0 6.0 ns Notes: 1. Reference Figure 15 for test load. 1/fCLK tHIGH tLOW tDSD tDSD SYSCLK SDCLK Figure 2. System Clock and SDCLK Timing Diagram 36-00-00-001 Ver. 1.5.0 20 Aeroflex Microelectronics Solutions - HiRel 3.8 DC Electrical Characteristics for PCI Inputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Conditions Min Max Units VIH High-level input voltage 0.5VDD -- V VIL Low-level input voltage -- 0.3VDD V IIN Input leakage current VIN = VDD -- 10 μA VIN = VSS -10 -- -- 22 pF Min Max Units CIN1 Input pin capacitance f = 1MHz; VDD = 0V, VDDC = 0V Notes: 1. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance. 3.9 DC Electrical Characteristics for PCI Outputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Conditions VOH High-level output voltage (PCI_AD[31:0], PCI_C/BE[3:0], PCI_RST, PCI_IDSEL, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR) IOH = -500μA 0.9VDD -- V VOL Low-level output voltage (PCI_AD[31:0], PCI_C/BE[3:0], PCI_RST, PCI_IDSEL, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR) IOL = 1500μA -- 0.1VDD V IOZ Three-state output current VO = VDD -10 10 μA VO = VSS -10 10 VO = VDD; VDD = 3.6V -- 270 VO = VSS; VDD = 3.6V -130 -- -- 22 IOS1 COUT2 Short-circuit output current Output pin capacitance f = 1MHz; VDD = 0V, VDDC = 0V mA pF Notes: 1. Guaranteed by design. 2. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance. 36-00-00-001 Ver. 1.5.0 21 Aeroflex Microelectronics Solutions - HiRel 3.10 AC Electrical Characteristics for PCI Inputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Conditions Min Max Units fPCI_CLK PCI clock frequency -- 33 MHz tHIGH PCI clock high time 11 -- ns tLOW PCI clock low time 11 -- ns 1/fPCI_CLK tHIGH tLOW PCI_CLK Figure 3. PCI Clock Timing Diagram 36-00-00-001 Ver. 1.5.0 22 Aeroflex Microelectronics Solutions - HiRel 4.0 Timing Specifications 4.1 Power Sequencing and Reset (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Conditions Min Max Units tVCD1 VDD valid to VDDC delay VDD > 3.0V; VDDC > 1.1V 0 -- ns tVHBZ1 VDD valid to control signals high-z (WRITE, OE, IOS, ROMS[1:0], RWE[3:0], RAMOE [4:0], READ SDWE, and SDCS[1:0]) VDD > 1.5V; VDDC = 0V -- 4 tCLK VDD valid to outputs high-z ([DATA[31:0], CB[7:0], and GPIO[15:0]) tCHBV1 VDDC valid to control signals valid-inactive (WRITE, OE, IOS, ROMS[1:0], RWE[3:0], RAMOE [4:0], READ SDWE, and SDCS[1:0]) VDD > 3.0V; VDDC > 1.1V -- 4 tCLK tRESET11 VDDC valid to RESET deassert VDDC > 1.1V 4 -- tCLK tRESET21 RESET deasserted to outputs valid-active (ROMS[0] and OE) -- 12 tCLK tRESET31 RESET asserted to control signals validinactive (WRITE, OE, IOS, ROMS[1:0], RWE[3:0], RAMOE [4:0], READ SDWE, and SDCS[1:0]) -- 4 tCLK RESET asserted to outputs high-z (DATA[31:0], CB[7:0], and GPIO[15:0]) Notes: 1. Guaranteed by design. 36-00-00-001 Ver. 1.5.0 23 Aeroflex Microelectronics Solutions - HiRel SYSCLK VDD 3.3V 0V tVCD VDDC 1.2V 0V tRESET1 RESET tCHBV tVHBZ Memory Bus Control Signals tRESET2 VALID-INACTIVE tRESET3 VALID-ACTIVE tVHBZ VALID-INACTIVE tRESET3 Tri-State Outputs VALID-ACTIVE Figure 4. Power Sequencing and Reset Timing Diagram 4.1.1. Power Sequencing For optimal power sequencing, both power-up and power-down, ramp both VDD and VDDC together. During power-up, if VDDC > VDD + 0.3V, excessive current or damage may occur to the device. During power down, it is acceptable for VDD to be less than VDDC by more than 0.3V as long as VDDC is not actively driven. 4.1.2 Bus Control and Bi-Direct Fail-Safe Circuitry In order to prevent bus contention on the external memory interface while VDDC is ramping up, the UT699E has functionality to ensure that the bi-direct and memory bus control signals described in Section 4.1 will be in a high-z state tVHBZ delay after VDD reaches 1.5V. The core logic will put these signals into their valid-inactive states tCHBV clock cycles after VDDC reaches 1.1V. Aeroflex recommends that users place pull-up resistors on the indicated output enable, write enable, and chip select pins, and a pulldown resistor on the READ pin, if tVCD is greater than 100ns. This will prevent bus capacitance or transients from inadvertently placing these pins in an active state, which could result in external memory devices driving the address and data buses. 4.1.3 Reset Circuitry The reset circuitry is controlled by the core logic; therefore, the circuitry is functional only after VDDC reaches its minimum operating voltage of 1.1V. After VDDC is stable, the system must continue to assert RESET for a minimum of tRESET1 clock cycles before it can be de-asserted. Asserting RESET for less time could result in the RESET signal not being recognized. The UT699E will begin fetching code from external memory no more than tRESET2 clock cycles after RESET is de-asserted. Control signals ROMS[0] and OE will be driven to their valid-active states in order for the UT699E to begin fetching code from PROM. During normal operation, the indicated bus control signals will go to a valid-inactive state, and the bi-directs will go to a high-z state, within tRESET3 clock cycles after the assertion of RESET. 36-00-00-001 Ver. 1.5.0 24 Aeroflex Microelectronics Solutions - HiRel 4.1.4 Boot Strap Programming on GPIO Data on pins GPIO[2:0], GAPIO[7:4] and GPIO[15:12] are latched on the rising edge of reset. The states of GPIO[2:0] determine the data width of the PROM area, and enable EDAC for the PROM area. Chapter 3 of the User’s Manual describes the value of these inputs to achieve the required operation. The states of GPIO[7:4] provides a means to configure the SpaceWire clock divisor link bits in the Clock Divisor Register. The states of GPIO[15:12] set the least significant address nibble of the IP and MAC address for the Ethernet Debug Communication Link (EDCL). In order for the state of GPIO[2:0] to be properly latched, Aeroflex recommends placing pull-up or pull-down resistors on these pins to ensure that the setup and hold timing is met. The states of these pins should be statically set prior to the rising edge of RESET. 36-00-00-001 Ver. 1.5.0 25 Aeroflex Microelectronics Solutions - HiRel 4.2 Output Timing Characteristics for Memory Interface, ERROR, and WDOG (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Min Max Units 1.5 8.5 ns t1a1 SDCLK↑ to ADDR[27:0] valid t1b1 SDCLK↑ to SDCS[1:0] valid 2 7.5 ns t1c1 SDCLK↑ to output valid SDRAS, SDCAS, and SDWE 1.5 8.5 ns t1d1 SDCLK↑ to SDDQM[3:0] valid 2.5 8.5 ns t1e1 SDCLK↑ to output valid (WRITE, OE, IOS, ROMS[1:0], RWE [3:0], RAMOE [4:0], RAMS[4:0], and READ) 1 8 ns t21,2 SDCLK↑ to output valid (DATA[31:0] and CB[7:0]) 2.5 8.5 ns t31,2,3 SDCLK↑ to output high-Z (DATA[31:0] and CB[7:0]) 2.5 8.5 ns SDCLK↑ to signal low (ERROR and WDOG) -- 10 ns WRITE↑ or RWE[3:0]↑ to output high-z (DATA [31:0] and CB[7:0]) 0.5 -- ns Skew from first memory output signal transition to last memory output signal transition -- 2 ns t41,4 t81,2,3 t91 Notes: 1. All outputs are measured using the load conditions shown in Figure 15. 2. CB[7] is not tested. 3. High-Z defined as +/-300mV change from steady state. 4. WDOG guaranteed by design. 36-00-00-001 Ver. 1.5.0 26 Aeroflex Microelectronics Solutions - HiRel SDCLK t1a t9 ADDR[27:0] t1b SDCS t1c SDRAS, SDCAS, and SDWE t1d SDDQM[3:0] WRITE and RWE[3:0] t8 t2 t3 DATA[31:0] and CB[7:0] t4 ERROR and WDOG t1e All Other Outputs Figure 5. Memory Interface, ERROR, and WDOG Output Timing Diagram 36-00-00-001 Ver. 1.5.0 27 Aeroflex Microelectronics Solutions - HiRel 4.3 Input Timing Characteristics for Memory Interface (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description t5a1,2 t5b Min Max Units Setup time to SDCLK↑ (DATA[31:0] and CB[7:0]) 1 -- ns Setup time to SDCLK↑ (BEXC, and synchronous BRDY) 2 -- ns 1.5 -- ns 0 -- ns 1.5 -- tCLK Hold time from SDCLK↑ (DATA[31:0] and CB[7:0]) t6a1,2 t6b Hold time from SDCLK↑ (Synchronous BRDY) t73 Asynchronous BRDY pulse width Notes: 1. CB[7] is not tested. 2. CB[6:0] timing is guaranteed by design when used as inputs. 3. Supplied as a design limit. Neither guaranteed nor tested. SDCLK t6a t5a DATA[31:0] and CB[7:0] t6b t5b BEXC and Synchronous BRDY t7 Asynchronous BRDY Figure 6. Memory Interface Input Timing Diagram 36-00-00-001 Ver. 1.5.0 28 Aeroflex Microelectronics Solutions - HiRel 4.4 Timing Characteristics for General Purpose Input / Output (GPIO) (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description SDCLK↑ to GPIO output valid (GPIO[15:0]) t101 Min Max Units -- 10 ns Notes: 1. All outputs are measured using the load conditions shown in Figure 15. SDCLK t10 GPIO[15:0] Figure 7. General Purpose I/O Timing Diagram 36-00-00-001 Ver. 1.5.0 29 Aeroflex Microelectronics Solutions - HiRel 4.5 Timing Characteristics SpaceWire Interface (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description SPW_CLK period t111,2 Transmit data and strobe bit width variation (SPW_TXD[3:0] and SPW_TXS[3:0]) t143,4,5 Min Max Units 5 -- ns UI-600 UI+600 ps t155,6 Receive data and strobe bit width (SPW_RXD[3:0] and SPW_RXS[3:0]) 5 -- ns t165 Receive data and strobe edge separation (SPW_RXD[3:0] and SPW_RXS[3:0]) 1/2*t11 + 0.5 -- ns Notes: 1. The SPW_CLK frequency must be less than or equal to 10x the SYSCLK frequency. For example, if SPW_CLK is running at 200MHz, the SYSCLK frequency must be greater than or equal to 20MHz. 2. Functionally tested. 3. Applies to both high pulse and low pulse. 4. A unit interval (UI) is defined as the nominal, or ideal, bit width. 5. Guaranteed by design. 6. The SPW_CLK period must be less than or equal to the minimum receive data/strobe bit width. t11 SPW_CLK t14 SPW_TXD t14 SPW_TXS Figure 8. SpaceWire Transmit Timing Diagram t15 SPW_RXD t16 t16 t15 SPW_RXS Figure 9. SpaceWire Receive Timing Diagram 36-00-00-001 Ver. 1.5.0 30 Aeroflex Microelectronics Solutions - HiRel 4.6 Timing Characteristics for PCI Interface (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Description Min Max Units t171 PCI_CLK↑ to output valid (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, PCI_PERR, PCI_REQ, and PCI_ARB_GNT[7:0]) 2 13 ns t181,2 PCI_CLK↑ to output valid from high-z (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, and PCI_PERR 2 13 ns t191,2 PCI_CLK↑ to output high-Z (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, and PCI_PERR -- 14 ns t203 Setup time to PCI_CLK↑ (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, PCI_PERR, PCI_IDSEL, PCI_GNT, and PCI_ARB_REQ[7:0]) 4 -- ns t213 Hold time from PCI_CLK↑ (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, PCI_PERR, PCI_IDSEL, PCI_GNT, and PCI_ARB_REQ[7:0]) 1 -- ns t224 PCI_CLK↑ to RESET deassertion 10 -- PCI Clocks t23a4 PCI_CLK↑ to PCI_RST deassertion 10 -- PCI Clocks t23b4 PCI_RST assertion to PCI_CLK idle 10 PCI_RST active to output high-Z -- t24 PCI Clocks 40 ns Notes: 1. All outputs are measured using the load conditions shown in Figure 15. 2. High-Z defined as +/-300mV change from steady state. 3. PCI_TRDY, PCI_STOP, and PCI_DEVSEL timing is guaranteed by design when used as inputs. 4. Guaranteed by design. 36-00-00-001 Ver. 1.5.0 31 Aeroflex Microelectronics Solutions - HiRel PCI_CLK t17 All Outputs t18 t19 Bi-Direct and Tri-State Outputs t21 t20 All Inputs Figure 10. PCI Timing Diagram SYSCLK PCI_CLK t23a t23b PCI_RST t22 RESET t24 Bi-Direct and Tri-State Outputs Figure 11. Timing Relationships of Clock and Reset for PCI Core Utilization SYSCLK PCI_CLK t22 RESET PCI_RST Figure 12. Timing Relationships of Clock and Reset for Unused PCI Core 36-00-00-001 Ver. 1.5.0 32 Aeroflex Microelectronics Solutions - HiRel 4.7 Timing Characteristics for Ethernet Interface (VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55oC to 105oC) Symbol Min Max Units ETX_CLK↑ to output valid (ETXD[3:0], and ETX_EN) -- 12 ns t262,3 Setup time to ERX_CLK↑ (ERX_DV, ERX_ER, and ERXD[3:0]) 1 -- ns t272,3 Hold time from ERX_CLK↑ (ERX_DV, ERX_ER, and ERXD[3:0]) 1 -- ns t251 Description Conditions t281 EMDC↑ to output valid (EMDIO) -4+tAMBA4 4+tAMBA4 ns t295 Setup time to EMDC↑ (EMDIO) 10 -- ns t305 Hold time from EMDC↑ (EMDIO) 10 -- ns Notes: 1. All outputs are measured using the load conditions shown in Figure 17. 2. ERX_ER timing is guaranteed by design. 3. ERX_COL and ERX_CRS are asynchronous inputs and are not tested. 4. tAMBA is defined as tSYSCLK. 5. Guaranteed by design. ETX_CLK t25 All Outputs ERX_CLK t26 t27 All Inputs Figure 13. Ethernet Transmit and Receive Timing EMDC t28 EMDIO (Output) t29 t30 EMDIO (Input) Figure 14. Ethernet MDIO Interface Timing 36-00-00-001 Ver. 1.5.0 33 Aeroflex Microelectronics Solutions - HiRel 4.8 Test Conditions for Timing Specifications VDD VDD 100 100 CL Figure 15. Equivalent Load Circuit for Timing Characteristics Tests CL = 50 pF for ATE test load CL =15 pF for benchtop test load 36-00-00-001 Ver. 1.5.0 34 Aeroflex Microelectronics Solutions - HiRel 5.0 Packaging Figure 16. 484-lead Ceramic Land Grid Array 36-00-00-001 Ver. 1.5.0 35 Aeroflex Microelectronics Solutions - HiRel Figure 17. 484-lead Ceramic Column Grid Array 36-00-00-001 Ver. 1.5.0 36 Aeroflex Microelectronics Solutions - HiRel Figure 18. 484-lead Ceramic Ball Grid Array 36-00-00-001 Ver. 1.5.0 37 Aeroflex Microelectronics Solutions - HiRel 7.0 Ordering Information UT699E LEON 3FT UT699E - * * * Lead Finish: (NOTE 1) (C) = Gold (A) = Solder Screening Level: (NOTE 2 & 3) (P) = Prototype (Temperature Range: 25oC only) (E) = HiRel (Temperature Range: -55oC to +105oC) Case Outline: (Z) = 484-Ceramic Land Grid Array (S) = 484-Ceramic Column Grid Array (C) = 484-Ceramic Ball Grid Array (High Temp Solder Balls) UT699E 32-bit LEON 3FT Notes: 1. Lead finish (A or C) must be specified. 2. Prototype Flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25oC only. Radiation is neither tested nor guaranteed. 3. HiRel Flow per Aeroflex Manufacturing Flows Document. Radiation is neither tested nor guaranteed. 36-00-00-001 Ver. 1.5.0 Package Option Associated Lead Finish (Z) 484-CLGA (C) Gold (S) 484-CCGA (A) Solder (C) 484-CBGA (A) Solder 38 Aeroflex Microelectronics Solutions - HiRel UT699E LEON 3FT: SMD 5962 * 13237 ** * * * Lead Finish: (NOTE: 1) (C) = Gold (F) = Solder Case Outline: (X) = 484-Ceramic Land Grid Array Package (Y) = 484-Ceramic Column Grid Array Screening Level: (Q) = QML Class Q (V) = QML Class V Device Type: (01) = UT699E (Temperature range: -55oC to +105oC) (02) = UT699E Assembled to Aeroflex’s Q+ Flow (Temp range: -55oC to +105oC) Drawing Number: 13237 Total Dose: (R) = 1E5 rad(Si) Federal Stock Class Number: No Options Notes: 1. Lead finish is “C” (gold) only for case outlines "X". Lead finish is "F" (solder) only for case outline "Y". 36-00-00-001 Ver. 1.5.0 Package Option Associated Lead Finish (X) 484-CLGA (C) Gold (Y) 484-CCGA (F) Solder 39 Aeroflex Microelectronics Solutions - HiRel Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel This product is controlled for export under the Export Administration Regulations (EAR). A license from the U.S. Government is required prior to the export of this product from the United States. www.aeroflex.com [email protected] Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services described herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 40 DATA SHEET REVISION HISTORY Revision Date Description of Change 11/13 1.0.0 Release of Preliminary Data Sheet 2/14/14 1.1.0 Replaced package drawings 3/12/14 1.2.0 Replaced BGA package drawing 6/16/14 1.2.1 Reordered SMD Case Outlines 9/10/2014 1.3.0 Release of Production Datasheet Page 1: Corrected SEL Immune Page 2: Corrected Block Diagram, Cache information Page 16: Corrected note 3 temperature Page 17: Moved Operational Environment table from section 5 (deleted) to 3.3 and updated Page 18: Finalized IDDCS, IDDS limits Page 20: Added IIN and IIN limits (to bound the range for pull up/down resistors) Page 21: Corrected tDSD limits Page 22: Corrected IIN and IOZ limits Page 31: Corrected symbols t14, t15, t16, and the corresponding timing diagrams] 11/21/14 1.4.0 Page 15: Added GPIO[2] entry to Bootstrap signals table. Page 25: Re-wrote section 4.1.4 Page 39:Corrected SMD lead finish designator. Page All: Added Footer March 2015 Page 16: Removed note 3 and changed the maximum junction temperature value from 125°C to 150°C in the Ver. 1.5.0 Absolute Maximum Ratings Table. Page 24: Rewrote section 4.1.1 on power sequencing. 36-00-00-001 Ver. 1.5.0 41 Aeroflex Microelectronics Solutions - HiRel