DATASHEET

DATASHEET
1.25V Radiation Hardened Ultra Low Noise, Precision
Voltage Reference
ISL71090SEH12
Features
The ISL71090SEH12 is an ultra low noise, high DC accuracy
precision voltage reference with a wide input voltage range
from 4V to 30V. The ISL71090SEH12 uses the Intersil
advanced bipolar technology to achieve 1µVP-P noise at 0.1Hz
with an accuracy over temperature of 0.15% and an accuracy
over radiation of 0.15%.
• Reference output voltage . . . . . . . . . . . . . . . . . 1.25V ±0.05%
• Accuracy over temperature . . . . . . . . . . . . . . . . . . . . ±0.15%
• Accuracy over radiation . . . . . . . . . . . . . . . . . . . . . . . . ±0.15%
• Output voltage noise . . . . . . . . . . 1µVP-P typ (0.1Hz to 10Hz)
• Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930µA (typ)
The ISL71090SEH12 offers a 1.25V output voltage with
10ppm/°C temperature coefficient and also provides
excellent line and load regulation. The device is offered in an
8 Ld flatpack package.
• Tempco (box method) . . . . . . . . . . . . . . . . . . . 10ppm/°C max
The ISL71090SEH12 is ideal for high-end instrumentation,
data acquisition and applications requiring high DC precision
where low noise performance is critical.
• Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ppm/mA
Applications
• RH voltage regulators precision outputs
• Precision voltage sources for data acquisition system for
space applications
• Strain and pressure gauge for space applications
• Output current capability . . . . . . . . . . . . . . . . . . . . . . . . 20mA
• Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8ppm/V
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• Radiation environment
- High dose rate (50 to 300rad(Si)/s) . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 100krad(Si)*
- SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . 86MeV•cm2/mg
*Product capability established by initial characterization. The
“EH” version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate
• Electrically screened to SMD 5962-13211
Related Literature
• AN1847, “ISL71090SEH12, ISL71090SEH25,
ISL71090SEH50, ISL71090SEH75 User’s Guide”
• AN1848, “Single Event Effects (SEE) Testing of the
ISL71090SEH Precision Voltage Reference”
• AN1849, “Total Dose Testing of the ISL71090SEH Precision”
ISL71090SEH12
2
VIN
0.1µF
3
1nF
4
DNC
DNC
VIN
DNC
COMP
VOUT
GND
TRIM
8
1.2530
7
VREF
UNIT5
5
VDD
VDD
VEE
VEE
BIPOFF
NOTE: Select C to minimize
settling time.
UNIT2
1.2505
1.1k
1.2500
-60
GND
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
HS-565BRH
1
1.2515
UNIT4
D12
FIGURE 1. ISL71090SEH12 TYPICAL APPLICATION DIAGRAM
March 18, 2016
FN8452.4
UNIT1
1.2510
DACOUT
D0
1.2520
0.1µF
C
REFIN
UNIT3
1.2525
6
VOUT (V)
1
FIGURE 2. VOUT vs TEMPERATURE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013, 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL71090SEH12
Ordering Information
ORDERING
NUMBER
(Notes 1, 2)
PART
NUMBER
VOUT OPTION
(V)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
5962R1321101VXC
ISL71090SEHVF12
1.25
-55 to +125
8 Ld Flatpack
K8.A
ISL71090SEHF12/PROTO
ISL71090SEHF12/PROTO
1.25
-55 to +125
8 Ld Flatpack
K8.A
5962R1321101V9A
ISL71090SEHVX12
1.25
-55 to +125
Die
ISL71090SEHX12SAMPLE
ISL71090SEHX12SAMPLE
1.25
-55 to +125
Die
ISL71090SEH12EV1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART
NUMBER
VOUT
(V)
TEMPCO
(ppm/°C)
OUTPUT VOLTAGE NOISE
(µVP-P)
LOAD REGULATION
(ppm/mA)
ISL71090SEH12
1.25
10
1
35
ISL71090SEH25
2.5
10
2
2.5
ISL71090SEH50
5.0
10
1.1
10
ISL71090SEH75
7.5
10
1
10
Submit Document Feedback
2
FN8452.4
March 18, 2016
ISL71090SEH12
Pin Configuration
ISL71090SEH12
(8 LD FLATPACK)
TOP VIEW
DNC
1
8
DNC
VIN
2
7
DNC
COMP
3
6
VOUT
GND
4
5
TRIM
NOTE: The ESD triangular mark is indicative of pin #1. It is a part of the device marking and is
placed on the lid in the quadrant where pin #1 is located.
Pin Descriptions
PIN NUMBER
PIN NAME
ESD CIRCUIT
DESCRIPTION
1, 7, 8
DNC
3
Do not connect. Internally terminated.
2
VIN
1
Input voltage connection.
3
COMP
2
Compensation and noise reduction capacitor.
4
GND
1
Ground connection. Also connected to the lid.
5
TRIM
2
Voltage reference trim input.
6
VOUT
2
Voltage reference output.
VDD
VDD
CAPACITIVELY
TRIGGERED CLAMP
VDD
PIN
DNC
GND
GND
ESD CIRCUIT 1
Submit Document Feedback
3
ESD CIRCUIT 2
ESD CIRCUIT 3
FN8452.4
March 18, 2016
ISL71090SEH12
Functional Block Diagram
VIN
BIAS
REGULATOR
DNC
3.7V
DNC
DNC
1.2V
+
Gm
-
+
VOUT
-
GND
COMP
TRIM
1.2V
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
Typical Trim Application Diagram
ISL71090SEH12
1
VIN
2
0.1µF
3
1nF
4
8
DNC
DNC
VIN
DNC
COMP
GND
VOUT
TRIM
7
VREF
6
5
100kΩ
0.1µF
1MΩ
FIGURE 4. TYPICAL TRIM APPLICATION DIAGRAM
Submit Document Feedback
4
FN8452.4
March 18, 2016
ISL71090SEH12
Absolute Maximum Ratings
Thermal Information
Maximum Voltage
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +40V
VIN to GND at an LET = 86MeV•cm2/mg . . . . . . . . . . . . . . -0.5V to +36V
VOUT to GND (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VOUT + 0.5V
Voltage on any Pin to Ground . . . . . . . . . . . . . . . . . -0.5V to +VOUT + 0.5V
Voltage on DNC Pins . . . . . . . . . . . . No connections permitted to these pins
ESD Ratings
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . 750V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld Flatpack Package (Notes 3, 4). . . . . .
140
15
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C
Recommended Operating Conditions
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V to +30V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the "case temp" location is the center of the ceramic on the package underside.
5. Product capability established by initial characterization. The "EH" version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate.
6. The output capacitance used for SEE testing is CIN = 0.1µF and COUT = 1µF.
Electrical Specifications for Flatpack VIN = 5V, IOUT = 0mA, CL = 0.1µF and CC = 1nF unless otherwise specified. Boldface limits
apply after radiation at +25°C and across the operating temperature range, -55°C to +125°C without radiation, unless otherwise specified.
PARAMETER
DESCRIPTION
VOUT
Output Voltage
VOA
VOUT Accuracy at TA = +25°C
TC VOUT
TEST CONDITIONS
UNIT
V
VOUT = 1.252V, (Note 9)
-0.05
+0.05
%
-0.15
+0.15
%
VOUT Accuracy at TA = +25°C, Post
Radiation
-0.15
+0.15
%
10
ppm/°C
VOUT = 1.252V, (Note 9)
Output Voltage Temperature
Coefficient (Note 8)
Input Voltage Range
Supply Current
VOUT /VIN
Line Regulation
VOUT/IOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 20mA
Dropout Voltage (Note 10)
IOUT = 10mA
ISC+
Short-Circuit Current
TA = +25°C, VOUT tied to GND
ISC-
Short-Circuit Current
tR
Turn-On Settling Time
Ripple Rejection
eN
VN
VOUT/t
MAX
(Note 7)
VOUT Accuracy at TA = -55°C to +125°C VOUT = 1.252V, (Note 9)
IIN
PSRR
TYP
1.252
VIN
VD
MIN
(Note 7)
4
VIN = 4V to 30V
30
V
0.930
1.280
mA
8
18
ppm/V
35
55
ppm/mA
1.70
2.25
V
53
mA
TA = +25°C, VOUT tied to VIN
-23
mA
90% of final value, CL = 1.0µF,
CC = open
250
µs
f = 120Hz
90
dB
Output Voltage Noise
0.1Hz ≤ f ≤10Hz
1.0
µVP-P
Broadband Voltage Noise
10Hz ≤ f ≤1kHz
1.2
µVRMS
Noise Density
f = 1kHz, VIN = 6V
21
nV/Hz
Long Term Drift
TA = +125°C, 1000hrs
15
ppm
Submit Document Feedback
5
FN8452.4
March 18, 2016
ISL71090SEH12
Electrical Specifications for Die VIN = 5V, IOUT = 0, CL = 0.1µF and CC = 0.01µF unless otherwise specified. Boldface limits apply
after radiation at +25°C and across the operating temperature range, -55°C to +125°C without radiation, unless otherwise specified. Specifications over
temperature are guaranteed but not production tested on die.
PARAMETER
DESCRIPTION
VOUT
Output Voltage
VOA
VOUT Accuracy at TA = +25°C
TC VOUT
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
1.252
UNIT
V
VOUT = 1.252V (Note 11)
-0.05
+0.05
%
VOUT Accuracy at TA = -55°C to +125°C VOUT = 1.252V (Note 11)
-0.15
+0.15
%
VOUT Accuracy at TA = +25°C, Post
Radiation
-0.15
+0.15
%
10
ppm/°C
30
V
0.930
1.280
mA
VOUT = 1.252V (Note 11)
Output Voltage Temperature
Coefficient (Note 8)
VIN
Input Voltage Range
IIN
Supply Current
VOUT /VIN
Line Regulation
VIN = 4V to 30V
8
18
ppm/V
VOUT/IOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 20mA
35
55
ppm/mA
Dropout Voltage (Note 10)
IOUT = 10mA
1.70
2.25
V
VD
4
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT(max) - VOUT(min) is divided
by the temperature range; in this case, -55°C to +125°C = +180°C.
9. Post-reflow drift for the ISL71090SEH12 devices can be 100µV typical based on experimental results with devices on FR4 double sided boards. The
engineer must take this into account when considering the reference voltage after assembly.
10. Dropout Voltage is the minimum VIN - VOUT differential voltage measured at the point where VOUT drops 1mV from VIN = nominal at TA = +25°C.
11. The VOUT accuracy is based on die mount with Silver Glass die attach material such as "QMI 2569" or equivalent in a package with an Alumina
ceramic substrate.
Submit Document Feedback
6
FN8452.4
March 18, 2016
ISL71090SEH12
Typical Performance Curves
VIN = 5V, VOUT = 1.252V, TA = +25°C, COUT = 0.1µF, COMP = 1nF unless otherwise
specified.
20
4
LOAD REGULATION (ppm/mA)
LINE REGULATION (ppm/V)
LINE REG ppm/V +125°C
3
2
LINE REG ppm/V +25°C
1
0
LINE REG ppm/V -55°C
-1
-2
10
0
LOAD REG ppm/mA (VIN = 5V -55°C)
-10
-20
LOAD REG ppm/mA (VIN = 5V +25°C)
-30
-40
LOAD REG ppm/mA (VIN = 5V +125°C)
-50
0
5
10
15
20
25
30
35
0
2
4
VIN (V)
6
8
10
12
14
16
18
20
IOUT (mA)
FIGURE 5. LINE REGULATION OVER-TEMPERATURE (0mA)
FIGURE 6. LOAD REGULATION OVER-TEMPERATURE AT VIN = 5V
(ppm/mA)
1.2520
1.2515
VOUT (V) -10mA +25°C
VOUT (V) -10mA -55°C
VOUT (V)
1.2510
VOUT (V) 0mA +25°C
1.2505
VOUT (V) 0mA -55°C
VOUT (V) 20mA -55°C
1.2500
VOUT (V) 20mA +25°C
VOUT (V) -10mA +125°C
1.2495
VOUT (V) 0mA +125°C
1.2490
VOUT (V) 20mA +125°C
1.2485
0
5
10
15
20
25
30
35
VIN (V)
FIGURE 7. VOUT vs VIN AT 0mA, 20mA AND -10mA
3.0
40
DROPOUT V AT +150°C
30
2.5
20
VOUT (mV)
DROPOUT (V)
2.0
1.5
DROPOUT V AT +25°C
DROPOUT V AT +125°C
1.0
+25°C VIN = 5V, VOUT = 1.252V, IOUT = 0mA TO 1mA,
COMP = 1nF, COUT = 1µF, V/DIV = 20mV/DIV,
SLEW RATE: 2mA/µs
10
0
-10
-20
0.5
-30
0
0
0.005
0.010
0.015
0.020
IOUT (mA)
FIGURE 8. DROPOUT VOLTAGE FOR 1.25V
Submit Document Feedback
7
0.025
-40
-200
0
200
400
600
800
TIME (µs)
FIGURE 9. LOAD TRANSIENT (0mA TO 1mA)
FN8452.4
March 18, 2016
ISL71090SEH12
Typical Performance Curves
VIN = 5V, VOUT = 1.252V, TA = +25°C, COUT = 0.1µF, COMP = 1nF unless otherwise
specified. (Continued)
1.2530
VOUT 200mV/DIV
UNIT3
1.2525
UNIT5
VOUT (V)
1.2520
VIN 10V/DIV
UNIT1
1.2515
UNIT2
1.2510
UNIT4
1.2505
1.2500
-60
-40
-20
50µs/DIV
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 10. TURN-ON SETTLING TIME
FIGURE 11. TYPICAL TEMPERATURE COEFFICIENT PLOT FOR 5 UNITS
0
1.E-05
-20
1.E-06
PSRR (dB)
NOISE (V/√Hz)
-40
1.E-07
-60
-80
1.E-08
-100
1.E-09
0.1
f = 1kHz, En = 21.02nV/√Hz
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 12. NOISE DENSITY vs FREQUENCY (VIN = 6.0V, IOUT = 0mA,
CIN = 0.1µF, COUT = 1µF, COMP = 1nF)
Submit Document Feedback
8
-120
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 13. PSRR (+25°C, VIN = 5V, VOUT = 1.252V, IOUT = 0mA,
CIN = 0.1µF, COUT = 1µF, COMP = 1nF, VSIG = 300mVP-P)
FN8452.4
March 18, 2016
ISL71090SEH12
Device Operation
Bandgap Precision Reference
The ISL71090SEH12 uses a bandgap architecture and special
trimming circuitry to produce a temperature compensated,
precision voltage reference with high input voltage capability and
moderate output current drive.
Applications Information
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting
location should be reviewed. The device uses a ceramic flatpack
package. Generally, mild stresses to the die when the Printed
Circuit (PC) board is heated and cooled, can slightly change the
shape. Because of these die stresses, placing the device in areas
subject to slight twisting can cause degradation of reference
voltage accuracy. It is normally best to place the device near the
edge of a board, or on the shortest side, because the axis of
bending is most limited in that location. Mounting the device in a
cutout also minimizes flex. Obviously, mounting the device on
flexprint or extremely thin PC material will likewise cause loss of
reference accuracy.
Board Assembly Considerations
Some PC board assembly precautions are necessary. Normal
output voltage shifts of typically 100µV can be expected with
Pb-free reflow profiles or wave solder on multilayer FR4 PC
boards. Precautions should be taken to avoid excessive heat or
extended exposure to high reflow or wave solder temperatures.
Output Voltage Adjustment
The output voltage can be adjusted above and below the
factory-calibrated value via the trim terminal. The trim terminal is
the negative feedback divider point of the output op amp. The
voltage at the trim pin is set at approximately 1.216V by the
internal bandgap and amplifier circuitry of the voltage reference.
The suggested method to adjust the output is to connect a 1MΩ
external resistor directly to the trim terminal and connect the
other end to the wiper of a potentiometer that has a 100kΩ
resistance and whose outer terminals connect to VOUT and
ground. If a 1MΩ resistor is connected to trim, the output adjust
range will be ±6.3mV. The TRIM pin should not have any
capacitor tied to its output, also it is important to minimize the
capacitance on the trim terminal during layout to preserve output
amplifier stability. It is also best to connect the series resistor
directly to the trim terminal, to minimize that capacitance and
also to minimize noise injection. Small trim adjustments will not
disturb the factory-set temperature coefficient of the reference,
but trimming near the extreme values can.
Output Stage
The output stage of the device has a push-pull configuration with
a high-side PNP and a low-side NPN. This helps the device to act
as a source and sink. The device can source 20mA.
Use of COMP Capacitor
The reference can be compensated for the COUT capacitors used
by adding a capacitor from COMP pin to GND. See Table 2 for
recommended values of the COMP capacitor.
TABLE 2. RECOMMENDED VALUES OF COMP CAPACITOR
Noise Performance and Reduction
The output noise voltage over the 0.1Hz to 10Hz bandwidth is
typically 1µVP-P. The noise measurement is made with a 9.9Hz
bandpass filter. Noise in the 10Hz to 1kHz bandwidth is
approximately 1.6µVRMS, with 0.1µF capacitance on the output.
This noise measurement is made with a bandpass filter of
990Hz. Load capacitance up to 10µF (with COMP capacitor from
Table 2) can be added but will result in only marginal
improvements in output noise and transient response.
Turn-On Time
Normal turn-on time is typically 250µs, the circuit designer must
take this into account when looking at power-up delays or
sequencing.
Temperature Coefficient
The limits stated for Temperature Coefficient (Tempco) are
governed by the method of measurement. The overwhelming
standard for specifying the temperature drift of a reference is to
measure the reference voltage at two temperatures, which
provide for the maximum voltage deviation and take the total
variation, (VHIGH - VLOW), this is then divided by the temperature
extremes of measurement (THIGH – TLOW). The result is divided by
the nominal reference voltage (at T = +25°C) and multiplied by
106 to yield ppm/°C. This is the “Box” method for specifying
temperature coefficient.
Submit Document Feedback
9
COUT
(µF)
CCOMP
(nF)
0.1
1
1
10
10
30
SEE Testing
The device was tested under ion beam at an LET of
86MeV•cm2/mg. The device did not latch up or burn out to a VDD
of 36V and at +125°C. Single Event transients were observed
and are summarized in Table 3:
TABLE 3. OBSERVATION OF SINGLE EVENT TRANSIENTS
VIN
(V)
IOUT
(mA)
COUT
(µF)
SET
(% VOUT)
4
5
1
-4.6
30
5
1
-4.4
30
5
10
-1.0
DNC Pins
These pins are for trimming purpose and for factory use only. Do
not connect these to the circuit in any way. It will adversely effect
the performance of the reference.
FN8452.4
March 18, 2016
ISL71090SEH12
Package Characteristics
Top Metallization
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
Weight of Packaged Device
0. 31 Grams (Typical)
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Connected to lead #4 (GND)
Case Isolation to Any Lead: 20 x 109 Ω (min)
ASSEMBLY RELATED INFORMATION
SUBSTRATE POTENTIAL
Floating
Die Characteristics
ADDITIONAL INFORMATION
Die Dimensions
WORST CASE CURRENT DENSITY
1464µm x 1744µm (58 mils x 69 mils)
Thickness: 483µm ± 25µm (19 mils ± 1 mil)
<2 x 105 A/cm2
Interface Materials
PROCESS
Dielectrically Isolated Advanced Bipolar Technology- PR40 SOI
GLASSIVATION
Type: Nitrox
Thickness: 15kÅ
Metallization Mask Layout
DNC
DNC
DNC
VS
COMP
VOUT
SENSE
GND
POWR
VOUT
FORCE
GND
QUIET
Submit Document Feedback
10
(see Note
12, Table 4)
TRIM
FN8452.4
March 18, 2016
ISL71090SEH12
TABLE 4. DIE LAYOUT X-Y COORDINATES
PAD NAME
PAD NUMBER
X
(µm)
Y
(µm)
BOND WIRES PER PAD
GND PWR
2
-104
0
1
GND QUIET
1
0
0
1
COMP
3
-108
589
1
VS
4
-125
1350
1
DNC
5
-108
1452
1
DNC
6
1089
1452
1
DNC
7
1089
1350
1
VOUT SENSE
8
1072
598
1
VOUT FORCE
9
1088
1
1
TRIM
10
985
-25
1
NOTES:
12. Origin of coordinates is the centroid of GND QUIET.
13. Bond wire size is 1.0 mil.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
CHANGE
March 18, 2016
FN8452.4
-Changed title from “Radiation Hardened Ultra Low Noise, Precision Voltage Reference” to “1.25V Radiation
Hardened Ultra Low Noise, Precision Voltage Reference”
-Updated Related Literature document titles to match titles on the actual documents.
-Added Table 1 on page 2.
On page 5:
-Changed Electrical Specification for Flatpack note from: "Boldface limits apply over the operating
temperature range, -55°C to +125°C and radiation." To: "Boldface limits apply after radiation at +25°C or
across the operating temperature range, -55°C to +125°C without radiation, unless otherwise specified.
-For parameter VOA (row 4) in Electrical Specifications for Flatpack table changed description from: "VOUT
Accuracy, Post Rad", to: "VOUT Accuracy at TA = +25°C, Post Rad" and for parameters VOA (rows 2, 3, 4)
added "Note 9" to Conditions column.
On page 6:
-Changed Electrical Specification for Die note from: "Boldface limits apply over the operating temperature
range, -55°C to +125°C and radiation." To: "Boldface limits apply after radiation at +25°C or across the
operating temperature range, -55°C to +125°C without radiation, unless otherwise specified.
- Added "VOA Post Rad" parameter, and for VOA (rows 2, 3, and 4) parameters added "Note 11" to
Conditions column.
August 14, 2015
FN8452.3
Updated second sentence on page 1
From: The ISL71090SEH12 uses the Intersil Advanced Bipolar technology to achieve sub 1µVP-P noise at
0.1Hz with an accuracy over temperature and radiation of 0.15%.
To: The ISL71090SEH12 uses the Intersil Advanced Bipolar technology to achieve sub 1µVP-P noise at 0.1Hz
with an accuracy over temperature of 0.15% and an accuracy over radiation of 0.15%.
Updated Features to have accuracy over-temperature and radiation on separate lines
Updated output capacitor in Figure 1 from 1µF to 0.1µF.
Added “Typical Trim Application Diagram” on page 4
Added in Electrical Spec Table “VOUT Accuracy at TA = +25°C, Post Radiation” on page 5
Updated Table 2 on page 9 second and last rows from 1, 1, 10, 10 to 1, 10, 10, 30 and added titles to both
Tables 2 and 3.
Updated POD K8.A to most recent revision. Change is as follows:
Modified Note 2 by adding the words ...”in addition to or instead of”...
Submit Document Feedback
11
FN8452.4
March 18, 2016
ISL71090SEH12
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision. (Continued)
DATE
REVISION
CHANGE
September 13, 2013
FN8452.2
Changed the output voltage noise value from 2µVP-P to 1µVP-P throughout the datasheet.
Figures 7, 11 changed VOUT value from VOUT = 1.25 to VOUT = 1.252
Removed (VOUT = 1.25V) from “Noise Performance and Reduction” section.
Updated Related Literature on page 1, as follow: Changed the link from AN1863 to AN1848 and AN1864 to
AN1849. Changed SEH12 to SEHXX.
Electrical specifications table for output voltage (VOUT) on page 5 and page 6 : Removed VIN = 5V from
conditions cell.
Electrical specifications table for dropout voltage on page 5 and page 6: Changed VOUT = 1.25V @ 10mA to
IOUT @ 10mA.
Electrical specifications table for V0A on page 5 and page 6: Updated conditions cell from VOUT = 1.25V TO
VOUT=1.252V.
Electrical specifications table for Flatpack on page 5 as follow: Removed VOUT = 1.25V from Input Voltage
Range, Line Regulation, Dropout Voltage, Output Voltage Noise, Broadband Voltage Noise, Noise Density.
Electrical specifications table for Die on page 6 as follow: Removed VOUT = 1.25V from Input Voltage Range,
Line Regulation, Dropout Voltage.
Figure7 on page 6: Added slew rate: 2 mA/us.
Typical Performance Curves on page 7 added to header: “COUT = 0.1µF, COMP = 1nF”.
Added die sale part number to Electrical spec table on page 6.
Electrical Spec on page 5: Changed CC = 0.02µF to CC = 1nF and changed IOUT = 0 to IOUT = 0mA.
Added the part numbers ISL71090SEHVX12 and ISL71090SEHX12SAMPLE to ordering information table on
page 2.
Figure 1 on page 1: Added 1nF cap on comp pin.
Added a note to Pin Configuration on page 3.
Removed a note from Electrical spec table on page 6.
August 8, 2013
FN8452.1
Update app note link in Related literature from AN1862 to AN1847.
June 26, 2013
FN8452.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
12
FN8452.4
March 18, 2016
ISL71090SEH12
Package Outline Drawing
K8.A
8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 4, 12/14
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
0.005 (0.13)
MIN
4
PIN NO. 1
ID AREA
0.022 (0.56)
0.015 (0.38)
0.110 (2.79)
0.087 (2.21)
0.265 (6.73)
0.245 (6.22)
TOP VIEW
0.036 (0.92)
0.026 (0.66)
0.009 (0.23)
0.004 (0.10)
6
0.265 (6.75)
0.245 (6.22)
-D-
-H-
-C-
0.180 (4.57)
0.170 (4.32)
SEATING AND
BASE PLANE
0.370 (9.40)
0.325 (8.26)
0.03 (0.76) MIN
SIDE VIEW
0.007 (0.18)
0.004 (0.10)
NOTES:
LEAD FINISH
0.009 (0.23)
BASE
METAL
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
2. If a pin one identification mark is used in addition to or instead of a tab,
the limits of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
3
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
Submit Document Feedback
13
FN8452.4
March 18, 2016