Standard Products Datasheet PWM5032 RadHard High Speed PWM Controller Radiation Tolerant www.aeroflex.com/PWM March 27, 2015 FEATURES Radiation performance - Total dose > 1 Mrad(Si), Dose rate = 50 - 300 rads(Si)/s - SEL: Immune to 100 MeV-cm2/mg - SEU: Immune up to 20 MeV-cm2/mg (Upsets found were benign and non-stressful to the PWM or supporting electronic components) CMOS low power design Sleep & enable control lines Optimized for applications: buck, boost, flyback, forward and center tapped push-pull converters Supports current mode or voltage mode operations Selectable 50% / 100% duty cycle Under-Voltage lockout with hysteresis Dual ±1Amp peak totem pole outputs 1 MHz maximum – user selectable Low Rho error amp Auxiliary op amp with shut down pin Power OK indicator PWM5034 - Same as PMW5032 except straight leads Designed for commercial, aerospace and high reliability space applications Ceramic 24-lead, hermetic package, .606”L x .293”W x .105”H - PWM5032 Gull Wing leads - PWM5034 Straight leads - Weight: 1.0 g max Evaluation board available for test and evaluation. See Aeroflex Application Note AN5031-1 Aeroflex Plainview’s Radiation Hardness Assurance Plan is DLA Certified to MIL-PRF-38534, Appendix G. Developed in Partnership with JHU/APL and the Technology Application Group for the Mars Technology Program; Part of NASA’s Mars Exploration Program OVERVIEW AND GENERAL OPERATION The chip is a fixed frequency Pulse Width Modulator based on the industry standard UC1843x Series with significant enhancements in performance and functionality. The chip operates in either the voltage or current mode and can support a wide variety of converter topologies. Radiation hardened by design techniques ensure the chip’s outstanding radiation tolerance, > 1 Mrad(Si), while reducing operating current by more than an order of magnitude over comparable parts. The PWM5032 provides an under voltage lockout feature with hysteresis that also provides an output to indicate Power is OK. An input called Sleep is used to power down the entire chip, the Enable input is used to shut down the Oscillator / Output Drives, and the Soft input drives the Output to zero. There is also a signal input called ENAUX that is used to disable the output to the auxiliary op-amp. The dual output drivers are designed using a Totem Pole output capable of sinking and sourcing 50mA constant current and peak currents up to 1 Amp to support a large variety of Power MOSFETs. Additional features that boost the appeal and utility of the part are: Dual break-before-make Totem Pole output stage is employed that virtually eliminates cross conduction and current shoot through Logic level input that allows the user to select either 50% or 100% maximum duty cycle operation Improved oscillator stage that vastly increases waveform linearity and reduces output voltage error Uncommitted on-board op-amp which can be used for signal conditioning, pulse feedback, or any other user defined purpose SCD5031 Rev W VREF 11 PWROK SLEEP 10 3 VCC 1,24 EN 17 50% 2 DRVP 22,23 Undervoltage Lockout Internal Bias Reference Cset 8 Rset 9 SOFT 7 Comp 4 Internal Enable / Shutdown Control 5 21 Duty Cycle Limiting (50% or 100%) Oscillator 2.5V VFB OUTA Logic & Control Functions Current Sense Comparators 2R 1.4V Error Amp Output Drive S Q R Q OUTB R 20 Isense 6 Uncommitted Op-Amp 1V 12 VEE 15 AOUT 16 14 ENAUX PIN 13 NIN 18,19 DRVN FIGURE 1 – Block Diagram SCD5031 Rev W 3/27/15 Aeroflex Plainview 2 PWM5032 PWM PIN DESCRIPTION PIN # SIGNAL NAME FUNCTION DESCRIPTION 1 24 VCC Logic Power 2 50% Input selects maximum duty cycle (50% or 100%). Logic ''1'' selects 50% max duty cycle and Output B is the complement of Output A. Logic ''0'' selects 100% and Output A is in-phase with Output B. 3 SLEEP This Input shuts down all functions on chip when asserted (Active Hi) 4 COMP Output of the error amplifier. Place compensation network from this pin to VFB to stabilize converter. 5 VFB Negative Input to the error amplifier 6 ISENSE Input Current sense pin used for current mode control 7 SOFT This High impedance Input is used to limit the error amplifier output voltage. Applying an RC circuit to this pin provides the standard softstart function. Pull this pin to ground to force zero duty cycle. **NOTE: Do not tie this pin directly to VCC. Pull to VCC through a 1K minimum resistor. This input is internally routed to ground when Enable (pin 17) is low, Sleep (pin 3) is high or an Under Voltage is detected. 8 CSET Works with Rset to establish oscillator free running frequency. Place cap from this Input pin to ground. Can synchronize oscillator by overdriving this pin with an external frequency source. 9 RSET Works with Cset to establish oscillator free running frequency. Place resistor from this Input pin to ground. 10 PWROK Logical output of UV lockout circuit -- logic ''1'' indicates chip has valid Vcc 11 VREF Buffered 3V Output reference voltage 12 VEE Logic Ground 13 NIN Auxiliary Op-Amp Inverting Input 14 PIN Auxiliary Op-Amp Non-Inverting Input 15 AOUT Auxiliary Op-Amp Output (Short circuit protected) 16 ENAUX Input Enable of Auxiliary Op-Amp (Active Hi) 17 EN Logic Input that enables the oscillator and output drivers. Reference voltage remains valid (Active Hi). 18 19 DRVN Output stage negative rail 20 OUT B Totem pole Output B 21 OUTA Totem pole Output A 22 23 DRVP Output stage positive rail SCD5031 Rev W 3/27/15 Aeroflex Plainview 3 ABSOLUTE MAXIMUM RATINGS 1/, 4/ Operating Temperature Range Maximum Junction Temperature Storage Temperature Range VCC Supply Voltage DRVP Supply Voltage -55°C to +125°C +135°C -65°C to +150°C 7.0VDC 7.0VDC 14.0VDC ±50mA ±1.0A VEE - 0.5V to VCC + 0.5V 500mW 450V 300°C -0.5V to VCC + 0.5V PWM5031 PWM5032 Steady State Output Current Peak Output Current (Internally Limited) Analog Inputs (Pins 5, 6, 13, 14) Power Dissipation at TA = +25°C ESD Rating 2/ Lead Temperature (soldering, 10 seconds) Digital Inputs NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. These are stress rating only; functional operation beyond the "Operation Conditions" is not recommended and extended exposure beyond the "Operation Conditions" may effect device reliability. OPERATING CONDITIONS 1/, 4/ PARAMETER DC Operating Voltage Quiescent Current PWM5031 PWM5032 Output Drive Voltage CONDITION SYMBOL MIN TYP MAX UNIT SLEEP @ '0'; EN & ENAUX @ '1': No loads on Outputs PWROK, AOUT and VREF VCC 4.5 - 5.0 - 5.5 5.8 V mA - - 7.1 mA - DRVP - - 5.0 12.0 V V - 97* - - 50 % % - - - 6.0 20 °C/W µA PWM5031 PWM5032 Output Duty Cycle – Maximum 50% Pin = Logic 0 50% Pin = Logic 1 Thermal Resistance TJC Sleep Mode 100% Duty Cycle 50% Duty Cycle - ICC ICCS * Dependent on Value of CSET & Operating Frequency ELECTRICAL CHARACTERISTICS 1/, 4/ 4.5 V < Vcc < 5.5V, -55°C < TA < +125°C, unless otherwise specified, EN = 1, Frequency = 209KHz PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Reference Section Reference Voltage Line Regulation Load Regulation Thermal Regulation TA = 25°C, IO = -1 mA, DRVP = 12V 0 < IO < 3 mA 3/ - 3.00 - 3.05 ±.1 ±.05 ±1 3.10 ±.12 ±.075 ±1.6 V % % % Output Short Circuit 3/ - - -40 mA - 201 209 217 KHz 20 - 1,000 KHz - ±2.0 ±3.8 % - ±0.5 ±1 % 50 - - K - - 600 pF Oscillator Section Initial Accuracy Range PWM5032 Frequency Range Frequency Stability (Part to Part) Temperature Stability RSET Range CSET Range 3/ TMIN < TA < TMAX, 3/ SCD5031 Rev W 3/27/15 3/ Aeroflex Plainview 4 ELECTRICAL CHARACTERISTICS 1/, 4/ 4.5 V < Vcc < 5.5V, -55°C < TA < +125°C, unless otherwise specified, EN = 1, Frequency = 209KHz PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - - 3.3 mV VEE + 0.2 - VCC - 0.2 V - - -1.0 µA 100 - - dB Unity Gain Bandwidth 1.0 2.0 - MHz Power Supply Rejection Ratio (PSRR) 60 - - dB - - +10 mA - - -28 mA VSOFT 0.2 - - - V - VEE + 0.2 V Error Amp Section Input Offset Voltage Input Common Mode Voltage Range Input Bias Current Open Loop Voltage Gain (AVOL) 3/ Output Sink Current VFB = 3.0V, VSOFT = 1.1V, Output Source Current VFB = 2.0V, VSOFT = 5V, VOUT High (Limited by VSOFT) 3/ 3/ VFB = 2.0V, RL = 15K to GND VOUT Low VFB = 3.0V, RL = 15K to +5V Gain (VCOMP/VI SENSE) 3/ 2.85 3 3.15 V/V Input Offset Voltage 3/ - - 3.3 mV Common Mode Input Voltage VSOFT = 5V, 0.1 - 1.0 V - - 1.0 µA - 80 100 ns ISINK = 1.0mA - - 0.1 V ISINK = 50mA PWM5031 - - 0.25 V ISINK = 50mA PWM5032 - - 0.6 V ISOURCE = 1.0mA, DRVP = 5V 4.9 - - V ISOURCE = 50mA, DRVP = 5V 4.6 - - V ISOURCE = 1.0mA, DRVP = 12V 11.9 - - V ISOURCE = 50mA, DRVP = 12V 11.4 - - V Peak Output Current 3/ ±1.0 ±1.35 - A Steady State Output Current - - - 50 mA - 8 18 ns - 6 28 ns - - 100 ns - - 100 ns - - 100 ns Current Sense Section Input Bias Current ISENSE to Output Delay 3/ 4/ 3/ Output Section Output Low Level Output High Level-PWM5031 Output High Level-PWM5032 Rise Time Fall Time TA = 25°C, CL = 20pF, DRVP = 5V 3/ Enable Output Off Delay Sleep Output Off Delay 3/ Under Voltage Output Off Delay SCD5031 Rev W 3/27/15 Aeroflex Plainview 5 ELECTRICAL CHARACTERISTICS 1/, 4/ 4.5 V < Vcc < 5.5V, -55°C < TA < +125°C, unless otherwise specified, EN = 1, Frequency = 209KHz PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - - 3.5 mV VEE + 0.2 - VCC - 0.2 V - - 1.0 µA 100 - - dB 1.0 - - MHz 60 70 - dB - - +45 mA - - -28 mA VCC - 0.3 - - V - - VEE + 0.2 V 3.9 3.35 4.1 3.5 4.25 3.65 V V 2.0 - - 0.8 100 V V nA VCC - 0.6 - VEE + 0.3 - V V Auxiliary Amp Section Input Offset Voltage - Input Common Mode Voltage Range Off VEE or VCC Rail, Input Bias Current 3/ AVOL f = 40KHz, 2V < VO < 4V, Unity Gain Bandwidth 3/ PSRR 4.5V < VCC < 5.5V, Output Sink Current Output Source Current VOUT High VOUT Low 3/ 3/ 3/ VPIN < VNIN, ENAUX = Hi, 3/ VPIN > VNIN, ENAUX = Hi, IO = 2mA Under-Voltage Lockout Section Start Threshold Operating Voltage After Turn On Digital Inputs VIL VIH Leakage Current - IIN Logic Low, Logic High, 3/ Digital Ouput (PWROK) VOL VOH Logic low at 1.6mA Logic high at -1.6mA 3/ 3/ Notes 1/ All voltages are with respect to Pin 12. All currents are positive into the specified terminal. 2/ Meets ESD testing per MIL-STD-883, method 3015, Class 1A. 3/ Parameters are guaranteed by design, not tested. 4/ All electrical characterizations for the PWM5034 are the same as the PWM5032. SCD5031 Rev W 3/27/15 Aeroflex Plainview 6 DETAILED COMPONENT OPERATION AND PERFORMANCE POWER SUPPLIES 1) Four I/O pins are used to supply power to the chip: Two pins for DRVP (referenced to DRVN) and two pins for VCC (referenced to VEE) 2) VCC & DRVP can be powered up in any sequence without damage to the chip. a) If VCC is applied first, the output will float until the DRVP voltage is applied. i) If the application requires the outputs to be off during power-up conditions, the VCC must be turned on before DRVP. b) If DRVP is applied before the VCC, the output will go to the potential on DRVP. 3) For protection against inadvertent over/undervoltages, the chip’s input pins are diode clamped to the supply rails through current limiting resistors. UNDERVOLTAGE LOCKOUT The chip includes an internal undervoltage lockout circuit with built in hysteresis and a logic level power good indicator. The positive and negative going thresholds are nominally 4.1V and 3.5V, respectively. If Vcc is below this range, the oscillator, error amplifier, main comparators, and output drive circuits are all disabled. The power OK indicator is active high (logic ''1'') when a valid supply voltage is applied. POWER OK 1 Vcc 24 ICC ON/OFF COMMAND TO REST OF IC 4.6mA Von Voff 4.1V 3.5V 4.4mA VOFF VCC VON FIGURE 2 –Undervoltage Lockout SHUTDOWN LOGIC The chip has two logic level inputs for implementing shutdown functions. Asserting a logic ''1'' on the SLEEP pin disables all chip functions and puts the chip into a very low power consumption mode. Asserting a logic ''0'' on the EN pin shuts down all functions except the reference, bias generators, and auxiliary amplifier. INPUTS OUTPUTS Sleep EN ENAUX OUTA&B AOUT COMP PWROK Vref 0 0 0 0 0 0 Active 3 VDC 0 0 1 0 Active 0 Active 3 VDC 0 1 0 Active 0 Active Active 3 VDC 0 1 1 Active Active Active Active 3 VDC 1 X X 0 0 0 0 0 X = Don’t care. Truth Table SCD5031 Rev W 3/27/15 Aeroflex Plainview 7 OSCILLATOR The chip uses two precision current mirrors that alternately charge and discharge an external capacitor to generate an extremely linear sawtooth oscillator waveform. At the start of each cycle, the charging current, set by the choice of resistor at the Rset pin, is 1:1 mirrored over to the Cset pin where it charges an external capacitor. When the capacitor voltage reaches the comparator’s upper threshold (nominally VREF), the comparator switches current mirrors and begins to discharge the external capacitor. The discharge current is set at roughly five times the charging current to result in fast discharge and minimal Dead Time. When the voltage reaches the comparator’s lower threshold (0.9V), the comparator switches back to the charging mirror, powers down the discharge mirror, and the whole process repeats. The frequency is set by choosing Rset and Cset such that: = 1 (.7 x RSET x (CSET + 16PF)) + (5250 x (CSET + 12PF)) 20KHz F OSC 1MHz Rset 9 Suggested Ranges for Cset and Rset are: 50K ohms < Rset < 300K 10pf < Cset < 600pF Cset 8 Ct Rt GND 12 320 300 280 260 240 220 200 Rset 180 160 140 120 100 80 60 40 390pF 200pF 100pF 47pF 10 20pF 10pF 100 1000 Frequency Khz FIGURE 3 – Timing Resistance vs Frequency SCD5031 Rev W 3/27/15 Aeroflex Plainview 8 DEAD TIME The amount of dead time determines the maximum duty cycle that can be achieved. The Dead Time and the frequency of operation will determine the duty cycle. Dead Time Duty Cycle = 1 – -------------------------- 1F osc Dead Time = 5250 C set + 12pF SELECTING RSET AND CSET To select values for RSET and CSET perform the following steps to insure the smallest Dead Time.. 1) Determine what frequency is required for your design. 2) Use Figure 4 to select a capacitor value for Cset that will provide the highest duty cycle (shortest Dead Time) at the frequency required. 3) Calculate the value of Rset using the formula: Note small values of Rset increase power consumption for the PWM5032 and small values of Cset may make PCB and stray capacitance a source of error. 100.00% 98.00% 390pF 200pF 100pF 47pF 20pF 10pF 96.00% Duty Cycle 94.00% 92.00% 90.00% 88.00% 86.00% 10.00 100.00 1000.00 Frequency Khz FIGURE 4 – Duty Cycle vs Frequency SCD5031 Rev W 3/27/15 Aeroflex Plainview 9 If desired, the user can synchronize the oscillator to an external frequency source by coupling a pulse train to the Cset pin: Sync Pulse 2nF 24 Cset To PWM FIGURE 5 – PWM can be synchronized to external source with just two additional components. Operation is similar to the free running case. Cset is alternately charged and discharged by the same current mirrors and the same comparator and thresholds are used. The only difference is that when a sync pulse is received, the capacitor voltage is level shifted up and reaches the comparator’s upper threshold voltage before it normally would in the free running case. If a series of pulses are received with shorter period than that of the free running oscillator, the comparator will trip in response to the sync pulse and the oscillator will be synchronized. (NOTE: The user must ensure that the sync pulse does not induce a voltage on CSET that exceeds the PWM5032 voltage rating. If this cannot be guaranteed, a simple diode clamp to the positive rail should be used to prevent damage to the PWM) ERROR AMPLIFIER The main error amplifier is a N-type input folded cascade configuration with a few interesting additions. The positive input is internally tied to 2.5V derived from the on chip reference. The negative input typically draws less than 1µA and has a voltage offset of less than 2mV. At 20µA bias current, the amplifier exceeds 2MHz bandwidth and 120dB open loop gain (see Figure 7). The amplifier is designed to limit at whatever voltage is applied to the SOFT pin. As mentioned previously, this function will allow the user to implement a softstart circuit, a controlled turn-on delay, or any number of other useful functions. SCD5031 Rev W 3/27/15 Aeroflex Plainview 10 VSOFT 7 2.5V 5 VFB IS Error Amp 2R 1.4V R Current Sense Comparators 4 COMP R 6 RS C 12 S Q R Q CURRENT SENSE VEE 1V Peak Current (Is) is determined by the formula: I S MAX = 1.0V ----------- or if V 1Volt then I S MAX RS RS = V SOFT – 1.4 -------------------------------3R S A small RC filter may be required to suppress switch transients FIGURE 6 – Current Sense Circuit 120 80 -55°C Gain dB +125°C 40 0 -40 1 10 100 1K 10K 100K 1M 10M Frequency Hz (Log Scale) FIGURE 7 – Error Amplifier Open-Loop Frequency Response at +125°C & -55°C SCD5031 Rev W 3/27/15 Aeroflex Plainview 11 OUTPUT DRIVE Dual push-pull outputs OutA and OutB are provided for driving off chip switches. The output stages are identical: u u u u u Totem Pole configuration Break-before-make switching to prevent harmful cross-conduction spikes Separate positive and negative supply connections to decouple power stage and sensitive logic Near rail-to-rail voltage swing ±1A maximum peak current capability (capacitive load) The outputs have two modes of control depending on whether the 50% toggle option is selected. In the case where the 50% pin is logic low, the outputs are in-phase with each other and the duty cycle is free to take on any value up to 100%. However, when the 50% pin is asserted high (logic ''1''), the outputs become limited to a maximum 50% duty cycle by turning off each output on every other clock period of the oscillator. In addition Output A and Output B will never turn on during the same clock cycle, see Figure 7A below. This would lend itself to a two phase switching system that would be 180° out of phase.. OSC MAX OUTPUT @ 100% PIN 2 SET LOW, 100% MODE OUT A OUT B MAX OUTPUT @ 50% PIN 2 SET HI, 50% MODE OUT A OUT B OUTPUT @ 25% OUT A OUT B FIGURE 7A – Output Drive Options SCD5031 Rev W 3/27/15 Aeroflex Plainview 12 600 500 VSAT mV 400 300 5032 200 5031 100 0 1 10 Current mA 100 FIGURE 8 – Output Sink and Source Saturation Characteristics at +25°C AUXILIARY AMPLIFIER The chip includes an uncommitted op-amp with independent shutdown feature for use in any user-defined application. Some possibilities are: u Signal conditioning of an isolated configuration feedback voltage u Implementation of more sophisticated compensation networks for control loop optimization The Auxiliary amplifier has a unity gain bandwidth greater than 1MHz and an open loop gain greater than 100dB. The ENAUX pin is active high such that a logic ''1'' enables the amplifier and logic ''0'' disables it. The amplifier has near rail-to-rail capability on both the input and output. A typical single output forward converter application is shown in Figure 9 to aid in the following operational description. During normal operation, the oscillator jumpstarts each switching cycle by resetting the RS latch, causing the output stage to go high and turn on M1. Current begins to build linearly through T1 and M1 and a proportional voltage is developed across the small sense resistor Rs. Switching spikes are filtered by C1 and R1, and the resulting sawtooth waveform is passed into the PWM to serve as the current comparator input. Meanwhile, a portion of the output voltage is sensed and compared to the PWM’s internal precision 2.5V reference. The difference is then amplified and level shifted to serve as the comparator threshold. When the voltage on the ISENSE pin exceeds this threshold, the comparator fires and resets the latch. The output then turns off until the beginning of the next oscillator cycle when the process repeats. SCD5031 Rev W 3/27/15 Aeroflex Plainview 13 TYPICAL APPLICATIONS T1 3.3V, 0.5A +5VDC 0.1µF VCC EN DRVP Out A Out B VREF ISENSE M1 R1 C1 RSOFT Rs 50% SOFT COMP M2 CSOFT Isolation Barrier Cset Optional circuit to force zero duty cycle Rset CSET Opto-Isolator or Pulse Transformer VFB RSET VEE DRVN FIGURE 9 – Typical Forward Converter Application Like all current mode PWMs, the chip provides built in fault protection by limiting peak switch current on a cycle by cycle basis. When an overload condition occurs, the sensed current reaches the current trip threshold earlier in the switching cycle than it otherwise would and thus forces the PWM latch off until the start of the next cycle. The process repeats until the overload condition is removed and the PWM can return to a normal duty cycle. The chip is capable of operating in this mode indefinitely without sustaining damage. There are two ways to set the current limit trip point. One is to simply tailor the sense resistor Rs: I pk = 1.0Vdc ----------------Rs Some users may find the power is dissipated in Rs to be unacceptably high. In this case, the user can fix Rs at a small value and vary the current comparator threshold instead. Fortunately, the PWM chip provides a very convenient method for doing so. Because the error amplifier output is internally clamped to the SOFT pin, the user need simply apply the desired voltage level to the SOFT pin to arbitrarily lower the current comparator threshold. Recalling that the EA output is level shifted and divided before being applied to the comparator input, the peak current limit is chosen by applying a voltage VSOFT such that: V soft – 1.4 I pk = ----------------------3 Rs 1.4V V soft 4.4V Clamping the EA output to the soft pin also makes implementing a softstart ciruit easy. Rsoft and Csoft are connected as in Figure 9 to provide the SOFT pin an asymptotically rising voltage. Because of the internal clamp on the EA output, the PWM duty cycle will increase only as fast as the chosen time constant will allow. In this way, excessive duty cycle and surge currents into the output capacitors are avoided. A transistor may be optionally connected across the softstart SCD5031 Rev W 3/27/15 Aeroflex Plainview 14 capacitor to force zero duty cycle on command. This is a particularly convenient method for implementing an externally controlled turn-on delay. The discussion so far assumes the user operates the chip in the current mode: switch current is sensed and compared to the error between the output voltage and a precision reference. Alternatively, the user may wish to implement voltage mode control in which the control loop is dependent only on the output voltage. The PWM chip readily supports this configuration with the following modification: M1 Out Switch Current Isense Vref 2N2222 Cset Cset FIGURE 10 – Circuit for implementing voltage mode control. A portion of the oscillator’s sawtooth waveform is coupled to the ISENSE pin and becomes the input to the comparator stage. The operation is now identical to the current mode application: when the sawtooth voltage exceeds the amplified difference between the output and a voltage reference, the comparator fires and latches off the output until the start of the next cycle. SELECTED APPLICATION EXAMPLES The flexibility and performance of the chip makes it suitable for an enormous range of power converter applications – step-up, step-down, DC-DC, AC-DC, isolated/non-isolated, and many more. This section will cover two of the more popular power converter applications for which this chip is particularly well suited although many more can be envisioned. 5V INPUT, 3.3V ISOLATED OUTPUT (SINGLE ENDED FORWARD CONVERTER) The isolated step down DC/DC converter is a staple of many satellite and aerospace systems. A common bus distributes raw primary power to various system loads which must then convert the primary to one or more low voltage secondary outputs. These outputs are filtered, regulated, and ground isolated from the primary side to keep EMI and undesired subsystem interaction at a minimum. Figure 9 is one example of a circuit that very efficiently performs this conversion. The values here were chosen to work for a 5V input and 3.3V output but the circuit topology is general enough to support an infinite variety of applications. For example, output voltages can be adjusted by changing values of just a few components. A wider input voltage range can be supported by varying the transformer’s turns ratios and by proper selection of M1. Thus, a very wide range of power converter applications can be satisfied by simple variations of the circuit. At the start of each switching cycle, the PWM output goes high and turns on M1. Energy is coupled across T1’s turns ratios to the secondary side where it is caught, rectified, and filtered to produce a clean DC voltage. A sampling network on the output side feeds back a portion of the output across the isolation barrier into the error amplifier negative input. This feedback can be accomplished in a number of different ways: pulse transformers, optocouplers, or capacitive coupling are a few methods. The compensation network may need modification depending on the feedback method chosen. The additional winding and rectifier on T1 are used to reset the transformer core after the PWM latches off M1 to prevent staircase saturation of the core. Note the chip is powered directly from the main power bus (via a zener and current limit resistor) without the need for additional bootstrap transformer windings. This is one of the main advantages this PWM chip provides over other products. This scheme could not be implemented with other chips which draw significantly more current. On the other hand, supplying bias to our PWM chip is about as simple as it gets. SCD5031 Rev W 3/27/15 Aeroflex Plainview 15 5V TO 1.8V BUCK CONVERTER A second application is a secondary side, non-isolated buck converter. The circuit takes a high voltage (5V in this case) and steps down to a lower voltage (5V to 1.8V in this example, although as pointed out above, these values are completely adjustable with proper component selection). If the output voltage is less than 2.5V the auxiliary amplifier can be used to provide the gain necessary to get VFB back up to 2.5V. INPUT 5V 0.1µF VCC DRVP VREF RSOFT SOFT M1 Out A OUTPUT CSOFT 1V/1.8V/2.5V/3.3V D1 CSET CSET RSET RSET ISENSE COMP Rcomp 50% Ccomp VFB VEE DRVN FIGURE 11 – Buck Converter The circuit switches M1 twice per cycle, chopping the 5VDC input into a fixed frequency pulse train whose DC average is the desired output voltage. The LC filter then simply smoothes this pulse train to produce a clean DC output. The control loop regulates against operating point perturbations (temperature, line, load) by adjusting M1's duty cycle. The circuit is operated in the voltage mode since switch current is not referenced to circuit ground. Alternatively, a current transformer may be used to properly reference the ISENSE signal to permit current mode control. An inverter is needed in the output path to properly drive the P-channel MOSFET. For low current applications (less than -50mA output current), it may be possible to use the PWM's output drive stage as the switching elements and eliminate M1 and D1 altogether. SCD5031 Rev W 3/27/15 Aeroflex Plainview 16 VCC 1 24 VCC 50% 2 23 DRVP SLEEP 3 22 DRVP COMP 4 21 OUTA VFB 5 20 OUT B ISENSE 6 19 DRVN SOFT 7 18 DRVN CSET 8 17 EN RSET 9 16 ENAUX PWROK 10 15 A OUT VREF 11 14 PIN VEE 12 13 NIN Note: The Lid is connected to pin 12 FIGURE 12 – Package Pin vs Function SCD5031 Rev W 3/27/15 Aeroflex Plainview 17 PIN 1 & ESD IDENT .394 .419 .300 MAX PIN 24 .614 MAX .019 .015 11 x .050 = .550 ±.006 .130 MAX .030 REF .008 ±.0012 .022 ±.005 .012 MAX .335 MIN .354 REF FIGURE 13 – PWM5031 /PWM5032 Flat Package (Gull Wing) Configuration Outline .614 MAX PIN 24 .110 MAX 11 x .050 = .550 ±.006 .008 ±.0012 .500 (1.300) .300 MAX .500 PIN 1 & ESD IDENT .019 .015 .022 FIGURE 14 – PWM5034 Flat Package (Straight Leads) Configuration Outline SCD5031 Rev W 3/27/15 Aeroflex Plainview 18 CONFIGURATIONS AND ORDERING INFORMATION MODEL DLA SMD # PWM5032-7 PACKAGE Commercial Flow, 0°C to +70°C - PWM5032-S PWM5032-001-1S 5962-0625102KXC PWM5032-001-2S 5962-0625102KXA PWM5034-7 Military Temperature, -55°C to +125°C Screened in accordance with the individual Test Methods of MIL-STD-883 for Space Applications Flat Package Gull Wing In accordance with DLA SMD Commercial Flow, 0°C to +70°C - PWM5034-S PWM5034-001-1S SCREENING 5962-0625102KYC PWM5032-EVAL - Military Temperature, -55°C to +125°C Screened in accordance with the individual Test Methods of MIL-STD-883 for Space Applications Flat Package Straight Lead In accordance with DLA SMD See Application note AN5031-1 1/ 8'' x 11'' x 3.25''ht 1/ Application note AN5031-1, titled “ High Speed Pulse Width Modulator Controller Evaluation Board”. Evaluation board PWM5032-EVAL is supplied with a PWM5032-7 component. EXPORT CONTROL: This product is controlled for export under the U.S. Department of Commerce (DoC). A license may be required prior to the export of this product from the United States. www.aeroflex.com/HiRel [email protected] Datasheet Definitions: Advanced Preliminary Datasheet Product in Development Shipping Non-Flight Prototypes Shipping QML and Reduced HiRel Aeroflex Plainview, Inc. reserves the right to make changes to any products and services described herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. SCD5031 Rev W 3/27/15 19 Our passion for performance is defined by three attributes. Solution-Minded Performance-Driven Customer-Focused