LINER LT3804EFE

Final Electrical Specifications
LT3804
Secondary Side Dual
Output Controller with Opto Driver
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FEATURES
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The LT®3804 is a high efficiency step-down switching
regulator with optocoupler feedback control for regulating
multiple outputs in single-secondary winding isolated
power supplies.
Regulates Two Secondary Outputs
Optocoupler Feedback Driver and Second Output
Synchronous Driver Controller
True Differential Remote Sensing Regulation
High Switching Frequency: up to 800kHz
Programmable Current Limit
Programmable Soft-Start and Power Good
Automatic Frequency Synchronization
Available in Thermally Enhanced 28-Lead TSSOP
The LT3804 contains an error amplifier and an optocoupler
driver to regulate the first (main) output. For the second
output regulation, the LT3804 contains a complete PWM
controller to drive dual synchronous N-channel MOSFETs.
With leading edge modulation, it operates with either
current or voltage mode control of the primary side. The
LT3804 is synchronized to the falling edge of the transformer secondary winding and can be used in singleended or double-ended isolated power converter topologies. A user selectable discontinuous conduction mode
improves light load efficiency.
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APPLICATIO S
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June 2003
DESCRIPTIO
48V Input Isolated DC/DC Converters
Multiple Output Power Supplies
Offline Converters
DC/DC Power Modules
True differential Kelvin sensing is used for each output
feedback amplifier to achieve high regulation accuracy
and design simplicity. Other features include soft start,
current limit and power good flags.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
VIN
36V
TO 72V
L1
1.8µH
VCC
BIAS
•
•
Q4
0.003Ω
OUT2
CL1P
OUT1
IN1 IN2
VCC
CSET
+
VOUT1
3.3V
AT 15A
COUT1
LT3804
SYNC
CL1N
LTC1693-1
Q3
x2
VOS1+
VOS1–
Q1
TGATE
L2
1.8µH
0.003Ω
SW
+
COUT2
Q2
x2
BGATE
390pF
VOUT2
1.8V
AT 15A
PGND
VOS1–
TG
•
BG
GNDS1
•
VAOUT2
VOS1+
LT3781
CL2P
CL2N
604Ω
2.74k
VFB1
SG
•
VC
+
–
VREF
1.5k
VAOUT1
VFB
OPTO
ISOLATION
BOUNDARY
3.01k
VFB2
•
GNDS2
3804 F01
COUT1, COUT2: SANYO POSCAP 4TPE680MF 680µF/4V
L1, L2: SUMIDA CEP125-IR8MC-H
Q1-Q4: SILICONIX Si7892DP
Figure 1. 250kHz, 3.3V and 1.8V Output Isolated DC/DC Converter (Simplified Schematic)
3804i
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT3804
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC Supply Voltage .................................................. 26V
BOOST Pin Voltage with Respect to SW Pin ............ 10V
BOOST Pin Voltage with Respect to GND Pin .......... 35V
SYNC Pin Voltage (Note 2) ..................................... 30V
GNDS1 Pin Voltage ................................................... 1V
GNDS2 Pin Voltage ................................................... 1V
Operating Junction Temperature Range
LT3804E (Note 3) ..............................–40°C to 125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
CL1P
1
28 ILCOMP1
CL1N
2
27 GBIAS
ILCOMP2
3
26 BGATE
BOOST
4
25 VCC
TGATE
5
24 PGND
SW
6
CSET
7
SYNC
8
21 CL2N
SS2
9
20 CL2P
23 OPTO
29
22 VAOUT1
PGIN1 10
19 PGOOD
PGIN2 11
18 VFB1
GNDS2 12
17 SS1
GNDS1 13
16 BGS
VFB2 14
LT3804EFE
15 VAOUT2
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD IS SGND (PIN 29)
MUST BE CONNECTED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, GNDS1=GNDS2=0V, operating maximum VCC = 25V, no load
on any outputs, unless otherwise noted.
PARAMETER
Overall
Supply Voltage (VCC)
Supply Current (IVCC)
BOOST Pin Current
Voltage Amplifier VA1,VA2
Reference Voltage (VREF1,VREF2)
VFB1, VFB2 Pin Input Current
Remote Ground Pin (GNDS1,GNDS2) Current
VAOUT1 High at OA1 Threshold 1.5V
VAOUT1 High at OA1 Threshold 1.25V
VAOUT1 Low
VAOUT2 High
VAOUT2 Low
VAOUT1 Source Current
VAOUT2 Source Current
Open-Loop Gain
Gain Bandwidth Product
Soft-Start Current (SS1,SS2)
CONDITIONS
MIN
●
●
0.591
0.587
–3
●
●
●
MAX
9
25
13
V
mA
2
2
3
3
mA
mA
0.6
0.609
0.609
3
0.5
–100
V
V
mV
µA
µA
V
V
V
V
V
µA
µA
dB
8
VAOUT2 ≤ 1.2V (Switching Off)
VBOOST = VSW + 8V, 0V ≤ VSW ≤ 24V
TGATE High
TGATE Low
Common Mode: ±20mV (0°C to 125°C)
(–40°C to 125°C)
∆VREF over Common Mode: ±100mV
VFB1 = VREF1, VFB2 = VREF2
–100mV ≤ GNDS1, GNDS2 ≤ 100mV
VFB1 = VREF1 – 10mV, I VAOUT1 = –50µA
VFB1 = VREF1 – 10mV, I VAOUT1 = –50µA
VFB1 = VREF1 + 10mV, I VAOUT1 = 100µA
VFB2 = VREF2 – 10mV, I VAOUT2 = –50µA
VFB2 = VREF2 + 10mV, I VAOUT2 = 100µA
TYP
100
70
5
0.2
–50
1.75
1.45
0.7
4.5
0.8
230
150
100
10
10
400
250
24
UNITS
MHz
µA
3804i
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LT3804
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, GNDS1=GNDS2=0V, operating maximum VCC = 25V, no load
on any outputs, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.4
1.55
1.65
V
Opto Driver Amplifier OA1
OA1 Upper Threshold
●
OA1 Threshold Hysteresis
0.25
V
OA1 Voltage Gain (VOPTO/VAOUT1)
1.2V < VOPTO < 4V, ROPTO = 1k
●
5.6
6
6.4
V
VOPTO High
VAOUT1= 0.9V, IOPTO = –10mA
●
4.5
5.2
6
V
VOPTO Low
VFB1 = VREF1 – 10mV, ROPTO = 1k
●
0
0.1
0.25
V
IOPTO Short-Circuit Current Limit
VFB1=VREF1 – 10mV, GNDS1 = 0V,
VOPTO = 4V
●
–50
–25
–12
mA
1.15
VREF
Power Good
Power Good Window Threshold
(PGIN1-GNDS1, PGIN2-GNDS2)
–100mV < GNDS1, GNDS2 < 100mV
0.85
Input Current (PGIN1,PGIN2)
0V < PGIN1, PGIN2 < 1V
Delay Time for Power Bad
25mV Overdrive on PGIN1,PGIN2
●
Output Low (PGOOD)
2mA into the Pin
●
Common Mode Voltage from 0V to VCC – 2.5V
VAOUT1 = 1.2V, VAOUT2 = 2.5V,
●
0.2
0.35
µA
200
300
µs
150
300
mV
40
50
60
mV
0
8
15
mV
100
Current Limit Amplifier CA1, CA2
Current Limit Threshold (CL1P-CL1N, CL2P-CL2N)
BGATE Off Threshold at (VCL2P-VCL2N), BGS Pin Float
Commond Mode Voltage from 0V to VCC – 2.5V
Switching Off Threshold at ILCOMP2
VILCOMP2
Input Current (CL1P, CL1N, CL2P, CL2N)
VCL2P = VCL1N, VCL2P = VCL2N
0.15
V
µA
100
Oscillator
Switching Frequency
CS = 500pF (NO SYNC)
CS = 333pF (NO SYNC)
CS = 200pF (NO SYNC)
●
●
●
170
240
400
Synchronization Frequency Range
CS = 500pF
CS = 333pF
CS = 200pF
●
●
●
245
345
575
CSET Ramp Valley Voltage
CS = 1000pF (NO SYNC)
CSET Peak-to-Peak Voltage
CS = 1000pF (NO SYNC)
2.4
V
Synchronization Pulse Threshold on SYNC Pin
Falling Edge VSYNC
2.5
V
Maximum Duty Cycle
VFB2 = VREF2 – 5mV, CS > 333pF
●
75
80
%
VGBIAS
IGBIAS < 25mA
●
7.5
8
VTGATE High (VTGATE – VSW)
ITGATE < 50mA, VBOOST = VGBIAS – 0.5V
5
6
7.5
V
VBGATE High
IBGATE < 50mA
●
5
6
7.5
V
VTGATE Low (VTGATE-VSW)
ITGATE < –50mA
●
0.5
V
VBGATE Low
IBGATE < 50mA
●
0.5
V
Peak Gate Drive Current
10nF Load
1
A
Gate Drive Rise and Fall Time
1nF Load
25
ns
0.90
200
280
470
1.15
240
340
570
kHz
kHz
kHz
400
500
800
kHz
kHz
kHz
1.4
V
Gate Drivers (TGATE, BGATE)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: If highter than 30V on SYNC pin is needed, add a 10kΩ resistor in
series with the pin.
8.5
V
Note 3: The LT3804E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
3804i
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LT3804
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TYPICAL PERFOR A CE CHARACTERISTICS
VGBIAS vs IGBIAS Over Junction
Temperature
Voltage Amplifier VA1, VA2 Gain
and Phase
ICC vs VCC (Switching Off)
8.1
13
120
TA = 25°C
–40°C
–0
TA = 25°C
12
11
7.9
GAIN
80
10
GAIN (dB)
ICC (mA)
25°C
9
PHASE
40
–100
8
7
7.8
0
125°C
7.7
10
IGBIAS (mA)
0
20
5
26
0dB, 10MHz
–20
8
10
12
14
16 18
VCC (V)
20
22
1.00
800
0.601
0
–1
10
15
VCC (V)
20
∆FREQ (kHz)
1
0.90
0.85
0.80
400
0.75
0.70
200
25
0.599
0.598
0.587
0.596
50
100
–40 –20
25
75
0
JUNCTION TEMPERATURE (°C)
100 200 300 400 500 600 700 800 900 1000
CSET (pF)
3804 G04
0.600
VREF (V)
FREQUENCY (kHz)
0
MAXIMUM DUTY CYCLE
600
MAXIMUM DUTY CYCLE
0.95
2
∆VREF
–180
10M 100M
0.602
TA = 25°C
∆FREQ
10k 100k 1M
FREQUENCY (Hz)
VREF vs Temperature
CSET
–1
1k
3804 G03
CSET vs Switching Frequency
CSET = 500pF
TA = 25°C
1
100
10
24
3804 G02
∆VREF vs VCC, ∆FREQ vs VCC
3
–150
6
3804 G01
∆VREF (mV)
–50
(–111°)
PHASE (DEG)
VGBIAS (V)
8.0
3804 G05
Switching Frequency vs
Temperature
125
3804 G06
Current Limit Amplifier CA1 Gain
at VCC = 11V, VCL2N = 5V
GBIAS vs IGBIAS (Charging 2.2µF)
8
CGBIAS = 2.2µF
TA = 25°C
7
10
6
200
8
5
150
6
100
4
250
IGBIAS (mA)
210
205
200
VGBIAS
IGBIAS
50
VAOUT2 (V)
12
300
215
VGBIAS (V)
SWITCHING FREQUENCY (kHz)
CSET = 500pF
VCC = 11V
VCL2N = 5V
TA = 25°C
4
CSET PEAK
3
2
2
0
1
CSET VALLEY
195
0
50
100
–40 –20
25
75
0
JUNCTION TEMPERATURE (°C)
125
3804 G07
0
500µs
TIME
1ms
3804 G08
0
30
40
50
60
VCL2P – VCL2N (mV)
70
3804 G09
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LT3804
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PI FU CTIO S
CL1P (Pin 1): Current Limit Amplifier CA1 Positive Input.
CA1 drives optocoupler when the first output is in current
limit.The threshold is set at 50mV.
CL1N (Pin 2): Current Limit Amplifier CA1 Negative Input.
When used, CL1N is connected to the output, and CL1P is
connected to the other end of the output current sense
resistor.
ILCOMP2 (Pin 3): Current Limit Amplifier CA2 Compensation Node. At second output current limit, CA2 pulls down
on this pin to regulate output current.
BOOST (Pin 4): Topside (Boosted) Driver Supply.This pin
is used to bootstrap and supply the topside power switch
gate drive circuitry. In normal operation VBOOST is powered
from the internally generated 8V GBIAS; VBOOST = VSW + 8V
when TGATE is on.
TGATE (Pin 5): Topside (Boosted) N-Channel MOSFET
Driver. When TGATE is on, the voltage is equal to VSW + 6V.
SW (Pin 6): Switch Node Connection to Inductor.
CSET (Pin 7): Oscillator Frequency Setting Pin.The capacitor from this pin to ground sets the PWM switching
frequency.
SYNC (Pin 8): Synchronization Input. This pin should be
connected to the secondary side output of the power
transformer with a series resistor. A filtering capacitor of
10pf is recommended.
BGS (Pin 16): Bottom Gate Switching Control. CA2 monitors the inductor current and prohibits BGATE from turning on when the inductor current is low (below 8mV across
the current sense resistor RS2) allowing discontinous
mode operation and avoiding reverse inductor current.
Grounding BGS disables this function, so that the PWM is
always in continuous mode except during start-up.
SS1 (Pin 17): Soft-Start for the First Output. A capacitor on
this pin sets the output ramp-up rate. The typical time for
SS1 to reach the programmed level is:␣ (C • 0.6V)/10µA.
VFB1 (Pin 18): Voltage Amplifier VA1 Inverting Input. A
resistor divider to this pin sets the first output voltage. The
reference voltage at this pin is VREF1 (0.6V referred to
remote sensing ground GNDS1).
PGOOD (Pin 19): Power Good. PGOOD goes high to
indicate power good only when both PGIN1 and PGIN2
sense power good. A pull up resistor is required on this pin
if the power good function is used.
CL2P (Pin 20): Second 0utput Current Limit Amplifier
CA2 Positive Input.The threshold is set at 50mV.
CL2N (Pin 21): Current Limit Amplifier CA2 Negative
Input. When used, CL2N is connected to the output
capacitor, and CL2P is connected to the other end of the
output current sense resistor.
VAOUT1 (Pin 22): Voltage Amplifier VA1 Output.
SS2 (Pin 9): Soft-Start for the Second Output. A capacitor
on this pin sets the output ramp-up rate. The typical time
for SS2 to reach the programmed level is:␣ (C • 0.6V)/10µA.
OPTO (Pin 23): Optocoupler Driver. A resistor to the opto
diode is required to set the optocoupler bias current.
Maximum sourcing current is 10mA at 5V.
PGIN1 (Pin 10): First Output Power Good Input.The voltage setting resistor divider should be connected to GNDS1
if remote sensing is used.
PGND (Pin 24): Ground of the Bottom Side N-Channel
MOSFET Driver.
PGIN2 (Pin 11): Second Output Power Good Input. The
voltage setting resistor divider should be connected to
GNDS2 if remote sensing is used.
GNDS2 (Pin 12): Second Output Remote Ground Sensing.
GNDS1 (Pin 13): First Output Remote Ground Sensing.
VFB2 (Pin 14): Voltage Amplifier VA2 Inverting Input. A
resistor divider to this pin sets the second output voltage.
The reference voltage at this pin is VREF2 (0.6V referred to
remote sensing ground GNDS2).
VCC (Pin 25): Supply of the Chip. A low ESR capacitor is
required to bypass the supply.
BGATE (Pin 26): Bottom Side N-Channel MOSFET Driver.
GBIAS (Pin 27): 8V Regulator Output for Boostrapping
VBOOST. A bypass capacitor of at least 2µF is needed.
ILCOMP1 (Pin 28): Current Limit Amplifier CA1 Compensation Node . When the first output is in current limit, CA1
pulls down VAOUT1 pin to regulate the first output current.
Exposed Pad (Pin 29): Signal Ground. Must be electrically
connected on PCB.
VAOUT2 (Pin 15): Voltage Amplifier VA2 Output.
3804i
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VCC
LT3781
Q3
ISOLATION
BOUNDARY
R11
OPTO
M4
M3
CS
10pF
RS
10k
SS1
CSET
7
8
E2
A7
A1
1.5V/
1.2V
VTH
SHUTDOWN
A2
15k
ONE
SHOT
+ –
CA1
CA
+
ILCOMP1 CL1P CL1N
28
1
2
AGND
29
EXPOSED PAD
NOTE: PACKAGE BOTTOM METAL
PLATE IS FUSED TO SIGNAL GROUND.
2.5V
90k
OA1
8V
+
–
25
–
E4
+
VCC
+
+
17
OPTO
23
D2
SYNC
OPTO
ROPTO
CSS1
1µF
C8
Q1
Q5
R
PWM
OSC
50mV
22
VAOUT1
–
S
18
+
+
CSS2
1µF
–
VA2
+
C16
– +
A8
A4
9
+
D7
D6
SS2
+
50mV
A6
8mV
A11
10µA
+
1.3V
VREF2
0.9
1.1
VREF2
A13
7V
A10
VREF1
0.6V
0.9VREF1
1.1VREF1
13
GNDS1
3.5V
–
CA2
+
1.6V
SS2
+
SW
2.5V
+
+
1.3V
VFB1
A3
D14
10µA
D15
R12
BGATE
–
VA1
+
C12
500pF
+
–
R8
200µA
+
C9
C13
C14
2V
8V
Q2
Q4
PGOOD
R2
R1
200µs
DELAY
+
200µs
DELAY
VREF2
0.6V
C15
+
–
+
–
+
VIN
36V TO 72V
+
–
+
–
–
+
–
C17
200pF
+
–
R7
+
6
–
TRANSFORMER
SECONDARY
OUTPUT
PGIN1
PGND
BGATE
12
14
15
3
21
20
11
C3
2µF
GBIAS
SW
TGATE
BOOST
GNDS2
VFB2
VAOUT2
ILCOMP2
CL2N
CL2P
PGIN2
16 BGS
24
26
27
6
5
4
19 PGOOD
10
R6, 5k
M2
L1
C6, 100pF
C2
0.3µF
M1
L2
COUT2
RS2
COUT1
RS1
3804 BD
R4
R3
R14
R13
VOUT2
R20
R19 LOAD
R17
R16 LOAD
VOUT1
LT3804
BLOCK DIAGRA
3804i
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LT3804
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OPERATIO
To generate isolated multiple outputs, most systems use
either multiple secondary windings or cascade regulators
for each additional output. Multiple secondary windings
sacrifice regulation of the auxiliary outputs. Cascaded
regulators require a larger inductor for the main output,
because all of the power is processed in series. By generating the auxiliary output(s) from the secondary winding
of the main output, the LT3804 allows for parallel processing of the output power. This minimizes the main output
inductor size and directly regulates the auxiliary output.
With synchronous rectification, the system efficiency is
greatly improved.
During normal operation (see Figure 2), a switching cycle
begins at the falling edge of the transformer secondary
voltage VS.
The internal oscillator is reset, turning off the top MOSFET,
M1, and turning on the bottom MOSFET, M2. During this
portion of the cycle, the inductor current is discharged by
the output voltage VOUT2. The transformer secondary
voltage, VS, will go high during this portion of the cycle.
Since M1 is off, the switch node voltage, VSW, remains
zero. The inductor current continues to be discharged by
the output voltage VOUT2. This condition lasts until the
ramp signal intersects the feedback error amplifier output
VAOUT2. The top MOSFET M1 turns on, pulling the switch
node voltage to VS. The inductor current of the LT3804
circuit is then charged by VS – VOUT2. The effective on time
of this buck circuit ends when the secondary voltage
becomes zero. The next cycle repeats. The ideal equation
for duty cycle of the LT3804 is:
The LT3804 regulates both the main and one auxiliary
output, with true remote sensing to achieve high output
accuracy. To regulate the first output, the LT3804 contains
a high gain error amplifier VA1 and an optocoupler driver
OA1 with a unique feature that reduces output overshoot
to a minimum. For details see the Applications Information
section. The second output includes a voltage amplifier,
VA2, (see Block Diagram)a voltage mode PWM with
trailing edge synchronization and leading edge modulation, a current limit amplifier, CA2, and high speed synchronous switch drivers.
D2 = VOUT2/VSP
where VOUT2 is the auxiliary output voltage, VSP is the
amplitude of the secondary voltage and D2 is the duty
cycle of the switching node voltage VSW, as defined in
Figure 2.
VRESET
T
D1T
TRANSFORMER
SECONDARY VOLTAGE
VS
VSP
SYNC SIGNAL VRESET
RAMP VCSET
VAOUT2
TGATE
BGATE
IL2
T
SWITCH NODE VSW
D2T
VSP
3710 F02
Figure 2. Leading Edge Modulation, Trailing Edge Synchronization
3804i
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LT3804
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APPLICATIO S I FOR ATIO
Synchronization and Oscillator Frequency Setting
The switching is synchronized to the secondary winding
falling edge and the synchronization threshold is typically
2.5V. The synchronization falling edge triggers an internal
inverted ramp (see Figure 2) and starts a new switching
cycle for the leading edge voltage mode PWM. The reason
for using leading edge modulation is to leave the transformer primary side peak current sensing undisturbed.
For proper synchronization, the oscillator frequency should
be set lower than the system switching frequency with
tolerances taken into account.
fOSC < (fSL • 0.8)
fSL is the low limit of the system switching frequency and
0.8 is the tolerance of fOSC.
For example, given a system operating at 200kHz with
15% tolerance, then fSL = 200kHz • 85% = 170kHz; and
fOSC < (170kHz • 0.8), so fOSC should be set below 136kHz.
Once fOSC is determined, CSET can be calculated by
CSET = (103540pF/fOSC(kHz)) – 18pF.
For fOSC = 200kHz, CSET = 500pF.
Output Voltage Programming
The LT3804 uses true remote sensing (separate ground
sensing pins, GNDS1 for the first output and GNDS2 for
the second output) to eliminate output error pickup due to
parasitic resistance.
The feedback reference voltages VREF1 and VREF2 are 0.6V
referred to GNDS1 and GNDS2 respectively. The output
voltage can be easily programmed by a resistor divider, as
shown in the Block Diagram:
VOUT1 = 0.6 (1 + R13/R14)
VOUT2 = 0.6 (1 + R3/R4)
For accurate sensing results, GNDS1 and GNDS2 should
stay within –0.1V and 0.1V referred to GND. Note that if
either GNDS1 or GNDS2 is not connected, the LT3804 will
be shut down.
Power Good
When both outputs reach between 90% and 110% of the
programmed level, VPGOOD goes high( a pull-up resistor is
required if the function is used) to signal power good. If
either output rises above 110% or drops below 90%,
VPGOOD goes low after a 200µs delay. PGIN1 senses the
first output and PGIN2 senses the second output with a
resistor divider. PGIN1 and PGIN2 are compared to the
references VREF1 and VREF2 respectively. Resistor dividers
should be connected to GNDS1 and GNDS2 with respect
to each output.
Current Limit CA1
The first output current limit is set by the 50mV threshold
across CL1P and CL1N, the inputs of the amplifier CA1. By
connecting an external resistor RS1(see Block Diagram),
the current limit is set for 50mV/RS1. C17 on ILCOMP1
stablizes the current limit loop. If current limit is not used,
both CL1P and CL1N should be grounded and C17 is not
needed.
Current Limit CA2
The second output current limit is set by the 50mV
threshold across CL2P and CL2N, the inputs of the amplifier CA2. By connecting an external resistor RS2 (see Block
Diagram), the current limit is set for 50mV/RS2. R6 and C6
on ILCOMP2 stablize the current limit loop. If current limit
is not used, both CL2P and CL2N should be grounded and
the BGS pin should also be grounded to disable comparator CA2; R6 and C6 are not needed.
where R14 connects to GNDS1 and R4 connects to
GNDS2.
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Filtering on the SYNC Input
To shut down the first output, the SS1 pin should be pulled
below 50mV by a small signal VN2222 type N-channel
MOSFET.
A small RC filter with RS = 10k and CS = 10pF is necessary
on the SYNC pin to eliminate fast switching glitches
caused by coupling from external components and layout
parasitics.
Soft-Start and Shutdown Second Output
During soft-start, VSS2 is the reference voltage that controls the output voltage, so the output ramps up following
VSS2. The effective range of VSS2 is from 0V to VREF2. The
typical time for the output to reach the programmed level
is:
Optocoupler Driver
Optocoupler driver OA1 is an amplifier with a fixed gain of
6 and can source up to 10mA into the optocoupler. An
external resistor is needed from the OPTO pin to the
optocoupler for DC biasing the optocoupler. With a unique
0.3V hysteresis on the threshold VTH, OA1 turns into a
comparator when it detects output startup or output short.
This comparator action jumpstarts the optocoupler to
reduce the output overshoot drastically (see Figure 3).
t = (CSS2 • 0.6V)/10µA
During start up, BGATE will stay off until VSS2 reaches
1.6V. This prevents the bottom MOSFET from turning on
if the output is precharged. To shut down the second
output, the SS2 pin should be pulled below 50mV by a
small signal VN2222 type N-channel MOSFET. Note that
during shutdown BGATE will be locked off when VSS2
drops below 0.6V. This prevents the bottom MOSFET from
discharging the output, which could cause the output to
undershoot below ground.
Soft-Start and Shutdown First Output
During soft-start, VSS1 is the reference voltage that controls the output voltage, so the output ramps up following
VSS1. The effective range of VSS1 is from 0V to VREF1. The
typical time for the output to reach the programmed level
is:
t = (CSS1 • 0.6V)/10µA
VOUT1
5nF
22nF
1k
R13
2.7k
470Ω
3.3V
VAOUT1
–
1k
ROPTO
90k
1.7V
VAOUT1
15k
1.4V
R14
600Ω
VA1
+
+
OA1
VFB1
1.5V/
1.2V VTH
STARTUP
OR SHORT
RELEASE
VOUT1
–
OPTO
VOUT1
SHORT
VTH
OPTO
1.5V
1.2V
VREF1
0.6V
LT3804
VOPTO
GNDS1
2V
0V
3804 F03
Figure 3. Optocoupler Driver
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Output Inductor Selection
The key parameters for choosing the inductor include
inductance, RMS and saturation current ratings, and DCR.
The inductance must be selected to achieve a reasonable
value of ripple current, which is determined by:
∆IL =
VOUT • (1 – D)
f •L
Where VOUT is the output voltage, D is the duty cycle, f is
switching frequency and L is the inductance. Typically, the
inductor ripple current is designed to be 20% to 40% of the
maximum output current.
The RMS current rating must be high enough to deliver the
maximum output current. A sufficient saturation current
rating should prevent the inductor core from saturating.
These two current ratings can be determined by:
2
∆I
IRMS ≥ IO + LMAX
12
∆I
ISAT ≥ IO + LMAX
2
2
where IO is the maximum DC output current and ∆ILMAX is
the maximum peak-to-peak inductor ripple current. To
optimize the efficiency, we usually choose the inductor
with the minimum DCR if the inductance and current
ratings are the same.
Output N-Channel MOSFET Drivers
The LT3804 employs high speed N-channel MOSFET
synchronous drivers to achieve high system efficiency.
GBIAS is the 8V regulator output to bias and supply the
drivers and should be properly bypassed with a low ESR
capacitor to the ground plane. A Schottky catch diode is
required on the switch node.
Power MOSFET Selection
The LT3804 drives two external N-channel MOSFETs to
deliver high currents at high efficiency. The gate drive
voltage is typically 6.5V. The key parameters for choosing
MOSFETs include drain to source voltage rating VDSS and
RDS(ON) at 6.5V gate drive. Note that the transformer
secondary voltage waveform will overshoot at its rising
edge due to the ringing between transformer leakage
inductance and parasitic capacitance. The VDSS of both
top and bottom MOSFETs must be sufficiently higher than
the maximum overshoot. It is recommended that an RC
snubber or voltage clamping circuitry be placed across the
transformer secondary winding to limit the VS overshoot.
The RDS(ON) of the MOSFETs should be selected to deliver
the required current at the desired efficiency as well as to
meet the thermal requirement of the MOSFET package.
The conduction power losses of the MOSFETs are:
PM1 ≅ IO2 • RDS(ON)M1 • D
PM2 ≅ IO2 • RDS(ON)M2 • (1 – D)
where IO is the maximum output current of LT3804 circuit,
and RDS(ON)M1 and RDS(ON)M2 are the on-resistance for
the top and bottom MOSFETs, respectively. The RDS(ON)
must be determined with 6.5V gate drive at the expected
operating temperature. Numerous high performance power
MOSFETs are available from Siliconix, International Rectifier and Fairchild. If the VDSS and RDS(ON) ratings are the
same, the MOSFETs with the lowest gate charge QG should
be chosen to minimize the power loss associated with the
MOSFET gate drives, the switching transitions, and the
controller bias supply.
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Light Load Operation of Second Output
Design Example
If the BGS pin is grounded, the LT3804 stays in continuous
mode independent of load condition except during softstart operation (see the Soft-Start section). If the BGS pin
is left open under light load, VRS2 will drop below 8mV,
BGATE will be turned off(see comparator CA2 of Block
Diagram), and the LT3804 will enter discontinous mode
operation.
Figure 4 shows an application example of LT3804. It is a
dual output high efficiency isolated DC/DC power supply
with 36V to 72V input range, 3.3V/15A and 1.8V/15A
outputs. The basic power stage topology is a two-switch
forward converter with synchronous rectification. The
primary side controller uses an LT3781, a current mode
two-switch forward controller with built-in MOSFET drivers. On the secondary side, the LT3804 is used to provide
the voltage feedback for the 3.3V output. The output from
the built-in optocoupler driver is fed into an optocoupler
(MOC207) and then transferred to LT3781 on the primary
side to complete the 3.3V regulation. An LTC1693-1 high
speed dual N-channel MOSFET driver provides the gate
drive for the synchronous MOSFETs at the 3.3V output
stage. The LTC1693-1 driver’s input signals come from
SG and BG outputs of the LT3781 through two small gate
drive transformers (T2 and T3).
Second Output Capacitor Selection
The selection of the output capacitor is determined by the
output ripple and load transient requirements. In low
output voltage applications, always choose capacitors
with low ESR. The output ripple voltage is approximated
by:

1 
∆VOUT ≈ ∆IL  ESR +

8fC OUT 

where ∆IL is the inductor peak-to-peak ripple current. A
partial list of low ESR high performance capacitor types
includes SP capacitors from Panasonic and Cornell Dubilier,
POSCAPs and OS-CON capacitors from Sanyo, T510 and
T520 surface mount capacitors from Kemet.
Layout Considerations
For maximum efficiency, the switching rise and fall times
should be less than 20ns. To prevent radiation, the power
MOSFETs, SW pin and input bypass capacitor leads should
be kept as short as possible. A ground plane should be
used under the switching circuitry to prevent interplane
coupling and to act as a thermal spreading path. Note that
the bottom metal of the package is the heat sink as well as
the IC signal ground, and must be soldered to the ground
plane.
The LT3804 also precisely regulates the 1.8V output by
further reducing and controlling the duty cycle of the
switching waveform from the power transformer (T1)
secondary winding. In fact, the 1.8V circuit is a special
synchronous buck converter whose input is a pulsed
waveform instead of a DC voltage.
True differential remote sensing is provided for both
outputs to achieve high regulation accuracies. Power
good indicator PGOOD will be high only if both outputs are
within ±10% of their nominal values.
The LT3804 provides current limit function for both 1.8V
and 3.3V outputs. The current limits for 3.3V and 1.8V
outputs are estimated to be 50mV/R55 and 50mV/R49,
respectively.
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A planar transformer PA0191 by Pulse Engineering is
employed as the power transformer in this design. This
transformer is constructed on a PQ20 core with nine turns
of primary windings, two turns of secondary windings and
seven turns of auxiliary windings for the LT3781 bias
supply. Si7892DP MOSFETs are selected for the secondary side due to their low RDS (ON), 30V VDSS rating and
compact, thermally enhanced PowerPak SO-8 package.
The switching frequency of the circuit is about 230kHz.
1500V input to output isolation is provided. Additional
features of this design include primary side on/off control,
input over voltage protection, under voltage lockout, soft
start and board over temperature shutdown. The complete
design is mounted within a standard half brick PC board
with about half inch height.
3804i
12
C27
1µF
ON OFF
R24
270k
0.25W
C25
4.7µF
16V
VCC
R26
73.2k
1%
C28
1000pF
R43
10k
Vi
D20
B0540W
Q7
FZT853
D17
MMBD4148
VCC
D19
5241B
11V
R25
20k
SHDN
0VLO
VCC
R45
1.24k
C31
1%
1µF
1
2
13
D13
BAS21TA
C20
0.1µF
100V
19 18
R42
2.43k
C32 1%
82pF
RT1
100k
VCC
LT3781
C29
0.01µF
3
R8
10Ω
7
4
10
R17
10k
R46
330Ω
D4
BAT54F
R6
3.3Ω
C26
6.8nF
9
R37
1k
VFB
12
Q10
ZVN3310F
C14
330pF
SG
C30
0.015µF
8
C10
2200pF
250VAC
D4
BAS21TA
C1
0.01µF
15 11
14
L2, 1mH
DO1608C-105
COILCRAFT
D3
BAS21TA
R9, 0.015Ω
1%,1/2W
Q3
Si7456DP
T1
PULSE
PA0191
R29
1k
R30
1k
5VREF
R38
1k
R36
1k
D12
V
BAT54S CC
C6
4.7µF
25V
6
7
5
C17
0.1µF
C33
10nF
C15
4.7µF
16V
4
8
3
ISO1
MOC207
2
1
T2
C16
P2033 10nF
PULSE ENG.
C19
T3
0.1µF P2033
PULSE ENG.
VCCS
C22
4700pF
R35
1k
R32
6.8k
R33
6.8k
R18
100Ω
OPTO
D8
BAT54
R31
470Ω
D9
BAT54
R34
470Ω
R16
2k
0.25W
D10
10V
MMBZ5240B
R4
10Ω
1/4W
R3
10Ω
1/4W
VOUT
C9
1000pF
100V
R55
0.003Ω
1%
2512
C8
1000pF
100V
D18
B0540W
Q12
FZT690B
D6
B340A
Q4
Si7892DP
×2
L3
1.8µH
CEP125-1R8
+
LTC1693-1
6
VCC2
VCC1
7
IN1
OUT1
3
5
IN2
OUT2
2
4
GND1
GND2
1
8
VCCS
VO 1
C4
470µF
4V
POSCAP
×3
(4TPD470M ×3)
Q6
Si7892DP
×2
C21
1µF
16V
C13
4.7µF
25V
Figure 4. 36V – 72VDC to 3.3V/15A and 1.8V/15A Dual Output Isolated Power Supply (Page 1 of 2)
R39
52.3k
1%
6
5
5VREF
20
VBST
5VREF
Vi
THERM
–VIN
TG
FSET
D1
B2100
BG
SYNC
D1
B2100
SENSE
SS
C2
1.5µF
100V
×2
BSTREF
Q1
Si7456DP
PGND
L1
1.2µH
DO1813P-122HC
VC
SGND
LT3804 TA02
VO RTN
VO 1
3.3V
AT 15A
CLIN
CLIP
SEC
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APPLICATIO S I FOR ATIO
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36V
TO 72V
LT3804
3804i
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LT3804
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APPLICATIO S I FOR ATIO
SEC
FROM TRANSFORMER
SECONDARY WINDING
VCCS
C45
10pF
R57
10k
C47
1µF
VCCS
OPTO
R5
100k
PGOOD
23
19
16
7
C37, 680pF
CLIP
C49, 1000pF
CLIN
1
2
22
R13
1.5k
C50
1000pF 18
13
R65
10Ω
C51
R19 6.8nF
1k
VO1
C24
4.7nF
VO1S+
3.3V OUTPUT
REMOTE SENSE
VO1S–
R14
3.01k
1%
R15
3.01k
1%
R66
665Ω
1%
R67
665Ω
1%
10
28
8
25
SYNC
VCC
OPTO
D14
4 CMDSH-3
BOOST
GBAIS
LT3804
PGOOD
TGATE
BGS
SW
CSET
BGATE
CLIP
CL2P
C36 C44
4.7µF 0.1µF
16V 16V
D15
CMDSH-3
(2R5TPD680M ×3)
27
Q13
Si7892DP
L4
1.8µH
CEP125-1R8
5
6
R49
0.003Ω
1%
R64
10Ω
26
20
Q14
Si7892DP
×2
21
CLIN
CL2N
VAOUT1
VAOUT2
15
C39
330pF
14
VFB1
VFB2
GNDS1
GNDS2
PGIN1
PGIN2
ILCOMP1
ILCOMP2
R58 SS1 PGND
10k
17
24
C35
180pF
+VO2
1.8V
15A
C12
+
680µF
2.5V
POSCAP
×3
12
R50
3.3k
C38
0.033µF
C46
1000pF
11
3
SS2
9
C43
0.1µF
R12
10k
C48
180pF
R53
220Ω
C42
4700pF
VO2S+
R54
3.01k
1%
R62
3.01k
1%
R60
1.5k
1%
R61
1.5k
1%
R68
10Ω
1.8V OUTPUT
REMOTE SENSE
VO2S–
R63
10Ω
3804 TA01
Figure 4. 36V – 72VDC to 3.3V/15A and 1.8V/15A Dual Output Isolated Power Supply (Page 2 of 2)
3804i
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LT3804
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PACKAGE DESCRIPTIO
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
2.74 6.40
(.108) BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.09 – 0.20
(.0036 – .0079)
0.45 – 0.75
(.018 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP 0203
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3804i
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LT3804
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1339
High Power Synchronous DC/DC Controller
Operation Up to 60V Maximum
LT1425
Isolated Flyback Switching Regulator
General Purpose with External Application Resistor
LT1431
Programmable Reference
0.4% Initial Voltage Tolerance
LT1680
High Power DC/DC Step-Up Controller
Operation Up to 60V Maximum
LT1725
General Purpose Isolated Flyback Controller
Drives External Power MOSFET with External ISENSE Resistor
LT1737
High Power Isolated Flyback Controller
Sense Output Voltage Directly from Primary-Side Winding
LT1950
PWM Controller for Forward, Flyback,
Boost and SEPIC
3V ≤ VIN ≤ 25V, Volt-Second Clamp, Leading-Edge Blanking,
Slope Compensation
LT3710
Secondary Side Synchronous Post Regulator
Generates Regulated Auxiliary Output in Isolated DC/DC Converters,
Dual N-Channel MOSFET Synchronous Drivers
LTC3722
Synchronous Phase Modulated Full-Bridge Controller
Adaptive or Manual Delay Control for Zero Voltage Switching,
Adjustable Maximum ZVS Delay, Current Mode and Voltage Mode.
LT3781
Dual Transistor Synchronous Forward Controller
Operation Up to 72V Maximum
3804i
16
Linear Technology Corporation
LT/TP 0603 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2003