9 EM MICROELECTRONIC - MARIN SA AppNote 28 Application Note 28 Title: How to use EM6x80 in Smart Power Mgmt Applications Product Family: 4-bit Microcontroller Part Number: Keywords: Date: EM6x80 4-bit microcontroller February 25, 2005 Introduction: One of the multitude of applications for which the EM6x80 is eminently suited is as an intelligent power supply supervisor and power manager for another larger micro-controller. For this type of application the EM6x80 provides a one-component solution for power supply monitoring and management for the complete application. Schematic example: V DD SVLD VDD External event PA5 PA0 16/32 bit MCU or DSP PA1 SCR ADC PA4 PA2 PA3 EM6x80 SPI Vreg VSS I/O’s port V SS Application description: During standard operation the EM6x80 is used as a voltage supervisor by using the SVLD function in continuous mode. When the voltage level falls below the minimum defined level the EM6x80 sends a sleep command to the application microcontroller. As soon as the voltage level recovers and becomes higher than the minimum defined level, the EM6x80 sends a wake-up command to restart the system. For applications where the activity is not continuous it is possible to put the application micro-controller and the EM6x80 in sleep mode for maximum power savings. As soon as activity is detected on the pin the EM6x80 is reactivated. Before activating the full system, the EM6x80 tests the system voltage and waits until it returns to an acceptable value if necessary. In this application we are using the standard serial bus for communication, but it is also possible to use a Manchester protocol or only 1 wire of the serial port leaving the other pins free for other uses. The Sleep Counter Reset (SCR) is an EM patented feature available on the EM6x80, which can be used to save power when the battery supply is weak. The SCR enables a periodic wake-up of the EM6x80 even though it is in Sleep Mode and all the clocks are stopped. The SCR allows, for example, automatic turn-on of an application along with absolute minimum power consumption. When activated, the SCR provides a delay, which is programmable from 14ms to 8.14 seconds after which the EM6x80 is automatically reset. It is possible to determine if the reset was a power-on reset or a sleep counter reset by examination of the sleep bit in register RegSysCntl2. In this application if the reset comes from the sleep counter, the SVLD is used to determine if the supply voltage level is now above the minimum defined level (for example 2V) before restarting the full system. Copyright © 2005, EM Microelectronic-Marin SA 1 www.emmicroelectronic.com AppNote 28 Software flowchart: EM6x80 supervisor Coming from SCR sequence Reset Yes Check SVLD level MAX init Check actual sensor pos. Yes No SCR Mode Check actual sensor pos. Update application status Send wake-up sequence Disable external IRQ actif Check actual mode 0AH Sleep/Pon Check actual mode 05H Sleep Pon Check SVLD upper than 2v Upper Check lowest SVLD level Lower Check actual sensor pos. Upper Update application status Send wake sequence Send wake-up sequence Disable external IRQ Enable IRQ Ext / svld Start SVLD 1.25V Countinuous mode standby Disable IRQ Ext / svld Copyright © 2005, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com AppNote 28 Handler Supervisor Disable SVLD IRQ STOP SVLD Save IRQ1/ 2 Clear IRQ1/2 SVLD IRQ No Yes External IRQ Yes Send Sleep sequence Go SCR Mode No Lower Check SVLD level Upper Send Sleep sequence enable external IRQ Check actual sensor pos. Send wake-up sequence Disable external IRQ RTI Copyright © 2005, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com AppNote 28 Software Code: ;--------------------------------------------------------------------------------------------INCLUDE V6680REG.ASM ;--------------------------------------------------------------------------------------------ORG 0 JMP MAIN ;--------------------------------------------------------------------------------------------; Variables ;--------------------------------------------------------------------------------------------INCLUDE 6680_RAM_MAP.asm ;--------------------------------------------------------------------------------------------; Interrupt Handler: ;--------------------------------------------------------------------------------------------Handler: STA STACK0 ; Save ACCU LDI 0DH AND RegIRQMask2 STA RegIRQMask2 ; disable SVLD IRQ STI RegVLDCntl, 01H ; Disable SVLD countinuous mode LDR RegIRQ1 ; Save IRQ flags STA V_IRQ_1 ; Save IRQ flags LDR RegIRQ2 ; Save IRQ flags STA V_IRQ_2 ; Save IRQ flags SVLD_Check: LDI 02H XOR V_IRQ_2 JPNZ External_IRQ STI RegPACntl3, 0CH STI RegPACntl4, 02H STI RegPA0OE, 06H ; Set PA2,1 as output STI RegSCntl1, 0CH ; master Mode LDR V_ADC_LEVEL STA RegSDataL STI RegSDataH, 05H ; Sleep CMD STI RegIRQMask2,00H ; disable SPI IRQ STI RegSysCNTL1, 09H ; Enable General IRQ and Remove Test Mode STI RegSCntl2, 08H ; Start SPI interface in slave mode NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP STI RegSysCntl2,04H ;Enable sleep mode LDI 03H OR RegSleepCR STA RegSleepCR ; Select maximum length of sleep time STI RegSysCntl1, 05H ; Go in Sleep External_IRQ: SHRR V_IRQ_1 JPC SVLD_TEST_HANDLER HandEnd: LDR RTI STACK0 Copyright © 2005, EM Microelectronic-Marin SA ; reload ACCU 4 www.emmicroelectronic.com AppNote 28 SVLD_TEST_HANDLER: STI RegSVLDLev, 04H ; SELECT 1.40V SVLD level Start_SVLD_HANDLER: STI RegVLDCNTL, 04H ; Start one SVLD mesure check_busy_bit_SVLD_HANDLER: NOP LDI 04H AND RegVldCntl JPNZ check_busy_bit_SVLD_HANDLER SHLR RegVldCntl JPC SVLD_UPPER_HANDLER SVLD_LOWER_HANDLER: STI V_Master_CMD, 00H STI RegPACntl3, 0CH STI RegPACntl4, 02H STI RegPA0OE, 06H ; Set PA2,1 as output STI RegSCntl1, 0CH ; master Mode LDR V_ADC_LEVEL STA RegSDataL STI RegSDataH, 05H ; Sleep CMD is 05H STI RegIRQMask2,00H ; enable SPI IRQ STI RegSysCNTL1, 09H ; Enable General IRQ and Remove Test Mode STI RegSCntl2, 08H ; Start SPI interface in slave mode NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP JMP HandEnd SVLD_UPPER_HANDLER: STI RegSleepCR, 08H ; Remove Pull on PA4 pin STI RegSVLDLev, 0FH ; SELECT UPPER ADC level Start_ADC_HANDLER: STI RegVLDCNTL, 0DH ; Start ADC mesure on PA4 check_busy_bit_HANDLER: NOP LDI 04H AND RegVldCntl JPNZ check_busy_bit_HANDLER End_ADC_measure_HANDLER: LDI 08H AND RegVldCntl JPNZ END_ADC_HANDLER DEC_ADC_LEVEL_HANDLER: DEC RegSVLDLev JPZ SCR_mode STA RegSVLDLEV JMP Start_ADC_HANDLER END_ADC_HANDLER: LDR RegSVLDLev STA V_ADC_LEVEL STI V_Master_CMD, 00H STI RegPACntl3, 0CH STI RegPACntl4, 02H Copyright © 2005, EM Microelectronic-Marin SA ;information for the master MCU 5 www.emmicroelectronic.com AppNote 28 STI STI LDR STA STI STI STI STI NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP JMP RegPA0OE, 06H RegSCntl1, 0CH V_ADC_LEVEL RegSDataL RegSDataH, 0AH RegIRQMask2,00H RegSysCNTL1, 09H RegSCntl2, 08H HandEnd LDI AND JPNZ 04H RegSysCntl2 SCR_return ; Set PA2,1 as output ; master Mode ; Wake-up CMD is 0AH ; enable SPI IRQ ; Enable General IRQ and Remove Test Mode ; Start SPI interface in slave mode MAIN: init: STI RegPACntl3, 00H STI RegPACntl4, 00H ADC_measure: STI RegSleepCR, 08H STI RegSVLDLev, 0FH Start_ADC: STI RegVLDCNTL, 0DH check_busy_bit: NOP LDI 04H AND RegVldCntl JPNZ check_busy_bit End_ADC_measure: LDI 08H AND RegVldCntl JPNZ END_ADC DEC_ADC_LEVEL: DEC RegSVLDLev JPZ SCR_mode STA RegSVLDLEV JMP Start_ADC END_ADC: LDR RegSVLDLev STA V_ADC_LEVEL STI RegPACntl3, 0CH STI RegPACntl4, 02H STI RegPA0OE, 06H STI RegSCntl1, 0CH LDR V_ADC_LEVEL STA RegSDataL STI RegSDataH,00H LDI 01H OR RegIRQMask2 Copyright © 2005, EM Microelectronic-Marin SA ; Remove Pull on PA4 pin ; SELECT UPPER ADC level ; Start ADC mesure on PA4 ;information for the master MCU ; Set PA2,1 as output ; master Mode ; check CMD only 6 www.emmicroelectronic.com AppNote 28 STA RegIRQMask2 ; enable SPI IRQ STI RegSysCNTL1, 09H ; Enable General IRQ and Remove Test Mode STI RegSCntl2, 08H ; Start SPI interface in slave mode halt Test_Actual_mode: LDI 0AH XOR RegSDataH JPZ Standby PON: SVLD_measure: STI RegSVLDLev, 0AH ; SELECT 2V SVLD level Start_SVLD: STI RegVLDCNTL, 05H ; Start one SVLD mesure check_busy_bit_SVLD: NOP LDI 04H AND RegVldCntl JPNZ check_busy_bit_SVLD End_SVLD_measure: LDI 08H AND RegVldCntl JPNZ Send_Wake_up Ckeck_lowest_SVLD: STI RegSVLDLev, 05H ; SELECT 1.25V SVLD level Start_SVLD_lower: STI RegVLDCNTL, 05H ; Start one SVLD mesure check_busy_bit_SVLD_lowest: NOP LDI 04H AND RegVldCntl JPNZ check_busy_bit_SVLD_lowest End_SVLD_Lowest_measure: LDI 08H AND RegVldCntl JPNZ SCR_MODE Call Sleep_sequence Standby: Enable_IRQ: STI STI STI STI STI Halt STI STI STI JMP SCR_mode: STI STI STI STI LDR STA STI LDI OR STA STI STI halt STI LDI RegIRQMask2, 02H RegPACntl2, 01H RegIRQMask1, 01H RegSVLDLev, 05H RegVLDCntl, 07H RegVLDCntl, 00H RegIRQMask2, 00H RegIRQMask1, 00H Test_Actual_mode RegPACntl3, 0CH RegPACntl4, 02H RegPA0OE, 06H RegSCntl1, 0CH V_ADC_LEVEL RegSDataL RegSDataH, 05H 01H RegIRQMask2 RegIRQMask2 RegSysCNTL1, 09H RegSCntl2, 08H RegSysCntl2,04H 03H Copyright © 2005, EM Microelectronic-Marin SA ; Enable SVLD IRQ ; Enable PA5 IRQ for External Event ; SELECT 1.25V SVLD level ; Enable SVLD countinuous mode ; Disable SVLD countinuous mode ; Disable SVLD IRQ ; Disable PA5 IRQ for External Event ; Set PA2,1 as output ; master Mode ; Sleep CMD ; enable SPI IRQ ; Enable General IRQ and Remove Test Mode ; Start SPI interface in slave mode ;Enable sleep mode 7 www.emmicroelectronic.com AppNote 28 OR STA STI Send_Wake_up: STI STI STI STI STI LDR STA STI LDI OR STA STI STI halt JMP RegSleepCR RegSleepCR RegSysCntl1, 05H V_Master_CMD, 00H RegPACntl3, 0CH RegPACntl4, 02H RegPA0OE, 06H RegSCntl1, 0CH V_ADC_LEVEL RegSDataL RegSDataH, 0AH 01H RegIRQMask2 RegIRQMask2 RegSysCNTL1, 09H RegSCntl2, 08H ; Select maximum length of sleep time ; Go in Sleep ; Set PA2,1 as output ; master Mode ; Wake-up CMD is 0AH ; enable SPI IRQ ; Enable General IRQ and Remove Test Mode ; Start SPI interface in slave mode Standby Sleep_sequence: STI V_Master_CMD, 00H STI RegPACntl3, 0CH STI RegPACntl4, 02H STI RegPA0OE, 06H STI RegSCntl1, 0CH LDR V_ADC_LEVEL STA RegSDataL STI RegSDataH, 05H LDI 01H OR RegIRQMask2 STA RegIRQMask2 STI RegSysCNTL1, 09H STI RegSCntl2, 08H halt RET Wake_up_sequence: STI V_Master_CMD, 00H STI RegPACntl3, 0CH STI RegPACntl4, 02H STI RegPA0OE, 06H STI RegSCntl1, 0CH LDR V_ADC_LEVEL STA RegSDataL STI RegSDataH, 0AH LDI 01H OR RegIRQMask2 STA RegIRQMask2 STI RegSysCNTL1, 09H STI RegSCntl2, 08H halt STI RegIRQMask2,00H ; Set PA2,1 as output ; master Mode ; Sleep CMD is 05H ; enable SPI IRQ ; Enable General IRQ and Remove Test Mode ; Start SPI interface in slave mode ; Set PA2,1 as output ; master Mode ; Wake-up CMD is 0AH ; enable SPI IRQ ; Enable General IRQ and Remove Test Mode ; Start SPI interface in slave mode RET SCR_return: STI RegSVLDLev, 0FH Start_SVLD_max: STI RegVLDCNTL, 05H check_busy_bit_max: NOP LDI 04H AND RegVldCntl JPNZ check_busy_bit_max Copyright © 2005, EM Microelectronic-Marin SA ; SELECT 2.75V SVLD level maximum ; Start one SVLD mesure 8 www.emmicroelectronic.com AppNote 28 End_SVLD_max_measure: LDI 08H AND RegVldCntl JPNZ Active_mode JMP SCR_mode Active_mode: STI RegSleepCR, 08H STI RegSVLDLev, 0FH Start_ADC_SCR: STI RegVLDCNTL, 0DH check_busy_bit_SCR: NOP LDI 04H AND RegVldCntl JPNZ check_busy_bit_SCR End_ADC_measure_SCR: LDI 08H AND RegVldCntl JPNZ END_ADC_SCR DEC_ADC_LEVEL_SCR: DEC RegSVLDLev JPZ SCR_mode STA RegSVLDLEV JMP Start_ADC_SCR END_ADC_SCR: LDR RegSVLDLev STA V_ADC_LEVEL STI RegVLDCNTL, 01H CALL Wake_up_sequence JMP Standby ; Remove Pull on PA4 pin ; SELECT UPPER ADC level ; Start ADC mesure on PA4 ;information for the master MCU ; Stop ADC mesure on PA4 Include File V6680REG.ASM : ;--------------------------------------------------------------------------------------------; EM6680 RAM Map File definition ; 28/01/05 ; Main Program AN28.asm ; All RAM address are define on this file. ;--------------------------------------------------------------------------------------------Stack0 EQU 00H ADDR EQU 01H ; selection value on all program V_SVLD_LEVEL EQU 02H V_ADC_LEVEL EQU 03H ; Used to send the ADC value to the master V_Master_CMD EQU 04H ; Used to send commande to the master V_IRQ_1 V_IRQ_2 EQU 1BH EQU ; Used in 6680_2.asm 1CH ; Used in 6680_2.asm © EM Microelectronic-Marin SA, 03/05, Rev. A Copyright © 2005, EM Microelectronic-Marin SA 9 www.emmicroelectronic.com