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EM MICROELECTRONIC - MARIN SA
EM6580
Ultra Low Power 8-pin Flash Microcontroller
Features
True Low Power:
5.8 µA active mode
3.3 µA standby mode
0.32 µA sleep mode
Large Supply Voltage 2.0 V to 5.5 V
No external component needed
Available in SO-8/14 packages and die
4-bit ADC or 12 levels Supply Voltage Level
Detector (SVLD)
Unique ID code of 52bits + 16bits CRC
Max 4 (5*) outputs with 2 high drive outputs of 10mA
Max. 5 (6*) inputs
Sleep Counter Reset (automatic wake-up from sleep
mode (EM patent))
Flash memory 4096 × 16 bits
RAM 80 × 4 bits
Internal RC oscillator 32kHz – 800kHz
2 clocks per instruction cycle
72 basic instructions
External CPU clock source possible
Watchdog timer (2 sec)
Power-On-Reset with Power-Check on start-up
3 wire serial port , 8 bit, master and slave mode
Universal 10-bit counter, PWM, event counter
Prescaler down to 1 Hz (freq. = 32kHz)
Frequency output 1Hz, 2048 Hz, CPUClk, PWM
6 internal interrupt sources ( 2×10-bit counter, 2×
prescaler, SVLD, Serial Interface)
2 external interrupt sources (port A)
Figure 1. Architecture
Flash
4096 x 16Bit
V DD
RAM
80 x 4Bit
V REG/V PP
Power Supply
Voltage reg.
Stable
RC oscillator
32 - 800kHz
Power on
Reset
Prescaler
Sleep Counter
Reset
Core
EM6600
10-Bit Univ
Count/Timer
Watchdog
4-bit ADC
SVLD check
Interrupt
Controller
Port A
Serial Interface
PA0
PA1
Reset
PA2
PA3
PA4
PA1 & PA2:
high current
drive outputs
*PA5
* PA5 available only
in 14-pin package
and in die
Figure 2. Pin Configuration
SO-8
PA0
1
8
V DD
PA1
2
7
V REG /V PP
PA2
3
6
PA4
PA3
4
5
V SS
NC
EM6580
Description
The EM6580 is a low power Flash 4-bit microcontroller
coming in a small 8-pin SO package and working up to
0.4 MIPS. It comes with an integrated 4-bit ADC and 2
high current drive outputs of 10mA and it requires no
external component. It has a sleep counter reset allowing
automatic wake-up from sleep mode. It is designed for use
in battery-operated and field-powered applications
requiring an extended lifetime. A high integration level
make it an ideal choice for cost sensitive applications.
The EM6580 contains the equivalent of 8kB of Flash
memory and a RC oscillator with frequencies between 32
to 800kHz. It also has a power-on reset, watchdog timer,
10 bit up/down counter, PWM and several clock
functions.
Development tools include windows-based simulator
program debugger, assembler and real time emulator.
Copyright © 2005, EM Microelectronic-Marin SA
SO-14
NC
1
14
PA0
2
13
V DD
PA1
3
12
V REG/V PP
PA2
4
11
PA5
PA3
5
10
NC
6
9
V SS
NC
7
8
NC
EM6580
PA4
Typical Applications
1
Household appliances
Safety and security devices
Automotive controls
Sensor interfaces
Watchdog
Intelligent ADC
Driver (LED, triac)
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EM6580
EM6580 at a glance
Power Supply
- Low voltage low power architecture
including internal voltage regulator
- 2.0V to 5.5V supply voltage
- 5.8 µA in active mode
- 3.3 µA in standby mode
- 0.32 µA in sleep mode
RAM
- 80 x 4 bit, directly addressable
FLASH
- 4096 x 16 bit (8k Byte),
CPU
- 4-bit RISC architecture
- 2 clock cycles per instruction (CPI=2)
- 72 basic instructions
Main Operating Modes and Resets
- Active mode (CPU is running)
- Standby mode (CPU in halt, peripherals running)
- Sleep mode (no clock, data kept)
- Initial Power-On-Reset with Power-Check
- Watchdog reset (logic)
- Reset terminal (software option on PA[3/4])
- Sleep Counter reset from Sleep mode
- Wakeup on change from Sleep mode
Prescaler
- Divider (4 stages) to best fit CPU clock (32kHz – 1MHz
to 32kHz system clock to keep peripherals timing close
to specification
- 15 stage system clock divider from 32kHz down to 1Hz
- 2 Interrupt requests (3 different frequencies)
- Prescaler reset (4kHz to 1Hz)
8-Bit Serial Interface
- 3 wire (Clock, DataIn , DataOut) master/slave mode
- READY output during data transfer
- Maximum shift clock is equal to the main system clock
- Interrupt request to the CPU after 8 bit data transfer
- Supports different serial formats
- pins shared with general 4 bit PA[3:0] I/O port
Oscillator
- RC Oscillator range: 32kHz up to 800kHz
- No external components are necessary
- Temperature compensated
- External clock source possible from PA[1]
4(5)-Bit I/O PA[3:0] & PA[4] / PA[5]*
- Direct input read on the port terminals
- 2 debounced function available muxed on 4 inputs
- 2 Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by register
- 2 Test variables (software) for conditional jumps
- PA[1] and PA[3/4] are inputs for the event counter
- PA[3/4] Reset input (register selectable)
- All outputs can be put tri-state (default)
- Selectable pull-downs in input mode
- CMOS or Nch. open drain outputs
- Weak pull-up selectable in Nch. open drain
mode
4-bit ADC & Voltage Level Det. (SVLD)
- External voltage compare from PA[4] input possible (low
resolution 4 bit AD converter)
-7 different levels from 2 V to 3.0 V for SVLD
- Used for Power Check after POR (2.0V check)
- Busy flag during measure
- Interrupt generated if SVLD measurement low
10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting
- Parallel load
- Event counting (PA[1] or PA[3/4])
- 8 different input clocks
- Full 10 bit or limited (8, 6, 4 bit) compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[1] and PA[3/4] or CPUClk
- Pulse width modulation (PWM) output
Interrupt Controller
- 2 external and 6 internal interrupt request sources
- Each interrupt request can individually be masked
- Each interrupt flag can individually be reset
- Automatic reset of each interrupt request after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request flag
when going into HALT mode
Sleep Counter Reset (SCR)
- wake up the EM6580 from sleep mode
- 4 timings selectable by register
- Inhibit SCR by register
Package form available
- SO-8/14
- Die form (9 pin possible due to additional I/O pin)
NB: All frequencies written in this document are related to a typical system clock of 32 kHz !
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EM6580
Table of Contents
FEATURES______________________________ 1
1H
DESCRIPTION ___________________________ 1
2H
8.4.2
PWM Characteristics__________________ 31
49H
8.5
COUNTER SETUP _____________________ 31
8.6
10-BIT COUNTER REGISTERS ____________ 32
9.
SUPPLY VOLTAGE LEVEL DETECTOR /
4-BIT ADC ______________________________ 34
50H
51H
EM6580 AT A GLANCE ____________________ 2
3H
1.
PIN DESCRIPTION FOR EM6580 _______ 4
4H
2.
2.1
2.2
2.3
3.
OPERATING MODES ________________
ACTIVE MODE_______________________
STANDBY (HALT) MODE _______________
SLEEP MODE _______________________
POWER SUPPLY____________________
4.
4.1
4.2
4.3
4.4
4.5
4.6
5.
5.1
5.2
5.3
6.
6.1
6.2
RESET ____________________________ 8
POR WITH POWER-CHECK RESET _________ 9
INPUT PORT A RESET _________________ 10
DIGITAL WATCHDOG TIMER RESET _______ 10
SLEEP COUNTER RESET _______________ 11
WAKE-UP ON CHANGE ________________ 11
THE CPU STATE AFTER RESET __________ 11
OSCILLATOR AND PRESCALER _____ 12
RC OSCILLATOR OR EXTERNAL CLOCK_____ 12
SPECIAL 4 STAGE FREQUENCY DIVIDER ____ 13
PRESCALER ________________________ 13
INPUT AND OUTPUT PORT A ________ 15
INPUT / OUTPUT PORT OVERVIEW ________ 15
PORTA AS INPUT AND ITS MULTIPLEXING ___ 16
6.4
7.
7.1
7.2
8H
9H
12H
13H
14H
15H
16H
17H
18H
19H
20H
21H
2H
23H
Debouncer __________________________16
IRQ on Port A _______________________17
Pull-up/down ________________________17
Software test variables ________________18
Port A for 10-Bit Counter _______________18
Port A Wake-Up on change_____________18
Port A for Serial Interface ______________18
Port A for External Reset_______________18
Port PA[4] as Comparator Input _________18
Reset and Sleep on Port A _____________18
Port A Blocked Inputs _________________18
25H
26H
27H
28H
29H
30H
31H
32H
3H
34H
35H
CMOS / Nch. Open Drain Output ________19
36H
PORT A REGISTERS___________________
SERIAL PORT _____________________
GENERAL FUNCTIONAL DESCRIPTION ______
DETAILED FUNCTIONAL DESCRIPTION______
20
22
23
23
37H
38H
39H
40H
Output Modes _______________________24
41H
SERIAL INTERFACE REGISTERS __________ 26
10-BIT COUNTER __________________ 27
FULL AND LIMITED BIT COUNTING ________ 27
FREQUENCY SELECT AND UP/DOWN COUNTING28
EVENT COUNTING ____________________ 29
PULSE WIDTH MODULATION (PWM) ______ 29
8.4.1
11.
RAM _____________________________ 37
12.
12.1
13.
INTERRUPT CONTROLLER __________ 38
INTERRUPT CONTROL REGISTERS _________ 39
PERIPHERAL MEMORY MAP _________ 40
14.
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
15.
15.1
15.2
16.
MASK OPTIONS ____________________ 43
PORT A METAL OPTIONS _______________ 43
RC OSCILLATOR FREQUENCY OPTION ______ 43
DEBOUNCER FREQUENCY OPTION ________ 44
POWER-CHECK LEVEL OPTION ___________ 44
ADC/SVLD VOLTAGE LEVEL #15 _________ 44
COUNTER UPDATE OPTION ______________ 44
VOLTAGE REGULATOR LEVEL OPTION ______ 44
ADDITIONAL REGISTERS COMPARE TO EM668045
RC OSCILLATOR ___________________ 46
FREQUENCY SELECTION ________________ 46
OSCILLATOR TRIMMING ________________ 47
UNIQUE ID CODE / SERIAL NUMBER __ 48
54H
5H
56H
57H
58H
59H
60H
61H
62H
63H
64H
65H
6H
67H
68H
69H
70H
24H
PORTA AS OUTPUT AND ITS MULTIPLEXING _ 19
7.2.1
7.3
8.
8.1
8.2
8.3
8.4
7H
1H
6.3.1
53H
6H
10H
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.3
5
5
5
5
7
5H
52H
10.
ADC/SVLD COMPARATOR
CHARACTERISTICS ______________________ 37
42H
43H
4H
45H
46H
47H
17.
TEMPERATURE AND VOLTAGE
BEHAVIOUR ____________________________ 49
17.1 IDD CURRENT (TYPICAL) _______________ 49
17.2 PULL-UP AND PULL-DOWN RESISTORS
(TYPICAL) __________________________ 50
17.3 OUTPUT CURRENT (TYPICAL) ____________ 50
17.4 OSCILLATOR FREQUENCY (TYPICAL) _______ 51
18.
ELECTRICAL SPECIFICATION ________ 52
18.1 ABSOLUTE MAXIMUM RATINGS ___________ 52
18.2 HANDLING PROCEDURES _______________ 52
18.3 STANDARD OPERATING CONDITIONS _______ 52
18.4 DC CHARACTERISTICS - POWER SUPPLY ___ 52
18.5 SUPPLY VOLTAGE LEVEL DETECTOR _______ 53
18.6 DC CHARACTERISTICS - I/O PINS _________ 53
18.7 RC OSCILLATOR FREQUENCY ____________ 54
18.8 SLEEP COUNTER RESET - SCR __________ 54
19.
PAD LOCATION DIAGRAM ___________ 55
71H
72H
73H
74H
75H
76H
7H
78H
79H
80H
81H
82H
83H
84H
85H
20.
20.1
21.
21.1
PACKAGE DIMENSIONS _____________ 55
SO-8/14 ___________________________ 55
ORDERING INFORMATION ___________ 56
PACKAGE MARKING ___________________ 56
86H
87H
8H
89H
How the PWM Generator works. _________30
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48H
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EM6580
1. Pin Description for EM6580
Table 1 EM6580 pin descriptions
# On
Chip
1
2
3
4
5
6
7*
8
9
SO-8
1
2
3
4
5
6
NC
7
Signal
Name
PA0
PA1
PA2
PA3
Vss
PA4
PA5
VREG
8
Description
general I/O, serial In, Wake-Up on Change, IRQ source,…
general I/O, serial CLK, timer source, external clock
general I/O, serial Out, freq., CPU reset status output,…
general I/O, serial Rdy/Cs, Interrupt source, reset
ground – negative supply pin
general I, Reset, timer source, Interrupt source, Wake-Up, Compare I
general I/O, Wake-Up on Change, IRQ source
regulated voltage supported by 470nF tw. Vss
High Voltage pin for Flash programming
positive supply pin – capacitance tw. VDD (C depends on VDD noise)
VDD
Figure 3. Typical configuration for Vdd > 2.0V
Vdd
VDD
100 Ohm
Voltage
regulator
Vbat
SVLD
4-bit ADC
C
I/O pad
Level Shifter
VPP
R
uPUS 4bits core
Digital peripherals
RAM 64 x 4 bits
ROM 1536 x 16 bits
Analog peripherals
RC oscillator
Power-on-Reset
Sleep Reset Cnt
Vreg
Capacitor
470nF
C
VSS
On I/O pins there are protective diodes towards VDD and VSS.
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EM6580
2. Operating modes
The EM6580 can operate in three different modes of which 2 are low-power dissipation modes (Stand-By and
Sleep). The modes and transitions between them are shown in Figure 5.
1.) Active mode
2.) Stand-By mode
3.) Sleep mode
Figure 4. EM6580 operating mode transitions
POWER-ON
START-UP
Power-On-Reset & Power Check Level, ~2.0V
POR static level
Power-Check Active
RC oscilator
running
PORwPC
8 oscillator
periods
PORwPC
RESET
PORwPC
resetPortA
WDreset
reset synchronizer
clocks active
PORwPC
8 CPU clock
periods
Reset-pad
WDreset
ACTIVE
or running
mode
HALT instruction
interrupt/event
SleepResCnt
WakeUp on
Change
STAND-BY
or HALT
mode
Clocks active
SLEEP
Everything stopped
Registers and
RAM keep their value
Sleep bit set
2.1 ACTIVE Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Leaving the active mode: via the halt instruction to go into standby mode, writing the SLEEP bit to go
into Sleep mode or detecting the reset to go into reset mode.
2.2 STANDBY (Halt) Mode
Executing a HALT instruction puts the EM6580 into standby mode. The voltage regulator, oscillator, watchdog
timer, interrupts, timers and counters are operating. However, the CPU stops since the clock related to
instruction execution stops. Registers, RAM and I/O pins retain their states prior to STANDBY mode.
STANDBY is cancelled by a RESET or an Interrupt request if enabled.
2.3 SLEEP Mode
Writing to the Sleep bit in the RegSysCntl1 register puts the EM6580 in sleep mode. The oscillator stops and
most functions of the EM6580 are inactive. To be able to write to the Sleep bit, the SleepEn bit in
RegSysCntl2 must first be set to "1". In SLEEP mode only the voltage regulator is active to maintain the RAM
data integrity, the peripheral functions are stopped and the CPU is reset.all other functions are in reset state.
SLEEP mode may be cancelled by Wake/Up on change, external reset or by Sleep Reset Counter if any of
them is enabled.
Waking up from sleep mode may takes some time to guarantee stable oscillation. Coming back from sleep
mode puts the EM6681 in reset state and as such reinitializes all registers to their reset value. During sleep
mode and the following start up the EM6580 is in reset state. Waking up from sleep mode clears the Sleep flag
but not the SleepEn bit. Inspecting the SleepEn allows to determine if the EM6580 was powered up (SleepEn
= "0") or woken from sleep mode (SleepEn = "1").
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EM6580
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EM6580
Table 2.3.1 Shows the Status of different EM6580 blocks in these three main operating modes.
Peripheral /// EM6580 mode ACTIVE mode
STAND-BY mode
SLEEP mode
POR (static)
On
On
On
Voltage regulator
On
On
On (Low-Power)
RC-oscillator
On
On
Off
Clocks (Prescaler & RC divider) On
On
Off
CPU
Running
In HALT – Stopped
Stopped
Peripheral register
“On”
“On” retain value
retain value
RAM
“On”
retain value
retain value
Timer/Counter
“On”
“On” if activated before stopped
Supply Voltage Level Det.=SVLD can be activated
can not be activated
Off
PortA / Reset pad debounced
Yes
Yes
No
Interrupts / events
Yes - possible
Yes - possible
No – not possible
Watch-Dog timer
On / Off (soft
On / Off (soft
No
selectable)
selectable)
Wake Up on Change PortA
No
No
On/Off (soft select.)
Sleep Reset Counter
Off
Off
On/Off (soft select.)
3. Power Supply
The EM6580 is supplied by a single external power supply between VDD (VBAT) and VSS (ground). A built-in
voltage regulator generates VREG providing regulated voltage for the oscillator and the internal logic. The
output drivers are supplied directly from the external supply VDD. Internal power configuration is shown in
Figure 3.
The internal voltage regulator is chosen for high voltage systems. It saves power by reducing the internal core
logic’s power supply to an optimum value. However, due to the inherent voltage drop over the regulator the
minimal VDD value is restricted to 2.0V .
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EM6580
4. Reset
Figure 6. illustrates the reset structure of the EM6580. One can see that there are five possible reset sources :
(1) Internal initial Power On Reset (POR) circuitry with Power-Check.Æ POR, ResetCold, System Reset, Reset CPU
(2) External reset from PA[3/4] if software enabled
Æ System Reset, Reset CPU
(3) Internal reset from the Digital Watchdog.
Æ System Reset, Reset CPU
(4) Internal reset from the Sleep Counter Reset.
Æ System Reset, Reset CPU
(5) Wake-Up on change from PA[0/5] or PA[3/4] if software enabled. Æ System Reset, Reset CPU
Table 4.1 Reset sources that can be used in different Operating modes
Reset Sources
ACTIVE mode
STAND-BY mode
POR (static) with Power Check
Yes
Yes
Software enabled reset on PA[3/4]
XS dig. debounced
XS dig. debounced
Digital Watch-Dog Timer
XS
XS
Sleep Counter Reset
No
No
Wake Up on Change from Sleep
No
No
Going in Sleep mode
Yes
No
XS = software enable
SLEEP mode
Yes
XS analog debounced
No
XS
XS
No
Figure 4. EM6580 Reset Structure
RESETs generation logic diagram
SCRsel0
SCRsel1
Ck[1]
WDVal
Write- Reset
WDVa
NoWDtim
Watchdog
times
Read Statuts
Write- Active
SleepEn
Sleep Counter
Reset Oscillator
typ . 100Hz
Prescaler
Sleep
Internal Data Bus
Read Statuts
Sleep
resetCold
Analogue
Filter
Wake up (on change)
System Reset
Delay
ResSys
Peripherals
&
CPU
ck[15]
Debounce
POR &
Power-check
POR
InResAH
ck[9]
Set
PORstatus
Reset
Rd RegSysCntl1
PA[3]
PA[4]
PA[3/4]Resin
All signals enter bottom, left, top and output on the right side of the boxes
All reset sources activate the System Reset (ResSys). The ‘System Reset Delay’ ensures that the system reset
remains active long enough for all system functions to be reset (active for 12 system clock cycles. CPU is reset
by the same reset
As well as activating the system reset, the POR also resets all bits in registers marked ‘p’ and the sleep enable
(SleepEn) latch. System reset does not reset these register bits, nor the sleep enable latch.
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EM6580
4.1 POR with Power-Check Reset
An on chip detection circuit generates a power-on reset (POR). The POR is generated whenever VDD is
below the detection level defined in section 17.4. A second detection circuit circuitry, power check level,
ensures a proper start-up of the microcontroller if VDD is higher than this level. This level is higher than POR
and defined in section 17.4.
If VDD drops below the static POR level, the chip goes in reset state.
To distinguish between POR reset and all other types of reset, the PORstatus bit in RegSysCntl2 is set on at
every POR and is cleared by writing the RegSysCntl1 register.
Figure 5. EM6580 Start-up sequence
VDD
Power
check level
Power on
reset level
Internal Reset
Tpchk
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4.2 Input Port A Reset
By writing the PA[3/4]ResIn in RegFreqRst registers the PA[3] or PA[4] input becomes dedicated for external
reset. This bit is cleared by POR only. Which input is selected is set by IrqPA[3l/4h] bit from RegPACntl2
register which is described in Chapter 6.
Bit InResAH in the RegFreqRst register selects the PA[3/4] reset function in Active and standby (Halt) mode. If
set to ‘0’ the PA[3/4] reset is inhibited. If Set to ‘1’ than PA[3/4] input goes through a debouncer and needs to
respect timing associated with the debounce clock selection made by DebSel bit in RegPresc register.
This InResetAH bit has no action in sleep mode, where a Hi pulse on PA[3/4] always immediately triggers a
system reset (only small analogue debouncer is attached to filter 1 or 2 μs spikes).
90H
Overview of control bits and possible reset from PA[3] or PA[4] is specified in table 4.2.1 below.
Table 4.2.1 Possible Reset from PA[3] or PA[4]
PA[3/4]ResIn InResAH
0
X
1
0
1
1
ACTIVE or STAND-BY mode
NO reset from PA[3] or PA[4]
NO reset from PA[3] or PA[4]
Debounce reset with debck of
* Ck[14]/ Ck[11]/ Ck[8] needing
0.25 ms / 2 ms / 16ms Hi pulse typ.
* Ck[14]/ Ck[11]/ Ck[8] are explained in chapter 5.2 Prescaler.
SLEEP mode
NO reset from PA[3] or PA[4]
Reset with small analog filter
Reset with small analog filter
91H
4.3 Digital Watchdog Timer Reset
The Digital Watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It
will generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by
activating an inhibit digital watchdog bit (NoWDtim) located in RegVLDCntl. At power up, and after any
system reset, the watchdog timer is activated.
If for any reason the CPU stops or stays in a loop where watchdog timer is not periodically cleared, it
activates the system reset signal. This function can be used to detect program overrun, endless loops, etc.
For normal operation, the watchdog timer must be reset periodically by software at least every 2.5 seconds
(system clock = 32 KHz), or a system reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and
timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog
timer also operates in standby mode and thus, to avoid a system reset, standby should not be active for
more than 2.5 seconds.
From a System Reset state, the watchdog timer will become active after 3.5 seconds. However, if the
watchdog timer is influenced from other sources (i.e. prescaler reset), then it could become active after just
2.5 seconds. It is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the
watchdog every second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the
counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’, {WDVal1 WDVal0}). When
reaching the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the
system reset which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore
always reads ‘0’.
Table 4.3.1 Watchdog timer register RegSysCntl2
Bit
Name
Reset
R/W
Description
3 WDReset
0
W
Reset the Watchdog (The Read value is always '0')
1 Æ Resets the Logic Watchdog
0 Æ no action
2 SleepEn
0
R/W
See Operating modes (sleep)
1 WDVal1
0
R
Watchdog timer data 1/4 ck[1]
0 WDVal0
0
R
Watchdog timer data 1/2 ck[1]
3 PORstatus
1 P*
R
Power-On-Reset status
1 P* POR sets the PORstatus bit which is cleared by writing register RegSysCntl1
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EM6580
4.4 Sleep Counter Reset
To profit the most from Low Power Sleep Mode and still supervise the circuit surrounding, one can enable the
Sleep Counter Reset which only runs in Sleep mode and periodically wakes up the EM6580. Four (4) different
Wake-Up periods are possible as seen in table below.
Control bits SleepCntDis which is set to default ‘0’by POR enables the Sleep Counter when the circuit goes
into Sleep mode. The SCRsel1, SCRsel0 bits that are used to determine Wake-Up period are in the
RegSleepCR register. To disable the Sleep Counter in Sleep mode SleepCntDis must be set to ‘1’.
Table 4.4.2 Register RegSleepCR
Bit
Name
Reset
3
NoPullPA[4]
0 por
2
SleepCntDis
0 por
1
SCRsel1
0 por
0
SCRsel0
0 por
R/W
R/W
R/W
R/W
R/W
Description
Remove pull-up/down from PA[4] input
Disable Sleep Reset Counter when Hi
Selection bit 1 for Sleep RCWake-Up period
Selection bit 0 for Sleep RCWake-Up period
Table 4.4.3 Wake-Up period from Sleep selection
SCRsel1
SCRsel0
Sleep Reset Counter periods
0
0
1.5 internal low speed RC clock periods
0
1
15.5 internal low speed RC clock periods
1
0
127.5 internal low speed RC clock periods
1
1
1023.5 internal low speed RC clock periods
Refer to table 18.8 or the actual SCR timeout period timings
92H
Sleep Counter Reset (SCR) uses the same prescaler (see chapter 5.3) as the System Clock in Active and
StandBy mode. Prescaler reset is made automatically just before going into Sleep mode if SCR is enable.
This causes the Sleep Reset Counter to have its specified period.
4.5 Wake-Up on Change
By writing the WUchEn[0/5] and/or WUchEn[3/4] bit in RegPaCntl2 registers the PA[0] or PA[5] and/or PA[3]
or PA[4] can generate a reset from sleep on any polarity change on a selected pin. The port selection is
defined with bits IrqPA[0l/5h] and IrqPA[3l/4h]. See chapter 6 and Figure 10 for more details.
4.6 The CPU State after Reset
Reset initializes the CPU as shown in Table 4.6.1 below.
93H
Table 4.6.1 Initial CPU value after Reset.
Name
Bits
Program counter 0
12
Program counter 1
12
Program counter 2
12
Stack pointer
2
Index register
7
Carry flag
1
Zero flag
1
Halt
1
Instruction register
16
Periphery registers
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Symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
Initial Value
$000 (as a result of Jump 0)
Undefined
Undefined
SP[0] selected
Undefined
Undefined
Undefined
0
Jump 0
Reg.....
See peripheral memory map
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5. Oscillator and Prescaler
5.1 RC Oscillator or external Clock
EM6580 can use the internal RC oscillator or external clock source for its operation.
The built-in RC oscillator without external components generates the system operating clock for the CPU and
peripheral blocks. The RC oscillator is supplied by the regulated voltage.
The RC oscillator frequency can be chosen from 5 possibilities with a register with 2 basic frequencies.
These are typically 32kHz, 64kHz, 128kHz, 256kHz or 500kHz for 32kHz basic frequency or 50kHz, 100kHz,
200kHz, 400kHz or 800kHz for 50kHz basic frequency . Depending on the selected RC frequency. A special 4
stage freq. divider is available to be able to deliver to Prescaler which generates all System clock except CPU
clock, a frequency close to 32 or 50 kHz to keep the peripheral timing as close as possible to specifications.
After POR the circuit always starts with the internal RC oscillator, but it can be switched to the external clock by
setting the ExtCPUclkON bit in the register RegPresc. The external clock is input at PA[1] and must be in
range from min. 10Khz to max. 1MHz. With this external frequency input all timing for peripherals change and
the special 4 stage freq. divider must be adapted to best suit the applied external frequency to keep 32/50kHz
System clock as close as possible. The system clock must be less than 64kHz. The external clock source
must be a square wave with full amplitude from Vss to Vdd. See Table 5.2.2 for advised special divisions
depending on the external clock frequency.
Switching from internal RC oscillator to External clock or back from External clock to RC oscillator is made
without generating a glitch on the internal clock. Once the circuit is running on the external Clock one can
disable the RC oscillator by setting the RCoscOff bit in RegSCntl2 to ‘1’.
In sleep mode the oscillator is stopped. It can be stopped also by setting the RCoscOff bit. This bit can be set
only if ExtCPUClkOn was set before, indicating that the CPUck was switched from the internal RC oscillator to
the external clock which MUST be present. If the External Clock stops without going into Sleep mode first the
EM6580 can block and only POR can reset it.
Figure 8. below shows the connection of the RC oscillator and external clock and generation of CPUclk and
System clock = SysClk which is divided by the special 4 stage Freq. Divider if needed as described in 5.2 and
prescaler described in 5.3.
94H
Figure 6. Clock source for CPU or system peripherals
RC oscillator
32kHz – 512kHz
50kHz - 800kHz
RCClk
metal option selection
0
CPUclk
MUX
PA[1]
External clock
10kHz – 800kHz
1
Frequency
divider
PAout[5]
div16
div8
div4
div2
Automatic clock selection
SysClk = 32kHz or 50kHz
depending on selected
RCClk selection
div1
ExtCPUclkON
MUX
PA[5]
MUX
PA[2]
foutSel[1:0]
MUX
CpuClk
SysClk
Ck[12]
Ck[1]
MUX
Sout
PAout[2]
ResSys
Ck[14]
To Peripherals
Ck[15:1]
PRESCALER
LOW 15 stages divider Ck[15:1]
SysClk
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5.2 Special 4 stage Frequency Divider
If an internal RC clock or external frequency higher than 32 kHz or 50 kHz is selected, then the special 4 stage
Frequency Divider must be used to select a frequency close to 32 kHz or 50 kHz for the SysClk - system clock
used by the Prescaler. This is done by register option.(Refer to RegMFP1 table chapter 14.8)
If the external clock will be used, the same register option used to select the division for SysClk. Table below
shows recommended divisions in this 4 stage divider.
95H
Table 5.2.1 PA[1] I/O status depending on its RegPACntl3 and RegPa0OE registers
Ext. clock
10 kHz – 50 kHz
55 kHz – 100 kHz
110 kHz – 200 kHz
220 kHz – 400 kHz
400 kHz – 1 MHz
RC frequency
(1)base (2) base
32
50
64
128
256
500
RC frequency or External freq.
Typical Obtained SysClk
MUST be divided by
Min.- typ. If RC - Max. [kHz]
No Division to SysClk
10 – 32 – 50
100
200
400
800
Divided by 2
Divided by 4
Divided by 8
Divided by 16
27.5
27.5
27.5
10
–
–
–
–
32
32
32
32
–
–
–
–
50
50
50
62.5
5.3 Prescaler
The prescaler consists of a fifteen element divider chain which delivers clock signals for the peripheral circuits
such as timer/counter, debouncer and edge detectors, as well as generating prescaler interrupts. The input to
the prescaler is the system clock signal closest to 32 kHz or 50 kHz which comes from the RC oscillator or
external clock as divided by the preceding divider. Power on initializes the prescaler to Hex(0001).
Table 5.3.1 Prescaler Clock Name Definition
Function
Name
System clock
System clock / 2
System clock / 4
System clock / 8
System clock/ 16
System clock / 32
System clock / 64
System clock / 128
Ck[16]
Ck[15]
Ck[14]
Ck[13]
Ck[12]
Ck[11]
Ck[10]
ck [9]
32 KHz
SysClk
32768 Hz
16384 Hz
8192 Hz
4096 Hz
2048 Hz
1024 Hz
512 Hz
256 Hz
50 KHz
SysClk
50000 Hz
25000 Hz
12500 Hz
6250 Hz
3125 Hz
1562 Hz
781 Hz
390 Hz
Function
Name
System clock / 256
System clock / 512
System clock / 1024
System clock / 2048
System clock / 4096
System clock / 8192
System clock / 16384
System clock / 32768
Ck[8]
Ck[7]
Ck[6]
Ck[5]
Ck[4]
Ck[3]
Ck[2]
Ck[1]
32 KHz
SysClk
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
50 KHz
SysClk
195 Hz
97 Hz
49 Hz
24 Hz
12 Hz
6 Hz
3 Hz
1.5 Hz
Figure 7. Prescaler Frequency Timing
Prescaler Reset
SysClk = System clock Ck[16]
Ck[15]
Ck[14]
Ck[13]
Horizontal Scale change
Ck[2]
Ck[1]
First positive edge of 1 Hz clock Ck[1] is 1 sec after the falling reset edge
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Table 5.3.2 Control of Prescaler Register RegPresc
Bit
3
2
Name
ExtCPUclkON
ResPresc
Reset
p
0
R/W
R/W
R/W
1
PrIntSel
0
R/W
0
DebSel
0
R/W
Description
Ext. Clock selection instead of RC oscillator for CPUClk.
Write Reset prescaler
1 Æ Reset the divider chain from Ck[14] to Ck[2], sets Ck[1].
0 Æ No action.
The Read value is always '0'
Prescaler Interrupt select. 0 Æ Interrupt from Ck[4] (typ. 8/12 Hz)
1 Æ Interrupt from Ck[7] (typ. 64/97 Hz)
Debouncer clock select. 0 Æ Debouncer with Ck[8]
1 Æ Debouncer with Ck[11] or Ck[14]
p* reset to ‘0’ by POR only.
With DebSel = 1 one may choose either the Ck[11] or Ck[14] debouncer frequency by selecting the
corresponding register mask option.(Refer to RegMFP1 table chapter 14.8) Relative to 32kHz the
corresponding max. debouncer times are then 2 ms or 0.25 ms. For the register option selection refer to
chapter 14.8
96H
97H
Switching the PrIntSel may generate an interrupt request. Avoid it with MaskIRQ64/8 = 0 selection during the
switching operation.
The prescaler contains 2 interrupt sources:
- IRQ64/8 ; this is Ck[7] or Ck[4] positive edge interrupt, the selection is depending on bit PrIntSel.
- IRQHz1 ; this is Ck[1] positive edge interrupt
There is no interrupt generation on reset.
The first IRQHz1 Interrupt occurs typically. 1 sec (if SysClk = 32kHz) after reset. (0.65 sec if SysClk is 50kHz).
NOTE: If not written explicitly all timing in peripherals is calculated for 32 kHz System Clock !
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6. Input and Output port A
The EM6580 has:
- port PA[3:0], one 4-bit input/output port
- port PA[4], one 1 bit input port.
- port PA[5], one 1 bit input/output. (not available in 8-pin package).
Pull-up and Pull-down resistors can be added to all these ports with register options.
6.1 Input / Output Port Overview
Table 6.1.1 Input and Output port overview
Pin in 8pin package
General I/O
Serial interface
WakeUp on change
Softw. pullUp/Down
Register option pullUp/Down
Timer input
Irq debounce & edge select.
CPU soft. variable input
Analogue compare Input
External reset input
External CPU clock input
PWM timer out
freq. Output (RC, 2kHz, 1Hz)
CPU reset condition
PA[0]
1
I/O
Sin I
yes* I
Yes
--yes* I
yes* I
---yes O
---
PA[1]
2
I/O
Sclk I/O
-yes
-yes I
----yes I
yes O
---
PA[2]
3
I/O
Sout O
-yes
--------yes* O
yes O
PA[3]
4
I/O
Rdy/CS O
yes* I
yes
-yes* I
yes* I
yes* I
-yes* I
-----
PA[4]
6
I
-yes* I
yes
yes
yes* I
yes* I
yes* I
yes I
yes* I
-----
PA[5]*
NC*
I/O
-yes* I
yes
--yes* I
yes* I
----yes* O
--
NC* – Pad PA[5] is Not Connected in 8-pin package, available on 14-pin and in die form
Register option – Refer to RegMFP1 table chapter 14.8
98H
As shown in Figure 10, Logic for the Wake up on change reset which is possible only from Sleep mode,
Debouce and IRQ function on Rising or falling edge are implemented only twice but can be attached and
configured by registers to 4 different pads when used as inputs.
Ports PA[0] and PA[5] can be configured to have wakeup on Change, and debounced or non-debounced IRQ
on the falling or rising edge. The same function is available on ports PA[3] or PA[4] which in addition can be
dedicated to input reset . Registers RegPACntl1 and RegPACntl2 make this selection.
Table 6.1.2 Register RegPACntl1
Bit
Name
POR
R/W
Description
3
DebounceNoPA[3/4]
0
R/W
Debounce on when Low for PA[3/4] input
2
DebounceNoPA[0/5]
0
R/W
Debounce on when Low for PA[0/5] input
1
EdgeFallingPA[3/4]
0
R/W
IRQ edge selector for interrupt from PA[3/4] input
0
EdgeFallingPA[0/5]
0
R/W
IRQ edge selector for interrupt from PA[0/5] input
* Default is debouncer On and Rising edge for IRQ
Table 6.1.3 Register RegPACntl2
Bit
Name
POR
R/W
Description
3
WUchEnPA[3/4]
0
R/W
Wake/Up on change EN on PA[3] or PA[4]
2
WUchEnPA[0/5]
0
R/W
Wake/Up on change EN on PA[0] or PA[5]
1
IrqPA[3l/4h]
0
R/W
PA[3] if Low / PA[4] if High for IRQ source
0
IrqPA[0l/5h]
0
R/W
PA[0] if Low / PA[5] if High for IRQ source
* Default: No wake Up on change and IRQ source, or reset and timer input, would be PA[3], PA[0]
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6.2 PortA as Input and its Multiplexing
The EM6580 can have up to 6 1-bit general purpose CMOS input ports. The port A input can be read at any
time, pull-up or pull-down resistors can be chosen by software.
Figure 10 explains how the inputs are treated with control signals and how they are distributed to different
peripherals and the CPU. This is also listed in Table 6.1.1 Input and Output ports overview.
Figure 8. EM6580 Multiplexed Inputs diagram
PA[4]
extVcheck
extVcheck
TimCk0
PA[1]
Q
Q
Debounce
I0
PA[5]
I1 S
debouncerYesPA[0/5]
irqPA[0l/5h]
Sleep
RdRegPA
0
I0
Z
QB
QB
Z
TimCk7
Qdeb
Qdeb
CkDeb
PA[0]
to SVLD Logic
Input to peripherals is blocked if used for SVLD comparator input
I1 S
to Timer / Event
Counter
PA[1]
Serial Clock Input
PA[0]
Serial Data Input
to Serial Interface
EdgeFallingPA[0/5]
WakeUp on change
In
Out
uPVar[1]
to CPU
uPVar[2]
WUchEnPA[0/5]
PA[3:0]
Internal Data Bus DB [3:0]
RdRegPA
1
PA[5:4]
Qdeb
CkDeb
Q
Debounce
PA[3]
I0
PA[4]
I1 S
Z
Z
QB
debouncerYesPA[3/4]
IRQPA[0/5]
I0
IRQPA[3/4]
to Interrupt Logic
I1 S
EdgeFallingPA[3/4]
irqPA[3l/4h]
WakeUp on change
In
Out
Sleep
WakeUp on Change
to Reset Logic
WUchEnPA[3/4]
Small Analogue Filter
ResDis
InResAH
In
Out
PA3/4_reset
ResFlt
PA3/4resln
All signals enter bottom, left, top and output on the right side of the boxes
Some Input functions are explained below.
6.2.1 Debouncer
The debouncer is clocked with one of the possible debouncer clocks (Ck[14] / Ck[11] / Ck[8] and can be used
only in Active or StandBy mode (as only in these two modes clocks are running). The input signal has to be
stable on two successive debouncer rising clock edges and must not change between them.
Figure 9. Debouncer function
DEBOUNCER function (signal must be stable during two Deb Clk rising edges)
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6.2.2 IRQ on Port A
For interrupt request generation (IRQ) one can choose direct or debounced input and rising or falling edge IRQ
triggering. With the debouncer selected debounceYesPA[x/y], the input must be stable for two rising edges of
the selected debouncer clock CkDeb. This means a worst case of 16ms(default) or 2ms (0.25ms by metal
mask) with a system clock of 32kHz.
Either a rising or falling edge on the port A inputs - with or without debouncing - can generate an interrupt
request. This selection is done by edgeFallingPA[x/y].
PortA can generate max 2 different interrupt requests. Each has its own interrupt mask bit in the
RegIRQMask1 register. When an IRQ occurs, inspection of the RegIRQ1 and RegIRQ2 registers allow the
interrupt to be identified and treated.
At power on or after any reset the RegIRQMask1 is set to 0, thus disabling any input interrupt. A new interrupt
is only stored with the next active edge after the corresponding interrupt mask is cleared. See also the interrupt
chapter 9.
It is recommended to mask the port A IRQ’s while one changes the selected IRQ edge. Otherwise one may
generate an unwanted IRQ (Software IRQ). I.e. if a bit PA[0/5] is ‘0’ then changing from positive to negative
edge selection on PA[0/5] will immediately trigger an IRQPA[0/5] if the IRQ was not masked.
9H
6.2.3 Pull-up/down
On Each terminal of PA[3:0] and PA[5] an internal pull-up (metal mask MAPU[n]) or pull-down (metal mask
MAPD[n]) resistor can be connected per metal mask option. By default the two resistors are in place. In this
case one can choose by software to have either a pull-up, a pull-down or no resistor.
See below for better understanding. If the port is used also as output please check Chapter 6.3.1 CMOS / Nch.
Open Drain Output.
PA[4] can have only strong Pull-up or Pull-down resistor which can be removed by the software register
NoPullUpDown[4].
PA[4] can have only strong Pull-up or Pull-down resistor. This resistor can be disconnected by software in
register RegSleepCR bit NoPullPA[4].
For Metal mask selection and available resistor values refer to chapter 13.
Pull-down ON: MAPD[n] must be in place ,
AND bit NoPdPA[n] must be ‘0’ .
with n=0, 1, 2, 3, 5
Pull-down OFF: MAPD[n] is not in place,
OR if MAPD[n] is in place NoPdPA[n] = ‘1’ cuts off the pull-down.
OR selecting NchOpDrPA[n] = ‘1’ cuts off the pull-down.
Pull-up ON :
MAPU[n] must be in place,
AND bit NchOpDrPA[n] must be ‘1’ ,
AND (bit OEnPA[n] = ‘0’ (input mode) OR if OEnPA[n] = ‘1’ while PAData[n] = 1. )
Pull-up OFF :
MAPU[n] is not in place,
OR if MAPU[n] is in place NchOpDrPA[n] = ‘0’ cuts off the pull-up,
OR if MAPU[n] is in place and if NchOpDrPA[n] = ‘1’ then PAData[n] = 0 cuts off the pull-up.
Never pull-up and pull-down can be active at the same time.
Any port A input must never be left open (high impedance state, not connected, etc. ) unless the internal pull
resistor is in place (mask option) and switched on (register selection). Any open input may draw a significant
cross current which adds to the total chip consumption.
Note: The mask settings MAPU[n]) and MAPD[n] do not define the default pull direction, but the pull
possibilities. It is the software which defines the pull direction (pull-up or pull-down). The only exception is on
PA[4] where the user must decide if he wants pull-up or pull-down. For this input the selected pull direction will
always be valid unless the software disconnects the pull resistor.
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6.2.4 Software test variables
As shown in Figure 10 PA[0/5] or PA[3/4] are also used as input conditions for conditional software branches.
These CPU inputs are always debounced and non-inverted.
• debounced PA[0/5] is connected to CPU TestVar1
• debounced PA[3/4] is connected to CPU TestVar2
CPU TestVar3 is connected to Ground and can not be used in Software.
6.2.5 Port A for 10-Bit Counter
The PA[1] and PA[3/4] inputs can be used as the clock input terminal for the 10 bit counter
• PA[1] is at counter clock selection 0. The input is direct ( no debouncer is possible
• PA[3/4] is at counter clock selection 7. As for the IRQ generation, debounced or input directly and
non-inverted or inverted input is possible. This is defined with the register RegPaCntl1. Debouncing
the input is always recommended.
6.2.6 Port A Wake-Up on change
In sleep mode if configured port PA[0/5] or PA[3/4] inputs are continuously monitored to wake up on change,
which will immediately wake up the EM6580.
6.2.7 Port A for Serial Interface
When the serial interface is used in slave mode, PA[0] is used for serial data input and PA[1] for the serial
clock.
6.2.8 Port A for External Reset
In Active and Stand-by (Halt) mode a positive debounced pulse on PA[3/4] can be the source of a reset when
PA[3/4]ResIn and InResAH are set at ‘1’. When IrqPA[3l/4h] is ‘0’ than PA[3] is selected for Reset source
and when IrqPA[3l/4h] is ‘1’ than PA[4] is selected for Reset source.
6.2.9 Port PA[4] as Comparator Input
When using the PA[4] as an input to the internal SVLD comparator NO pull resistor should be connected on
this terminal. Otherwise the device may draw excessive current.
First PA[4] pull-up/down resistor should be disconnected by software and the ExtVcheck bit can be set to ‘1’.
This dedicates PA[4] as SVLD resistor divider input to the SVLD comparator.
At this point the measurements respect the same timing as any other SVLD measurements as explained in
Chapter Supply Voltage Detector. It can also generate an IRQ if the input voltage is lower as Comparator level.
Thus configured a direct read of PA[4] will result in reading ‘0’.
6.2.10 Reset and Sleep on Port A
During circuit initialisation, all Control registers are reset by Power On Reset and therefore all pull-ups are off
and all pull-downs are on.
During Sleep mode, the circuit retains its register values. As such the PA configurations remain active also
during Sleep.Sleep mode is cancelled with any Reset. However the Reset State does not reset the Control
registers bits which are specifically marked to be initialised by POR only. (Pull, Nch Open drain, Freq out, etc
configurations).
however Sleep mode is cancelled with a Reset and all system register will be reinitialized at this point. (the
circuit is in Reset State. and pull-downs, if previously turned on. After any reset the serial interface parameters
are reset to : Slave mode, Start and Status = 0, LSB first, negative edge shift , PA[3:0] tri-state.
6.2.11 Port A Blocked Inputs
In sleep mode if PortA inputs are not used and prepared for Wake-Up on Change or Reset these inputs are
blocked. At that time port can be undefined from external and this will not generate an over-consumption.
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
: Blocked if Sleep bit set
: Blocked if Sleep bit set
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
Also blocked if External VLD check enabled
: Never blocked
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6.3 PortA as Output and its Multiplexing
The EM6580 can have up to 4 (5 in Die form or 14-pin package) bit general purpose CMOS or N-channel Open
Drain Output ports. Table 6.1.1 Input and Output ports overview shows all the possibilities. Figure 12 shows
the output architecture and possible output signals together with software controlled pull-up and pull-down
resistors which are disconnected when the port is an output and in a defined state, to preclude additional
consumption.
The output multiplexing registers are RegPACntl3 and RegPACntl4.
Figure 10. Port A Architecture (Outputs)
Open Drain Control
Register (NchOpPA[n])
Pull-down Register
(NoPdPA[n])
OD[n]
Pd[n]
Vdd
Output Enable Register
(OEnPA[n])
Active Pull-up
in Nch. Open
Drain Mode
OE[n]
Port A
Input / Output
Control Logic
Port A Data Register
(PAout[n])
Metal
Option
MAPu[n]
Output Mux Registers
out[n]
Internal DATA Bus
Vdd
PA[5,3:0]
mux[n]
Metal
Option
MAPd[n]
Multiplexed Outputs from:
- Serial Interface
- PWM, frequency out.
- System Reset
Active
Pull-down
Read Port A
Block Input (Low)
To Irq, Reset, Clock, etc
6.3.1 CMOS / Nch. Open Drain Output
The port A outputs can be configured as either CMOS or Nch. open drain outputs. In CMOS both logic ‘1’ and
‘0’ are driven out on the terminal. In Nch. Open Drain only the logic ‘0’ is driven on the terminal, the logic ‘1’
value is defined by the internal pull-up resistor (if implemented), or high impedance.
Figure 11. CMOS or Nch. Open Drain Outputs
CMOS Output
Nchannel Open Drain Output
Vdd
Active Pull-up
for High State
Daout[n]
PA[5,3:0]
Mux
Other Outputs
Daout[n]
I/O Terminal
Tri-State Output
Buffer is Closed
Out Mux Control
PA[5,3:0]
Mux
Other Outputs
Out Mux Control
Tri-State Output
Buffer : High
Impedance for
Data = ‘1’
I/O Terminal
NOTE: State of I/O pads may not be defined until Vreg reaches typ. 0.8V and Power-On-Reset logic
supplied by Vreg clears them to Inputs.
This time depends on how fast capacitor on Vreg is charged and typ. it can be in range of couple of ms.
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6.4 Port A registers
The two Control registers for Input control, RegPACntl1 and RegPACntl2, were already shown in chapter 6;
Input / Output Ports Overview.
10H
Table 6.4.1 Register RegPA0
Bit
Name
Reset
R/W
Description
3
PAData[3]
0
R* /W
PA[3] input and PAout[3] output
2
PAData[2]
0
R* /W
PA[2] input and PAout[2] output
1
PAData[1]
0
R* /W
PA[1] input and PAout[1] output
0
PAData[0]
0
R* /W
PA[0] input and PAout[0] output
* Direct read on Port A terminals
Table 6.4.2 Register RegPa0OE
Bit
Name
Reset
R/W
Description
3
OEnPA[3]
0
R/W
I/O control for PA[3] , output when OEnPA[3] = Hi
2
OEnPA[2]
R/W
I/O control for PA[2] , output when OEnPA[2] = Hi
0 P**
1
OEnPA[1]
0
R/W
I/O control for PA[1] , output when OEnPA[1] = Hi
0
OEnPA[0]
0
R/W
I/O control for PA[0] , output when OEnPA[0] = Hi
P** On Reset PA[2] is forced to output if ( PA[0]=’0’, PA[1]=’1’, PA[4]=’1’, Sout/RstPA[2]=’1’ and
freqOutPA[2]=’1’ ) until System reset is finished. Refer also to Table 6.4.11.
After Reset is finished and circuit starts to execute instructions PA[2] becomes tri-state input.
Bit OEnPA[2] is reset to ‘0’ with every Reset.
Table 6.4.3 Register Pa0noPDown
Bit
Name
POR*
R/W
Description
3
NoPdPA[3]
0
R/W
No pull-down on PA[3]
2
NoPdPA[2]
0
R/W
No pull-down on PA[2]
1
NoPdPA[1]
0
R/W
No pull-down on PA[1]
0
NoPdPA[0]
0
R/W
No pull-down on PA[0]
POR* Reset only with Power On Reset
10H
Table 6.4.4 Register Pa0NchOpenDr
Bit
Name
POR*
R/W
Description
3
NchOpDrPA[3]
0
R/W
Nch. Open Drain on PA[3]
2
NchOpDrPA[2]
0
R/W
Nch. Open Drain on PA[2]
1
NchOpDrPA[1]
0
R/W
Nch. Open Drain on PA[1]
0
NchOpDrPA[0]
0
R/W
Nch. Open Drain on PA[0]
* Reset only with Power On Reset, Default "0" is: CMOS on PA[3..0]
Table 6.4.5 Register RegPA1
Bit
Name
Reset
R/W
Description
3
NchOpDrPA[5]
p**
R* /W
Nch. Open Drain on PA[5]
2
OEnPA[5]
0
R* /W
I/O control for PA[5] , output when OEnPA[5] = Hi
1
PAData[5]
0
R* /W
PA[5] input and PAout[5] output
0
PAData[4]*
0
R*
PA[4] input
* Direct read on Port A terminals
p** reset to ‘0’ by POR only
Table 6.4.6 Register RegFreqRst
Bit
Name
POR
3
InResAH
p
2
PA3/4resIn
p
1
foutSel[1]
x
0
foutSel[0]
x
R/W
R/W
R/W
R/W
R/W
Description
Input reset On in Active and StandBy mode
PA3/4 dedicated for Input reset when set at ‘1’
Output Frequency selection (foutSel[1:0])
(11)CPUClk, (10) SysClk, (01) 2kHz, (00) 1Hz
Interrupt PortA Control bits MaskIRQPA[0/5] and MaskIRQPA[3/4] used to enable (Mask) the Interrupt
ReQuest IRQ from PortA are in register RegIRQMask1.
Interrupt status bits IRQPA[0/5] and IRQPA[3/4] used to signal the Interrupt from PortA are in register
RegIRQ1. They are both shown in Chapter Interrupt Controller.
Note: CPUClk = RCClk if no external clock used.
In case of external clock, CPUClk is equal to the PA[1] input clock.
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Output multiplexing registers are shown below.
Table 6.4.7 Register RegPACntl3
Bit
Name
POR
3
SerialStPA[3]
0
2
SerialCkPA[1]
0
1
PWMoutPA[1]
0
0
PWMoutPA[0]
0
R/W
R/W
R/W
R/W
R/W
Description
Output selection for PA[3] when output
Output selection for PA[1] when output
Output selection for PA[1] when output
Output selection for PA[0] when output
Table 6.4.8 Register RegPACntl4
Bit
Name
POR
3
NoPdPA[5]
0
2
freqOutPA[5]
0
1
Sout/rstPA[2]
1
0
freqOutPA[2]
1
R/W
R/W
R/W
R/W
R/W
Description
No pull-down on PA[5]
Output selection for PA[5] when output
Output selection for PA[2] when output
Output selection for PA[2] when output
Table 6.4.9 PA[0] I/O status depending on its RegPACntl3 and RegPa0OE registers
OEnPA[0]
PWMoutPA[0]
Description of PA[0] terminal
Input
0
X
PAout[0] general Output
1
0
PWM Output from the 10-Bit Counter
1
1
Table 6.4.10 PA[1] I/O status depending on its RegPACntl3 and RegPa0OE registers
OEnPA[1]
SerialCkPA[1] PWMoutPA[1] Description of PA[1] terminal
Input
0
X
X
PAout[1] general Output
1
0
0
PWM Output from the 10-Bit Counter
1
0
1
Sclk (Serial interface clock output)
1
1
X
Table 6.4.11 PA[2] I/O status depending on its RegPACntl4 and RegPa0OE registers
OEnPA[2]
Sout/rstPA[2] freqOutPA[2]
Description of PA[2] terminal
0
X
X
Input
1
0
0
PAout[2] general Output
1
0
1
Freq. Output (CPUClk,SysClk, 2kHz, 1Hz)
1
1
0
Sout (Serial interface data output)
High level ‘1’ during Reset state output
1
1
1
8kHz frequency output while out of reset state
Low level ‘0’ output during sleep
0
PA[0] = ‘1’
Output: high level during Reset state
1
1
PA[4] = ‘1’
Input: out of reset state and during sleep
PA[1] = ‘0’
Frequency output is selected in 6.4.6 Register RegFreqRst
Table 6.4.12 PA[3] I/O status depending on its RegPACntl3 and RegPa0OE registers
OEnPA[3]
SerialStPA[3]
Description of PA[3] terminal
Input
0
X
PAout[3] general Output
1
0
Rdy/CS (Serial interface status output)
1
1
Table 6.4.13 PA[5] I/O status depending on its RegPACntl4 and RegPA1 registers
OEnPA[5]
freqOutPA[5]
Description of PA[5] terminal
Input
0
X
PAout[5] general Output
1
0
Freq. Output (CPUClk,SysClk, 2kHz, 1Hz)
1
1
Frequency output is selected in 6.4.6 Register RegFreqRst
Note: CPUClk = RCClk if no external clock used.
In case of external clock, CPUClk is equal to the PA[1] input clock.
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7. Serial Port
The EM6580 contains a simple, half duplex three wire synchronous type serial interface., which can be used to
program or read an external EEPROM, ADC, ... etc. Its I/O are multiplexed on Port A.
For data reception, a shift-register converts the serial input data on the SIN(PA[0]) terminal to a parallel format,
which is subsequently read by the CPU in registers RegSDataL and RegSDataH for low and high nibble. To
transmit data, the CPU loads data into the shift register, which then serializes it on the SOUT(PA[2]) terminal.
It is possible for the shift register to simultaneously shift data out on the SOUT terminal and shift data in on the
SIN terminal. In Master mode, the shifting clock is supplied internally by the Prescaler : one of three prescaler
frequencies are available, Ck[16], Ck[15] or Ck[14]. In Slave mode, the shifting clock is supplied externally on
the SCLKIn(PA[1]) terminal. In either mode, it is possible to program : the shifting edge, shift MSB first or LSB
first and direct shift output. All these selection are done in register RegSCntl1 and RegSCntl2.
Figure 12. Serial Interface Architecture
Serial Master Clock Output
SCLKout to SCLK PA[1]
Serial Input Data
from SIN PA[0]
Internal Master Clock
Source (ck[16,15,14])
8-bit Shift Register
Mux
Internal DATA bus
External Slave Clock Source
(SCLKin from SCLK PA[1]
Shift Ck
Clock
Enable
Write Tx Read Tx
Shift complete
(8th Shift Clock)
IRQSerial
Status to
CS/Ready PA[3]
Mode
Control
&
Status Registers
Serial Output Data to
SOUT PA[2]
Start
Status
Direct MSB;LSB
Shift
First
Status
Control Logic
ResetStart
The PA[3..0] terminal configuration is shown in Figure 10 and 12. When the Serial Interface is used then care
should be taken not to use inputs and outputs needed for Serial Interface for other peripherals !:
∗ PA[0] {SIN} must be dedicated to Serial input if needed and can not be used for IRQ, Software Variable
jumps or Output. It can be still used for Wake-Up on Change
∗ PA[1] {SCLK} is an output for Master mode {SCLKOut} and an input for Slave mode {SCLKIn}. But different
functions can be Switched On/Off with care as they are needed.
∗ PA[2] {SOUT} must be dedicated to Serial Data Output if needed and can not be used for Analogue input, or
other Output.
∗ PA[3] {CS/ Ready } if used for serial Interface status output. When used for Serial Interface it should not be
used for IRQ, Software Variable jumps or Output. It can be still used for Wake-Up on Change.
Note:
Before using the serial interface, the corresponding circuit terminals must be configured accordingly.
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7.1 General Functional Description
After power on or after any reset the serial interface is in serial slave mode with Start and Status set to 0, LSB
first, negative shift edge and all outputs are in high impedance state.
When the Start bit is set, the shift operation is enabled and the serial interface is ready to transmit or receive
data, eight shift operations are performed: 8 serial data values are read from the data input terminal into the
shift register and the previous loaded 8-bits are send out via the data output terminal. After the eight shift
operation, an interrupt is generated, and the Start bit is reset.
Parallel to serial conversion procedure ( master mode example ).
Setup the circuit IO’s accordingly.
Write to RegSCntl1 serial control (clock freq. in master mode, edge and MSB/LSB select).
Write to RegSDataL and RegSDataH (shift out data values).
Write to RegSCntl2 (Start=1, mode select, status).
Æ Starts the shift out
After the eighth clock an interrupt is generated, Start becomes low. Then, interrupt handling
Serial to parallel conversion procedure (slave mode example).
Setup the circuit IO’s accordingly.
Write to RegSCntl1 (slave mode, edge and MSB/LSB select).
Write to RegSCntl2 (Start=1, mode select, status).
After eight serial clocks an interrupt is generated, Start becomes low.
Interrupt handling.
Shift register RegSDataL and RegSDataH read.
A new shift operation can be authorized.
7.2 Detailed Functional Description
Master or Slave mode is selected in the control register RegSCntl1.
In Slave mode, the serial clock comes from an external device and is input via the PA[1] terminal as a
synchronous clock (SCLKIn) to the serial interface. The serial clock is ignored as long as the Start bit is not
set. After setting Start, only the eight following active edges of the serial clock input PA[1] are used to shift the
serial data in and out. After eight serial clock edges the Start bit is reset. The PA[3] terminal is a copy of the
(Start OR Status) bit values, it can be used to indicate to the external master, that the interface is ready to
operate or it can be used as a chip select signal in case of an external slave.
In Master mode, the synchronous serial clock is generated internally from the system clock. The frequency is
selected from one out of three sources ( MS0 and MS1 bits in RegSCntl1) . The serial shifting clock is only
generated during Start = high and is output to the SCLK terminal as the Master Clock (SCLKOut). When Start
is low, the serial clock output on PA[1] is 0.
An interrupt request IRQSerial is generated after the eight shift operations are done. This signal is set by the
last negative edge of the serial interface clock on PA[1] (master or slave mode) and is reset to 0 by the next
write of Start or by any reset. This interrupt can be masked with register RegIRQMask2. For more details
about the interrupt handling see chapter 11.
Serial data input on PA[0] is sampled by the positive or negative serial shifting clock edge, as selected by the
Control Register POSnNeg bit. Serial data input is shifted in LSB first or MSB first, as selected by the Control
Register MSBnLSB bit.
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7.2.1 Output Modes
Serial data output is given out in two different ways. Refer also to Figures 15 and 16.
Figure 13. Direct or Re-Synchronized Output
Direct Shift Out
Re-Synchronised Shift Out
• OM[0] = 0 :
The serial output data is generated with the selected shift register clock (POSnNeg). The first data bit is
available directly after the Start bit is set.
• OM[0] = 1 :
The serial output data is re-synchronized by the positive serial interface clock edge, independent of the
selected clock shifting edge. The first data bit is available on the first positive serial interface clock edge after
Start=‘1’.
Table 7.2.1 Output Mode Selection in RegSCntl2
OM[0]
Output mode
Description
0
Serial-Direct
Direct shift pos. or neg. edge data out
1
Serial-Synchronized
Re-synchronized positive edge data shift out
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Figure 14. Shift Operation and IRQ Generation
Note : A write operation in the control registers or in the data registers while Start is high will change internal
values and may cause an error condition. The user must take care of the serial interface status before writing
internal registers. In order to read the correct values on the data registers, the shift operation must be halted
during the read accesses.
Figure 15. Example of Basic Serial Port Connections
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7.3 Serial Interface Registers
Table 7.3.1 Register RegSCntl1
Bit
Name
Reset
R/W
Description
3
MS1
0
R/W
Frequency selection
2
MS0
0
R/W
Frequency selection
1
POSnNeg
0
R/W
Positive or negative clock edge selection for shift operation
0
MSBnLSB
0
R/W
Shift MSB or LSB value first (0=LSB first)
Default "0" is: Slave mode external clock, negative edge, LSB first
Table 7.3.2 Frequency and Master Slave Mode Selection
MS1
MS0
Description
Slave mode: Clock from external
0
0
Master mode Ck[14]: System clock / 4
0
1
Master mode Ck[15]: System clock / 2
1
0
Master modeCk[16]: System clock
1
1
Table 7.3.3 Register RegSCntl2
Bit
Name
Reset
3
Start
0
2
Status
0
1
RCoscOff
0
0
OM[0]
0
R/W
R/W
R/W
R/W
R/W
Description
Enabling the interface,
Ready or Chip Select output on PA[3]
RC oscill. disable when set @ ‘1’ if ExtCPUclkOn is ‘1’
‘0’: Direct shift Output,
‘1’: Output resynchronized
Default "0" is: Interface disabled, status 0, direct shift output.
Table 7.3.4 Register RegSDataL
Bit
Name
Reset
3
SerDataL[3]
0
2
SerDataL[2]
0
1
SerDataL[1]
0
0
SerDataL[0]
0
Default "0" is: Data equal 0.
R/W
R/W
R/W
R/W
R/W
Description
Serial data low nibble
Serial data low nibble
Serial data low nibble
Serial data low nibble
Table 7.3.5 Register RegSDataH
Bit
Name
Reset
3
SerDataH[3]
0
2
SerDataH[2]
0
1
SerDataH[1]
0
0
SerDataH[0]
0
Default "0" is: Data equal 0.
R/W
R/W
R/W
R/W
R/W
Description
Serial data high nibble
Serial data high nibble
Serial data high nibble
Serial data high nibble
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8. 10-bit Counter
The EM6580 has a built-in universal cyclic counter. It can be configured as 10, 8, 6 or 4-bit counter. If 10-bits
are selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting.
The counter works in up- or down count mode. Eight clocks can be used as the input clock source, six of them
are prescaler frequencies and two are coming from the input pads PA[1] (direct only) and PA[3/4] (direct or
debounced). In this case the counter can be used as an event counter.
The counter generates an interrupt request IRQCount0 every time it reaches 0 in down count mode or 3FF in
up count mode. Another interrupt request IRQCntComp is generated in compare mode whenever the counter
value matches the compare data register value. Each of this interrupt requests can be masked (default). See
section 9 for more information about the interrupt handling.
A 10-bit data register CReg[9:0] is used to initialize the counter at a specific value (load into Count[9:0]). This
data register (CReg[9:0]) is also used to compare its value against Count[9:0] for equivalence.
A Pulse-Width-Modulation signal (PWM) can be generated and output on port B terminal PA[0] or PA[1].
102H
Figure 16. 10-bit Counter Block Diagram
Comparator
Up / Down Counter
Data Registers
Control Registers
8.1 Full and Limited Bit Counting
In Full Bit Counting mode the counter uses its maximum
of 10-bits length (default ). With the BitSel[1,0] bits in
register RegCDataH one can lower the counter length,
for IRQ generation, to 8, 6 or 4 bits. This means that
actually the counter always uses all the 10-bits, but
IRQCount0 generation is only performed on the number
of selected bits. The unused counter bits may or may not
be taken into account for the IRQComp generation
depending on bit SelIntFull. Refer to chapter 8.4.
Table 8.1.1. Counter length selection
BitSel[1] BitSel[0 ] counter length
0
0
10-Bit
0
1
8-Bit
1
0
6-Bit
1
1
4-Bit
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8.2 Frequency Select and Up/Down Counting
Eight (8) different input clocks can be selected to drive the Counter. The selection is done with bits
CountFSel2…0 in register RegCCntl1. Six (6) of this input clocks are coming from the prescaler. The
maximum prescaler clock frequency for the counter is half the system clock SysClk and the lowest is 1Hz typ.
Therefore a complete counter roll over can take as much as 17.07 minutes (1Hz clock, 10 bit length) or as little
as 977 μs (Ck[15] typ 16.3kHz, 4 bit length). The IRQCount0, generated at each roll over, can be used for time
bases, measurements length definitions, input polling, wake up from Halt mode, etc. The IRQCount0 and
IRQComp are generated with the system clock Ck[16] rising edge. IRQCount0 condition in up count mode is :
reaching 3FF if 10-bit counter length (or FF, 3F, F in 8, 6, 4-bit counter length). In down count mode the
condition is reaching ‘0’. The non-selected bits are ‘don’t care’. For IRQComp refer to section 8.4.
Note: The Prescaler and the Microprocessor clock’s are usually non-synchronous, therefore time bases
generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down
mode). However the prescaler clock can be synchronized with µP commands using for instance the prescaler
reset function.
Figure 17. Counter Clock Timing
Prescaler Frequencies or Debounced Port A Clocks
System Clock
Prescaler Clock
Counting
Counter IRQ’s
Non Debounced Port A Clocks (System Clock Independent)
System Clock
Port A Clock
Divided Clock
Counting
Counter IRQ’s
The two remaining clock sources are coming from the PA[1] or PA[3/4] terminals. Refer to Figure 10 on page
15 for details. Input PA[1] can be only direct non-debounce input, second PA[3/4] can be either debounce
(Ck[11] or Ck[8]) or direct input, the input polarity can also be chosen. The outputs for Timer clock inputs are
named TimCk0 and TimCk7 respectively. For the debouncer and input polarity selection refer to chapter 6.
In the case of port A input clock without debouncer, the counting clock frequency will be half the input clock on
port A. The counter advances on every odd numbered port A negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA[3/4] or PA[1] input clock edge. In this condition
the EM6580 is able to count with a higher clock rate as the internal system clock (Hi-Frequency Input).
Maximum port A input frequency is limited to 500kHz (@Vdd ≥ 1.5 V). If higher frequencies are needed, please
contact EM Microelectronic’s.
In both, up or down count (default) mode, the counter is cyclic. The counting direction is chosen in register
RegCCntl1 bit Up/Down (default ‘0’ is down count). The counter increases or decreases its value with each
positive clock edge of the selected input clock source. Start up synchronization is necessary because one can
not always know the clock status when enabling the counter. With EvCount=0, the counter will only start on the
next positive clock edge after a previously latched negative edge, while the Start bit was already set to ‘1’. This
synchronization is done differently if event count mode (bit EvCount) is chosen. Refer also to Figure 18.
Internal Clock Synchronization.
103H
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8.3 Event Counting
The counter can be used in a special event count mode where a certain number of events (clocks) on the PA[1]
(only non-debounced and only rising edge) or PA[3/4] input are counted. In this mode the counting will start
directly on the next active clock edge on the selected port A input.
Figure 18. Internal Clock Synchronization
Ck
Ck
Start
Start
Count[9:0 ]
+/-1
EvCount = 0
Count[9:0 ]
+/-1
Ck
Ck
Start
Start
Count[9:0 ]
Count[9:0 ]
EvCount = 0
EvCount = 1
+/-1
EvCount = 1
The Event Count mode is switched on by setting bit EvCount in the register RegCCntl2 to ‘1’. PA[3] or PA[4]
input depending on IrqPA[3l/4h] bit in RegPaCntl1 can be inverted depending on edgeFallingPA[3/4] in
register RegPaCntl1 and should be debounced. The debouncer is switched on with debounceNoPA[3/4] at ‘0’
in the same register. Its frequency depends on the bit DebSel from register RegPresc setting. Refer also to
Figure 10 for PortA Inputs Function. As already said for other PA[1] input only possibility is to count rising nondebounced edges.
A previously loaded register value (CReg[9:0]) can be compared against the actual counter value
(Count[9:0]). If the two are matching (equality) then an interrupt (IRQComp) is generated. The compare
function is switched on with the bit EnComp in the register RegCCntl2. With EnComp = 0 no IRQComp is
generated. Starting the counter with the same value as the compare register is possible, no IRQ is generated
on start. Full or Limited bit compare are possible, defined by bit SelIntFull in register RegSysCntl1.
EnComp must be written after a load operation (Load = 1). Every load operation resets the bit EnComp.
Full bit compare function.
Bit SelIntFull is set to ‘1’. The function behaves as described above independent of the selected counter
length. Limited bit counting together with full bit compare can be used to generate a certain amount of
IRQCount0 interrupts until the counter generates the IRQComp interrupt. With PWMOn=‘1’ the counter would
have automatically stopped after the IRQComp, with PWMOn=‘0’ it will continue until the software stops it.
EnComp must be cleared before setting SelIntFull and before starting the counter again. Be careful,
PWMoutPA[0] also redefines the port PA[0] or PWMoutPA[1] the PA[1] output data. (refer to section 8.4).
The signal PWMOn is acombination of PWMOutPA[0], PWMOutPA[1], SerialCkPA[1]
104H
PWMOn = (PWMOutPA[0] OR PWMOutPA[1]) AND NOT(SeriaCktPA[1]))
Limited bit compare
With the bit SelIntFull set to ‘0’ (default) the compare function will only take as many bits into account as
defined by the counter length selection BitSel[1:0] (see chapter 6.3).
8.4 Pulse Width Modulation (PWM)
The PWM generator uses the behavior of the Compare function (see above) so EnComp must be set to
activate the PWM function.. At each Roll Over or Compare Match the PWM state - which is output on port
PA[0] or PA[1] - will toggle. The start value on PA[0] or PA[1] is forced while EnComp is 0 the value is
depending on the up or down count mode. Every counter value load operation resets the bit EnComp and
therefore the PWM start value is reinstalled.
One can output PWM signal to PA[0] or PA[1]. Setting PWMoutPA[0] to ‘1’ in register RegPaCntl3 routes the
counter PWM output to PA[0]. Insure that PA[0] is set to output mode. Setting PWMoutPA[1] to ‘1’ in register
RegPaCntl3 routes the counter PWM output to PA[1]. Insure that PA[1] is set to output mode. Refer to section
6.3 and 6.4 for the port A output setup.
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The PWM signal generation is independent of the limited or full bit compare selection bit SelIntFull. However if
SelIntFull = 1 (FULL) and the counter compare function is limited to lower than 10 bits one can generate a
predefined number of output pulses. In this case, the number of output pulses is defined by the value of the
unused counter bits. It will count from the start value until the IRQComp match.
One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit
compare) in down count mode.
For instance, loading the counter in up count mode with hex 000 and the comparator with hex C52 which will
be identified as :
- bits[11:10] are limiting the counter to limits to 4 bits length, =03
- bits [9:4] are the unused counter bits = hex 05 (bin 000101),
- bits [3:0] (comparator value = 2).
(BitSel[1,0])
(number of PWM pulses)
(length of PWM pulse)
Thus after 5 PWM-pulses of 2 clocks cycles length the Counter generates an IRQComp and stops.
The same example with SelIntFull=0 (limited bit compare) will produce an unlimited number of PWM at a length
of 2 clock cycles.
8.4.1 How the PWM Generator works.
For Up Count Mode; Setting the counter in up count and PWM mode the PA[0] or PA[1] PWM output is
defined to be 0 (EnComp=0 forces the PWM output to 0 in upcount mode, 1 in downcount). Each Roll Over
will set the output to ‘1’ and each Compare Match will set it back to ‘0’. The Compare Match for PWM always
only works on the defined counter length. This, independent of the SelIntFull setting which is valid only for the
IRQ generation. Refer also to the compare setup in chapter 0.
105H
In above example the PWM starts counting up on hex 0,
2 cycles later compare match Æ PWM to ‘0’,
14 cycles later roll over Æ PWM to ‘1’
2 cycles later compare match Æ PWM to ‘0’ , etc. until the completion of the 5 pulses.
The normal IRQ generation remains on during PWM output. If no IRQ’s are wanted, the corresponding masks
need to be set.
Figure 19. PWM Output in Up Count Mode
Figure 20. PWM Output in Down Count Mode
Clock
Clock
Count[9 :0] 03E
03F
000
001
...
Data-1
Data
Roll-over
Compare
IRQCount0
Data+1
Data+2
Count[9 :0] 001
000
3FF
3FE
...
Data+1
Data
Data-1
Data-2
Roll-over
Compare
IRQCount0
IRQComp
IRQComp
PWM output
PWM output
In Down Count Mode everything is inverted. The PWM output starts with the ‘1’ value. Each Roll Over will set
the output to ‘0’ and each Compare Match will set it back to ‘1’. Due to this positive pulse length is always
longer by 1 selected clock period compared to written value. Example: for 25% positive pulse duty cycle on 4
bit counter one must write 3 in counter instead of 4.
For limited pulse generation one must load the complementary pulse number value. I.e. for 5 pulses counting
on 4 bits load bits[9 :4] with hex 3A (bin 111010).
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8.4.2 PWM Characteristics
PWM resolution is
: 10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps)
the minimal signal period is
: 16 (4-bit) x Fmax*
Æ 16 x 1/Ck[15]
Æ 977 µs
(32 KHz)
the maximum signal period is : 1024 x Fmin*
Æ 1024 x 1/Ck[1]
Æ 1024 s
(32 KHz)
the minimal pulse width is
: 1 bit
Æ 1 x 1/Ck[15]
Æ 61 µs
(32 KHz)
* This values are for Fmax or Fmin derived from the internal system clock (32kHz). Much shorter (and longer)
PWM pulses can be achieved by using the port A as frequency input.
One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit
compare) in down-count mode.
8.5 Counter Setup
RegCDataL[3:0], RegCDataM[3:0], RegCDataH[1:0] are used to store the initial count value called CReg[9:0]
which is written into the count register bits Count[9:0] when writing the bit Load to ‘1’ in RegCCntl2. This bit is
automatically reset thereafter. The counter value Count[9:0] can be read out at any time, except when using
non-debounced high frequency port A input clock. To maintain data integrity the lower nibble Count[3:0] must
always be read first. The ShCount[9:4] values are shadow registers to the counter. To keep the data integrity
during a counter read operation (3 reads), the counter values [9:4] are copied into these registers with the read
of the count[3:0] register. If using non-debounced high frequency port A input the counter must be stopped
while reading the Count[3:0] value to maintain the data integrity.
In down count mode an interrupt request IRQCount0 is generated when the counter reaches 0. In up count
mode, an interrupt request is generated when the counter reaches 3FF (or FF,3F,F if limited bit counting).
Never an interrupt request is generated by loading a value into the counter register.
When the counter is programmed from up into down mode or vice versa, the counter value Count[9:0] gets
inverted. As a consequence, the initial value of the counter must be programmed after the Up/Down selection.
Loading the counter with hex 000 is equivalent to writing stop mode, the Start bit is reset, no interrupt request
is generated.
How to use the counter;
If PWM output is required one has to decide first on which PA port to put it. After corresponding port
Output Enable OEnPA[n] must be set PWMoutPA[n] = 1 in step 5. ( n= 0 or 1)
1st,
set the counter into stop mode (Start=0).
2nd,
select the frequency and up- or down count mode in RegCCntl1.
3rd,
write the data registers RegCDataL, RegCDataM, RegCDataH (counter start value and
length)
4th,
load the counter, Load=1, and choose the mode. (EvCount, EnComp=0)
5th,
select bits PWMoutPA[n] in RegPaCntl3 and SelIntFull in RegSysCntl1
6th,
if compare mode desired , then write RegCDataL, RegCDataM, RegCDataH (compare value)
7th,
set bit Start and select EnComp in RegCCntl2.
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8.6 10-bit Counter Registers
Table 8.6.1. Register RegCCntl1
Bit
Name
Reset
R/W
3
Up/Down
0
R/W
2
CountFSel2
0
R/W
1
CountFSel1
0
R/W
0
CountFsel0
0
R/W
Default : PA0 ,selected as input clock, Down counting
Description
Up or down counting
Input clock selection
Input clock selection
Input clock selection
Table 8.6.2. Counter Input Frequency Selection with CountFSel[2..0]
CountFSel2
CountFSel1
CountFSel0
clock source selection
0
0
Port A PA[1] = non debounced only TimCk0
0
0
1
Prescaler Ck[15] typ. 16 kHz
0
1
0
Prescaler Ck[12] typ. 2 kHz
0
1
1
Prescaler Ck[10] typ. 512 Hz
0
0
0
Prescaler Ck[8] typ. 128 Hz
1
0
1
Prescaler Ck[4] typ. 8 Hz
1
1
0
Prescaler Ck[1] typ. 1 Hz
1
1
1
Port A PA[3/4]
1
Table 8.6.3. Register RegCCntl2
Bit
Name
Reset
R/W
Description
3
Start
0
R/W
Start/Stop control
2
EvCount
0
R/W
Event counter enable
1
EnComp
0
R/W
Enable comparator
0
Load
0
R/W
Write: load counter register;
Read: always 0
Default : Stop, no event count, no comparator, no load
Table 8.6.4. System Control register RegSysCntl1
Bit
Name
Reset
R/W
Description
3 IntEn
0
R/W
General interrupt enable
2 Sleep
0
R/W
Sleep mode
1 SetIntFull
0
R/W
Compare Interrupt select (note 1)
0 ChTmDis
p 0*
R/W
Disable Test modes by setting it to 1 (MUST be DONE)
p 0* ChTmDis is cleared on POR to be able to enter test modes at EM. One of first instructions not to
enter test mode by mistake even if protocol to do it is difficult to achive is to set this bit to 1.
Because circuit starts itself with its ROM code also on tester user has to respect minimal number of
instructions before setting this bit to be able to test the circuit on tester.
Table 8.6.5. Number of instructions before cutting Test access
Min Nb. of instructions before ChTmDis is
CPU frequency
set or PortPA[0] declared as an output
Basic frequency (32 kHz or 50 kHz)
4
Basic f. x 2 ( 64 kHz or 100 kHz)
8
Basic f. x 4 ( 128 kHz or 200 kHz)
16
Basic f. x 8 ( 256 kHz or 400 kHz)
32
Basic f. x 16 ( 500 kHz or 800 kHz)
64
By writing to RegSysCntl1 – setting ChTmDis to 1 PORstatus will be cleared.
Test mode is totally disabled also if PortPA[0] is declared as an output. OenPA[0] = ‘1’
(note 1) Default : Interrupt on limited bit compare for Counter
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Table 8.6.6. Register RegCDataL, Counter/Compare Low Data Nibble
Bit
Name
Reset
R/W
3
CReg[3]
0
W
2
CReg[2]
0
W
1
CReg[1]
0
W
0
CReg[0]
0
W
3
Count[3]
0
R
2
Count[2]
0
R
1
Count[1]
0
R
0
Count[0]
0
R
Description
Counter data bit 3
Counter data bit 2
Counter data bit 1
Counter data bit 0
Data register bit 3
Data register bit 2
Data register bit 1
Data register bit 0
Table 8.6.7. Register RegCDataM, Counter/Compare Middle Data Nibble
Bit
Name
Reset
R/W
Description
3
CReg[7]
0
W
Counter data bit 7
2
CReg[6]
0
W
Counter data bit 6
1
CReg[5]
0
W
Counter data bit 5
0
CReg[4]
0
W
Counter data bit 4
3
ShCount[7]
0
R
Data register bit 7
2
ShCount[6]
0
R
Data register bit 6
1
ShCount[5]
0
R
Data register bit 5
0
ShCount[4]
0
R
Data register bit 4
Table 8.6.8. Register RegCDataH, Counter/Compare High Data Nibble
Bit
Name
Reset
R/W
Description
3
BitSel[1]
0
R/W
Bit select for limited bit count/compare
2
BitSel[0]
0
R/W
Bit select for limited bit count/compare
1
CReg[9]
0
W
Counter data bit 9
0
CReg[8]
0
W
Counter data bit 8
1
ShCount[9]
0
R
Data register bit 9
0
ShCount[8]
0
R
Data register bit 8
Table 8.6.9. Counter Length Selection
BitSel[1]
BitSel[0 ]
0
0
0
1
1
0
1
1
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counter length
10-Bit
8-Bit
6-Bit
4-Bit
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9. Supply Voltage Level Detector / 4-bit ADC
The EM6580 has a built-in circuitry made up of a comparator with band-gap reference and a resistor divider
chain with 16 terminals to detect levels from 0.5V to 2.75V with a step of 150mV. This can be used as:
a. Supply Voltage Level Detector (SVLD) to compare the positive power supply level Vdd (Vbat) against levels
which are in the range of Vddmin to Vddmax. There are 12 pre-selected levels in the range from 1.2 to 2.75V.
In this case ExtVcheck must be cleared to ‘0’ (default).
b. Simple 4-bit Analogue to Digital Converter – ADC. Setting the ExtVcheck bit to ‘1’ makes the PA[4] input
an analog ADC input. PA[4] input voltage must not exceed Vbat + 0.3V
In Sleep mode both functions are disabled.
Figure 21. SVLD / 4-bit ADC schematic with controls and timing
Supply Voltage Level Detector & 4-bit ADC function
SVLD level5 (1.25V) or SVLD level9 (1.85V) is used during Power On Reset for Power-Check to check the
minimum operating voltage before the POR signal is released as described in Chapter 4.1.
When used as a SVLD the ExtVCheck bit in register RegVldCntl must be cleared to ‘0’. Then Vdd (Vbat) is
selected as the input to the resistive divider which provides the comparator inputs. The SVLD level must be
selected by writing the RegSVLDlev register. For proper operation only levels from #4 to #15 can be selected.
Then the CPU activates the voltage comparison by writing the VLDstart bit to ‘1’ in the register RegVLDCntl.
The actual measurement starts on the next ck[14] (8kHz @ 32kHz SysClk) falling edge and lasts typ. 260 us.
The busy flag VldBusy stays high from the time VLDStart is set to ‘1’ until the measurement is finished. The
worst case time until the result is available is 3.125 * ck[14] prescaler clock periods (32kHz Æ 382us). See
figure 24 for details.
During the actual measurement (typ. 260us) the device will draw typically an additional 4цA of IVDD current @
Vdd=1.5V. After the end of the measurement an interrupt request IRQSvld can be generated if Vdd is lower than
the level which was selected. The interrupt is generated only if the MaskIRQSvld bit is set to ‘1’. The result is
available by inspection of the bit VLDResult. If the result is ’0’, then the power supply voltage was lower than
the detection level value. If ‘1’ the power supply voltage was higher than the detection level value. The value of
VLDResult is not guaranteed while VldBusy=1.
An interrupt can be generated only if Vdd(Vbat) is lower than the selected level. IRQSvld bit is cleared by reading
RegIRQ2.
0H
Table 9.1 register RegVldCntl
Bit
Name
Reset
R/W
Description
3
ExtVcheck
0
W
PA[4] as positive input of divider chain
3
VLDResult
0
R*
VLD result flag
2
VLDStart
0
W
VLD start command
2
VLDBusy
0
R
VLD busy flag is on Until compare is finished
1
SVLDen
0
R/W
SVLD comparator is On continuously
0
NoWDtim
p
R/W
No watchdog timer
R*; VLDResult is not guaranteed while VLDBusy=1
Figure 22. SVLD timing
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The VLDresult bit from the previous measurement stays in the register until the new measurements is finished.
For good measurements external noise or CPU activity should be as low as possible during the comparison.
Table 9.2 register RegSVLDlev
Bit
3
2
1
0
Name
SVLDlev[3]
SVLDlev[2]
SVLDlev[1]
SVLDlev[0]
POR
0
1
0
1
R/W
R/W
R/W
R/W
R/W
Description
SVLD level select bit #3
SVLD level select bit #2
SVLD level select bit #1
SVLD level select bit #0
Table 9.3 SVLD level selection (typical values VSVLDNom)
SVLDlev[3:0]
MSB
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LSB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Nb.:
Level #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADC
SVLD
ADCNom SVLDNom
0.5 V
Do not set
0.65 V
Do not set
0.80 V
Do not set
0.95 V
Do not set
1.10 V
Do not set
1.25 V
Do not set
1.40 V
Do not set
1.55 V
Do not set
1.70 V
Do not set
1.85 V
Do not set
2.00 V
2.00 V
2.15 V
2.15 V
2.30 V
2.30 V
2.45 V
2.45 V
2.60 V
2.60 V
2.75 V
2.75 V
Description of specialitis
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Do not use this level with SVLD
Default level after POR for Power Check
External source is coming from PA[4] as explained in Chapter 2 and shown on figure 10.
To implement a 4-bit ADC first ExtVcheck bit must be set to ‘1’, that PA[4] input is connected to positive side of
resistor divider chain. To find the level as fast as possible with successive approximation for instance it is
advised to Set SVLDen bit to ‘1’ to have comparator and resistive divider chain operational all the time when
the PA[4] input is sampled with ck[15] (typ. 16kHz @ 32kHz SysClk) frequency. With SVLDlev[3:0] we can
select one of 16 possible levels to check and by making max. 4 measurements at 4 different levels (if input
PA[4] is stable) we have the result with successive approximation method.
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In this case PA[4] input is blocked for all other functions, because its level can be in a zone where logic ‘0’ or ‘1’
are not well defined and this would generate an over consumption otherwise. So it is dedicated only to SVLD
comparator input to be compared with internal band-gap reference. NoPullPA[4] must be set to ‘1’ - PullUP/Down must be removed by register also.
In both cases if Vbat (Vdd) or PA[4] level is tested than if selected tested level lower an IRQ can be generated if
enabled.
With SVLDen bit one can switch on the band-gap, resistive divider and Comparator continuously. Like that one
can monitor Vbat or PA[4] level continuously, at higher frequency (ck[15]). Only at the beginning after setting
the SVLDen at ‘1’ one has to wait until VLDbusy drops to ‘0’ indicating that system is powered up (band-gap
reference and resistor divider are stabilized and comparator is ready to give proper result). This will increase
power consumption by typ. 4цA @ Vdd=1.5V while used.
During continuously monitoring one can change RegSVLDlev register value on fly and the new result should
be read only after about 1.5 * ck[15] to be sure it is a result of a new SVLDlev selection. Depending on CPUclk
and divisions to obtained SysClk this can be 2 / 6 / 10 / 20 / 36 instruction after RegSVLDlev change for
multiples by 1 / 2 / 4 / 8 / 16.
When fast monitoring is not necessary any more one can remove it by clearing SVLDen to ‘0’.
When SVLD logic is used for this fast monitoring IRQ can also be generated when checked level falls below its
value.
Figure 23. SVLD timing in “ADC” mode when SVLDen set @ “1”
Due to IRQSvld which can come very fast – with ck[15] there is danger that immediately after coming out from
IRQ subroutine new IRQSvld which came during that time put uC back in IRQ subroutine and software can be
stacked at this place until checked input is lower then SVLD level. Otherwise IntEn register must be cleared in
IRQ subroutine already !! or even better to use this function by reading the SVLD result only and not setting the
MaskIRQSvld.
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10. ADC/SVLD Comparator characteristics
tested level
band-gag (360mV)
Level
- comparator hyst.
Comparator output
Comparator hysteresis is adaptive in 4 steps controlled by MSB of RegSVLDlev register to cover all tested
levels from 0.5V to 3.0V to give a typ. “tested level” hysteresis of 40mV.
Negative hysteresis on comparator is implemented to eliminate comparator output oscillation arround switching
point.
11. RAM
The EM6580 has one 80x4 bit static RAM built-in located on addresses hex 0 to 4F. All the RAM nibbles are
direct addressable.
Figure 24. RAM Architecture
RAM 80 x 4 = direct addressable
Adr [hex]
RAM location
4F
RAM_79
4E
RAM_78
4D
RAM_77
4B
RAM_76
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
04
03
02
01
00
RAM_04
RAM_03
RAM_02
RAM_01
RAM_00
Read / Write
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
.
.
.
.
.
.
.
.
.
.
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
RAM Extension : Unused R/W Registers can often be used as possible RAM extension. Be careful not to use
registers which start, stop, or reset some functions.
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12. Interrupt Controller
The EM6580 has 8 different interrupt request sources masked individually. These are:
External (2)
- Port A,
- Compare
PA[0/5] and PA[3/4] inputs
PA[4] input
Internal (6)
- Prescaler (2x)
- 10-bit Counter (2x)
- SVLD (1)
- Serial Interface (1)
ck[1], 64Hz/8Hz
Count0, CountComp
End of measure when level is low
8 bit transfered
The SVLD and the PA[4] level check share the same interrupt line.
Serial Interface could be put under Internal when Serial clock is coming form EM6580 or External when Serial
clock is external.
To be able to send an interrupt to the CPU, at least one of the interrupt request flags must be set (IRQxx) and
the general interrupt enable bit IntEn located in the register RegSysCntl1 must be set to 1. The interrupt
request flags can only be set by a positive edge of IRQxx with the corresponding mask register bit
(MaskIRQxx) set to 1.
Figure 25. Interrupt control logic for generating and clearing interrupts
Interrupt control logic
At power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any
interrupt request to be stored. Also the general interrupt enable IntEn is set to 0 (No IRQ to CPU) by reset.
After each read operation on the interrupt request registers RegIRQ1 or RegIRQ2 the contents of the
addressed register are reset. Therefore one has to make a copy of the interrupt request register if there was
more than one interrupt to treat. Each interrupt request flag may also be reset individually by writing 1 into it
(ClrIntBit).
Interrupt handling priority must be resolved through software by deciding which register and which flag inside
the register need to be serviced first.
Since the CPU has only one interrupt subroutine and because the IRQxx registers are cleared after reading,
the CPU does not miss any interrupt request which comes during the interrupt service routine. If any occurs
during this time a new interrupt will be generated as soon as the software comes out of the current interrupt
subroutine.
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their
corresponding mask setting and not on the general interrupt enable status. Whenever the EM6580 goes into
HALT Mode the IntEn bit is automatically set to 1, thus allowing to resume from Halt Mode with an interrupt.
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12.1 Interrupt control registers
Table 12.1.1 Register RegIRQ1
Bit
Name
Reset
R/W
3
IRQCount0
0
R/W*
2
IRQCntComp
0
R/W*
1
IRQPA[3/4]
0
R/W*
0
IRQPA[0/5]
0
R/W*
W*; Writing of 1 clears the corresponding bit.
Description
Counter interrupt request when at 0
Counter interrupt request when compare True
Port A PA[3/4] interrupt request
Port A PA[0/5] interrupt request
Table 12.1.2 Register RegIRQ2
Bit
Name
Reset
R/W
3
IRQHz1
0
R/W*
2
IRQHz64/8
0
R/W*
1
IRQSvld
0
R/W*
0
IRQSerial
0
R/W*
W*; Writing of 1 clears the corresponding bit.
Description
Prescaler interrupt request of 1Hz
Prescaler interrupt request of 64 Hz or 8 Hz
SVLD or Compare interrupt request
Serial interface interrupt request
Table 12.1.3 Register RegIRQMask1
Bit
Name
Reset
R/W
3
MaskIRQCount0
0
R/W
2
MaskIRQCntComp
0
R/W
1
MaskIRQPA[3/4]
0
R/W
0
MaskIRQPA[0/5]
0
R/W
Interrupt is not stored if the mask bit is 0.
Description
Counter when at 0 interrupt mask
Counter compare True interrupt mask
Port A PA[3/4] interrupt mask
Port A PA[0/5] interrupt mask
Table 12.1.4 Register RegIRQMask2
Bit
Name
Reset
R/W
3
MaskIRQHz1
0
R/W
2
MaskIRQHz64/8
0
R/W
1
MaskIRQSvld
0
R/W
0
MaskIRQSerial
0
R/W
Interrupt is not stored if the mask bit is 0.
Description
Prescaler 1Hz interrupt mask
Prescaler 64 Hz or 8 Hz interrupt mask
SVLD or Compare interrupt mask
Serial interface interrupt mask
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13. PERIPHERAL MEMORY MAP
Reset values are valid after power up or after every system reset.
Register
Name
Ram1_0
Ram1_63
Add Add
Hex Dec.
00
4F
0
79
Reset
Value
b'3210
xxxx
xxxx
RegPA0
50
80
0000
RegPa0OE
51
81
0000
0 = after
PORend
RegPaCntl1
52
82
pppp
p = POR
RegPaCntl2
53
83
pppp
p = POR
Pa0noPDown
54
84
pppp
p = POR
Pa0NchOpenDr
55
85
pppp
p = POR
RegFreqRst
56
86
ppxx
RegSCntl1
57
87
0000
RegSCntl2
58
88
0000
RegSDataL
59
89
0000
RegSDataH
5A
90
0000
RegCCntl1
5B
91
0000
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Read Bits
Write Bits
Remarks
Read / Write Bits
0: Data0
1: Data1
2: Data2
3: Data3
0: Data0
1: Data1
2: Data2
3: Data3
0: PA[0]
0: PAout[0]
1: PA[1]
1: PAout[1]
2: PA[2]
2: PAout[2]
3: PA[3]
3: PAout[3]
0: OEnPA[0]
1: OEnPA[1]
2: OEnPA[2]
3: OEnPA[3]
0: EdgeFallingPA[0/5]
1: EdgeFallingPA[3/4]
2: debunceNoPA[0/5]
3: debunceNoPA[3/4]
0: IrqPA[0l/5h]
1: IrqPA[3l/4h]
2: WUchEnPA[0/5]
3: WUchEnPA[3/4]
0: NoPdPA[0]
1: NoPdPA[1]
2: NoPdPA[2]
3: NoPdPA[3]
0: NchOpDrPA[0]
1: NchOpDrPA[1]
2: NchOpDrPA[2]
3: NchOpDrPA[3]
0: foutSel[0]
1: foutSel[1]
2: PA[3/4]resIn
3: InResAH
0: MSBnLSB
1: POSnNeg
2: MS0
3: MS1
0: OM[0]
1: RCoscOff
2: Status
3: Start
0: SerDataL[0]
1: SerDataL[1]
2: SerDataL[2]
3: SerDataL[3]
0: SerDataH[0]
1: SerDataH[1]
2: SerDataH[2]
3: SerDataH[3]
0: CountFSel0
1: CountFSel1
2: CountFSel2
3: Up/Down
40
Direct addressable
Ram 80 x 4 bit
Direct addressable
Ram 80 x 4 bit
PortA [3:0]
Direct input read,
Output data register
PortA [3:0]
Output enable active Hi,
PortA [3:0] control1
Debounce Yes/No &
Faling / Rising edge
PortA [3:0] control2
WakeUp on change enable &
Irq source from PA select
Option register
Pull/down selection on PA[3:0]
Default : pull-down ON
Option register
N/channel Open Drain
Output on PA[3:0]
Default : CMOS output
Output Frequency select
and Input reset Control
Serial interface
control 1
Serial interface
control 2
Serial interface
low data nibble
Serial interface
high data nibble
10-bit counter
control 1;
frequency and up/down
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EM6580
Register
Name
Add Add
Hex Dec.
Reset
Value
b'3210
RegCCntl2
5C
92
0000
RegCDataL
5D
93
0000
RegCDataM
5E
94
0000
RegCDataH
5F
95
0000
RegPA1
60
96
p000
RegPaCntl3
61
97
pppp
RegPaCntl4
62
98
ppPP
RegIRQMask1
65
101
0000
RegIRQMask2
66
102
0000
RegIRQ1
67
103
0000
REgIRQ2
RegSysCntl1
68
69
104
105
0000
000p
p = POR
RegSysCntl2
6A
106
Pp00
p = POR
RegSleepCR
6B
107
pppp
p = POR
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Read Bits
Write Bits
Remarks
Read / Write Bits
0: '0'
0: Load
1: EnComp
1: EnComp
2: EvCount
2: EvCount
3: Start
3: Start
0: Count[0]
0: CReg[0]
1: Count[1]
1: CReg[1]
2: Count[2]
2: CReg[2]
3: Count[3]
3: CReg[3]
0: Count[4]
0: CReg[4]
1: Count[5]
1: CReg[5]
2: Count[6]
2: CReg[6]
3: Count[7]
3: CReg[7]
0: Count[8]
0: CReg[8]
1: Count[9]
1: CReg[9]
2: BitSel[0]
2: BitSel[0]
3: BitSel[1]
3: BitSel[1]
0: PA[4]
0: -1: PA[5]
1: PAout[5]
2: OEnPA[5]
2: OEnPA[5]
3: NchOpDrPA[5]
3: NchOpDrPA[5]
0: PWMoutPA[0]
1: PWMoutPA[1]
2: SerialCkPA [1]
3: SerialStPA [3]
0: freqOutPA[2]
1: Sout/rstPA[2]
2: : freqOutPA[5]
3: NoPdPA[5]
0: MaskIRQPA[0/5]
1: MaskIRQPA[3/4]
2: MaskIRQCntComp
3: MaskIRQCount0
0: MaskIRQSerial
1: MaskIRQSvld
2: MaskIRQHz64/8
3: MaskIRQHz1
0: IRQPA[0/5]
0:RIRQPA[0/5]
1: IRQPA[3/4]
1:RIRQPA[3/4]
2: IRQCntComp
2:RIRQCntComp
3: IRQCount0
3:RIRQCount0
0: IRQSerial
0:RIRQSerial
1: IRQSvld
1:RIRQSvld
2: IRQHz64/8
2:RIRQHz64/8
3: IRQHz1
3:RIRQHz1
0: ChTmDis
0: ChTmDis
1: SelIntFull
1: SelIntFull
2: '0'
2: Sleep
3: IntEn
3: IntEn
0: WDVal0
0: -1: WDVal1
1: -2: SleepEn
2: SleepEn
3: PORstatus
3: WDReset
0: SCRsel0
1: SCRsel1
2: SleepCntDis
3: NoPullPA[4]
41
10-bit counter control 2;
comparison, event counter and start
10-bit counter
data low nibble
10-bit counter
data middle nibble
10-bit counter
data high bits
PortA [5:4]
Direct input read,
Output data register with
Output enable active Hi
PortA Control3
Output distribution on PA[0], PA[1]
and PA[3]
PortA Control4
Output distribution on PA[2]
and PA[5]
Port A & Counter
interrupt mask;
masking active 0
Prescaler, SVLD & serial interf.
interrupt mask;
masking active low
Read: port A & Counter interrupt
Write: Reset IRQ if data bit = 1.
Read: Prescaler, SVLD & serial
interface interrupt.
Write: Reset IRQ if data bit = 1
System control 1;
ChTmDis only usable only for EM
test modes
System control 2;
watchdog value and periodical reset,
enable sleep mode
Sleep Counter reset control
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EM6580
Register
Name
Add Add
Hex Dec.
Reset
Value
b'3210
RegPresc
6C
108
0000
IXLow
6E
110
xxxx
IXHigh
6F
111
xxxx
RegVldCntl
73
115
000p
RegSVLDlev
74
116
PpPp
RegOscTrimH
75
117
pPPP
RegOscTrimL
76
118
PPPP
RegMFP0
79
121
pppp
RegMFP1
7A
122
pppp
RegMFP2
7B
123
pppp
7C
124
xxxx
7D
125
xxxx
RegTestEM1
7E
126
pppp
RegTestEM2
7F
127
pppp
Read Bits
Write Bits
Remarks
Read / Write Bits
0: DebSel
1: PrIntSel
2: '0'
3: ExtCPUclkON
0: DebSel
1: PrIntSel
2: ResPresc
3: ExtCPUclkON
0: IXLow[0]
1: IXLow[1]
2: IXLow[2]
3: IXLow[3]
0: IXHigh[4]
0: IXHigh[4]
1: IXHigh[5]
1: IXHigh[5]
2: IXHigh[6]
2: IXHigh[6]
3: '0'
3: -0: NoWDtim
0: NoWDtim
1: SVLDen
1: SVLDen
2: VldBusy
2: VldStart
3: VldResult
3: ExtVcheck
0: SVLDlev[0]
1: SVLDlev[1]
2: SVLDlev[2]
3: SVLDlev[3]
0: RegOsctrim[4]
1: RegOsctrim[5]
2: RegOsctrim[6]
3: RegOsctrim[7]
0: RegOsctrim[0]
1: RegOsctrim[1]
2: RegOsctrim[2]
3: RegOsctrim[3]
0:Opt[0]
1:Opt[1]
2:Opt[2]
3:Opt[3]
0:Opt[4]
1:Opt[5]
2:Opt[7]
3:Opt[7]
0:Opt[8]
1:
2:
3:
Prescaler control;
Debouncer, prescaler interrupt
select and reset,
External CPU clock enable
Internal µP index
register low nibble;
for µP indexed addressing
Internal µP index
register high nibble;
for µP indexed addressing
Voltage level
detector & RC osc. control
SVLD test voltage level select
Oscillator trimming word, MSB
Oscillator trimming word, LSB
PA4 pull up/down selection
Counter clock option
Serial Interface clock
Debouncer clock
RC frequency base selection
RC frequency selection
RC frequency selection
RC frequency selection
ADC/SVLD level #15 selection
Reserved for EM6680 software
compatibility.
Reserved for EM6680 software
compatibility.
0: Tmsel[0]
1: Tmsel[1]
2: Tmsel[2]
3: disablePOR
0: OeTm0
1: OeTm1
2: TestResSys
3: TestPOR
For EM test only
For EM test only
p = defined by POR at ‘0’ (power on reset) only
P = defined by POR at ‘1’ (power on reset) only
x = undefined state by reset (register must be written before used)
RegTestEm1 and RegTestEm2 can be written only if ChTmDis in RegSysCntl1 is ‘0’. They are used for EM
test only and are Write only. To prevent entering test mode in normal operation one has to set the ChTmDis bit
to ‘1’ as soon as possible after reset. It should be one of first instructions.
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EM6580
14. Mask Options
Mask option are available on the EM6680, on EM6580 options are accessible through specific registers that are
only present into the EM6580. These registers are name RegMFPn (n 0,1,2 and 3) and are mapped within a
free range addresses, from address 75h to 7Bh
14.1 Port A Metal Options
Table 14.1.1 Pull-down Metal mask Options
Strong
Description
Weak
Pull-down
Pull-down
Option Name
MAPD[5]
MAPD[4]
MAPD[3]
MAPD[2]
MAPD[1]
MAPD[0]
1
PA[5] input pull-down
PA[4] input pull-down
PA[3] input pull-down
PA[2] input pull-down
PA[1] input pull-down
PA[0] input pull-down
2
R1 Value
Typ.100k
3
NO
Pull-Down
4
100k
100k
100k
100k
100k
100k
X
X
X
X
X
X
NO pull down option is already software controllable with register as in the EM6680.
Table 14.1.2 Pull-up Metal mask Options
Strong
Description
Weak
Pull-up
Pull-up
Option Name
MAPU[5]
MAPU[4]
MAPU[3]
MAPU[2]
MAPU[1]
MAPU[0]
1
PA[5] input pull-up
PA[4] input pull-up
PA[3] input pull-up
PA[2] input pull-up
PA[1] input pull-up
PA[0] input pull-up
2
R1 Value
Typ.100k
3
NO
Pull-up
4
100k
100k
100k
100k
100k
100k
X
X
X
X
X
X
NO pull up option is already software controllable with register as in the EM6680.
PA[4] pull -up pull-down selection can be down with regMFP0 Opt[0].
14.2 RC oscillator Frequency Option
Option
Name
Description
User
Default
Value
Value
A
B
RC osc Frequency
RCfreq
32 kHz
By default the RC oscillator frequency is typ. 32 kHz With option RCfreq. Other possibilities are: 64kHz,
128kHz, 256kHz and 512kHz or 50kHz, 100kHz, 200kHz, 400kHz or max. 800kHz .
RC frequency selection is done with register regMFP1 Opt[7:4]
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EM6580
14.3 Debouncer Frequency Option
Option
Name
Description
User
Default
Value
Value
A
B
Debouncer freq.
MDeb
Ck[11]
By default the debouncer frequency is Ck[11]. The user may choose Ck[14] instead of Ck[11].
Ck[14 ]corresponds to maximum 0.25ms debouncer time in case of a 32kHz System Clock – SysClk.
Debouncer Frequency is selected with register RegMFP0 Opt[3].
14.4 Power-Check Level Option
Option
Name
Description
PClev.
Power-Check level
Default
Value
A
2.00
User
Value
B
NA
The power check level is fixed at 2V (Typ) v in order to guarantee a proper working of the Flash memory.
14.5 ADC/SVLD Voltage Level #15
Option
Name
Description
HisvldLev. ADC/SVLD lev.#15
Default
Value
A
2.75V
User
Value
B
By default the ADC/SVLD Voltage Level #15 is at 2.75V but user can select also the second possibility which is
3.0V and does not influence on other ADC/SVLD levels.
Selection is done with register RegMFP2 Opt[0].
14.6 Counter Update option
Option
Name
CntF
Counter Reg. level
Default
Value
A
SysClk
User
Value
B
By default the counter is updated by Sysclk (32 or 50kHz typ) and the highest counter frequency is Sysclk/2 (16
or 25kHz Typ). The other possibility is to select RCclk for counter update freq. Which gives a possibility to
replace port A input at selection 7 by RC/2. If DebouncerNoPA[3/4] in RegPACntl[1] is ‘1’ then the resulting
clock on timer selection 7 is CPUClk divided by 4. If DebouncerNoPA[3/4] is ‘0’ then the resulting clock is
CpuClk/2 directly.
Counter Update Option selection is done with register RegMFP0 Opt[1]
14.7 Voltage Regulator level option
Name
LevelReg
Voltage Reg. level
Default User
Value
Value
A
B
2T/W NA
This is not an option any more.
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EM6580
14.8 Additional registers compare to EM6680
This paragraph describe new registers with respect to EM6680. These registers are the substitute of metal
options we can find on the EM6680.
Register RegOscTrimH
Bit
Name
3
RegOscTrim[7]
2
RegOscTrim[6]
1
RegOscTrim[5]
0
RegOscTrim[4]
@ addr. 117 decimal = 75 hex.
Reset
R/W
Description
0
R/W
Oscillator trimming register, MSB
1
R/W
1
R/W
1
R/W
Register RegOscTrimL
Bit
Name
3
RegOscTrim[3]
2
RegOscTrim[2]
1
RegOscTrim[1]
0
RegOscTrim[0]
@ addr. 118 decimal = 76 hex.
Reset
R/W
Description
1
R/W
Oscillator trimming register, LSB
1
R/W
1
R/W
1
R/W
Register RegMFP0
Bit
Name
3
Opt[3]
2
Opt[2]
1
Opt[1]
@ addr. 121 decimal = 79 hex.
Reset
R/W
Description
0
R/W
Debouncer clock select “0” = ck[11], “1”=ck[14]
0
R/W
Must be remain to “0”
0
R/W
Counter Clock source 7 selection
"0" PA3/PA4, "1" RCclk/2
0
R/W
PA4 Pull up/Pull down selection, "0" P-down, "1" P-up
0
Opt[0]
Note1. bit1: When Opt[1]=1 the clock of the counter is no more ck16 (32kHz/50kHZ) but the CPU clock in
order to achieve a correct sampling of the RCclk/2 signal.
@ addr. 122 decimal = 7A hex.
Register RegMFP1
Bit
Name
Reset
R/W
Description
3
Opt[7]
0
R/W
RC base frequency (32/50 kHz) selection.
2
Opt[6]
0
R/W
RC frequency selection bit 2
1
Opt[5]
0
R/W
RC frequency selection bit 1
0
Opt[4]
0
R/W
RC frequency selection bit 0
Register RegMFP2
Bit
Name
3
Opt[11]
2
Opt[10]
1
Opt[9]
0
Opt[8]
@ addr. 123 decimal = 7B hex.
Reset
R/W
Description
?
R/W
?
R/W
?
R/W
0
R/W
ADC/SVLD voltage level#15: "0" 2.75v, "1" 3v
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EM6580
15. RC Oscillator
The oscillator is able to generate 2 main frequencies, 800kHz and 512kHz, then through a division chain
generates the 12 possible frequencies of EM6680 chip. The frequency selection as opposed to EM6680 in
done with registers, RegMFP1.
RegOscTrim1
[3:0]
trimming
bus [7:0]
RegOscTrim2
[3:0]
Base frequency
selection
Selected
trimmed
frequency
0
RC Oscillator
Special 4 stages divider
1
/2
/4
/8
Frequency
divider
/2 /4 /8 /16
Frequency divider
rate selection
RegMFP1[3] RegMFP1[2:0]
RegPresc[3]
ExtCPUclkON
External
Clock
RC Osc.
512kHz/ 800kHz
Selected
divided
frequency
CPU clock frequency
RCCLK
/16
Peripherals clock frequency
SysCLK
automatically
set at 32 or 50kHz
RegMFP1[2:0]
PRESCALER
LOW 15 stage divider
Uses to
cadence all
peripherals
Figure 26: Oscillator architecture
15.1 Frequency selection
After power up the oscillator runs at 32 kHz, frequency switching is done by the software thanks to a register.
This frequency switching has to be done in a way it guarantees a proper working of the microcontroller.
RC Oscillator frequency selection. RegMFP1[3:0]
RegMFP1[3] RegMFP1[2] RegMFP1[1] RegMFP1[0]
Opt[7]
Opt[6]
Opt[5]
Opt[4]
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
Frequency of RCclk
Unit
32.00
64.00
128.00
256.00
512.00
50.00
100.00
200.00
400.00
800.00
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
RegMFP1[3] bit selects the base frequency, 512kHz or 800kHz.
RegMFP1[2:0] bit select the frequency divider rate, 1, 2, 4, 8, 16.
When the RC frequency is changed the system clock, sysClk, has to be as close as possible to 32/50 kHz
thanks to frequency dividers.
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EM6580
15.2 Oscillator Trimming
The internal oscillator circuit is designed for use with no external components to provide a clock source with
tolerance less than ±25%. Two 4-bit registers, RegOscTrimH and RegOscTrimL allow adjustment to a
tolerance less than ±5%. The default value of the trimming register is 7Fh allowing a frequency adjustment
from –127 steps to +128 steps around this central value. Increasing the trimming register increases the
frequency of the oscillator.
Reserved Flash location, 32 words at the end of the flash memory, contains the value of the trimming and the
function allowing to load the register with the trimming value since the 4-bit microcontroller core does not have
indirect addressing to code space.
EM6580 Flash Memory is splitted in two areas. First area (Sector 1) contains the main application code
whereas the second are (Sector 2) contains specific trimming code for the RC oscillator. Manufactory trimming
code for 512kHz and 800kHz frequencies are defined as follow :
Address
Memory area
0000H
Sector 1
Application code
area
0FDFH
Address
0FE0H
.
.
.
0FE0H
0FE1H
0FE2H
Sector 2
Trimming code
area
0FE3H
0FE4H
0FE5H
Op-codes
; 512kHz Trimming function
STI
RegOscTrimH, 0xH
STI
RegOscTrimL, 0xH
RET
; 800kHz Trimming function
STI
RegOscTrimH, 0xH
STI
RegOscTrimL, 0xH
RET
0FFFH
Cx75
Cx76
FA7F
Cx75
Cx76
FA7F
x represents the trimming value
(differ from chip to chip)
To be able to use this routine, you need to define two constants which define the Trimming code location for
each trim routine.
Trim_osc_base_512kHz
Trim_osc_base_800kHz
EQU 4064
EQU 4067
(0FE0H)
(0FE3H)
If you need to use trimming for your the application, just use a call instruction to trim the RC oscillator at the
correct frequency.
CALL
Trim_osc_base_512kHz
or
CALL
Trim_osc_base_800kHz
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EM6580
16. Unique ID Code / serial number
A unique ID code is included into the sector 2 of the flash memory during the manufacturing tests. Thanks to
this unique code, the EM6580 is suitable for applications such as for instance logistics and tracking.
This code is made of 52 bits unique code and 16 bits CRC for validation, see definition underneath:
Address
Memory area
0000H
Sector 1
Application code
area
0FDFH
0FE0H
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0FFFH
Address
0FE6H
0FE7H
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
0FEDH
0FEEH
0FEFH
0FF0H
0FF1H
0FF2H
0FF3H
0FF4H
0FF5H
0FF6H
0FF7H
Sector 2
area
Op-codes
Cx3F
STI
3FH,0xH ; CRC4 (checksum)
Cx40
STI
40H,0xH ; CRC3 (checksum)
Cx41
STI
41H,0xH ; CRC2 (checksum)
Cx42
STI
42H,0xH ; CRC1 (checksum)
Cx43
STI
43H,0xH ; KHH (tester N° High nibble)
Cx44
STI
44H,0xH ; KLH (tester N° Low nibble)
Cx45
STI
45H,0xH ; MH (Month of the test)
Cx46
STI
46H,0xH ; DHH (Day of test High nibble)
Cx47
STI
47H,0xH ; DLH (Day of test Low nibble)
Cx48
STI
48H,0xH ; YHH (Year of test High nibble)
Cx49
STI
49H,0xH ; YLH (Year of test Low nibble)
Cx4A
STI
4AH,0xH ; HHH (Hour of test High nibble)
Cx4B
STI
4BH,0xH ; HLH (Hour of test nibble)
Cx4C
STI
4CH,0xH ; MHH (Minute of test High
Cx4D
nibble)
STI
4DH,0xH ; MLH (Minute of test Low nibble) Cx4E
STI
4EH,0xH ;SHH (Second of test High nibble) Cx4F
FA7F
STI
4FH,0xH ; SLH (Second of test Low
nibble)
RET
x represents the ID code value (unique for each chip)
To be able to use this routine, one needs to define a constant which define the date code location to restore the
ID code into the ram address 3FH to 4FH.(The polynomial for the checksum can be provide to customer on
request.)
Date_Code
EQU
4070
(0FE6H)
If you need to use the ID unique code in your application, just use a call instruction to the date_code label as
follow :
CALL
Date_Code
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17. Temperature and Voltage Behaviour
17.1 IDD current (Typical)
Idd RUN vs. temperature
80
5.5V
3.0V
2.0V
Idd[uA]
60
40
Idd[uA]
Idd RUN vs. frequency
20
0
0
200
400
600
800
-40.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
-20.00
0.00
Frequency [kHz]
Idd[uA]
4.000
2.000
0.000
300
20.00
40.00
60.00
80.00
100.00
400
500
-40
600
-20
f=800kHz
f=512kHz
f=256kHz
f=32kHz
0
Frequency [kHz]
20
40
60
80
100
Temperature[°C]
Idd SLEEP vs. temperature
Idd HALT vs. frequency, 800kHz base
5.5V
3.0V
2.0V
8.000
500
400
Idd[nA]
6.000
Idd[uA]
f=32kHz
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
Idd[uA]
5.5V
3.0V
2.0V
6.000
200
f=400kHz
Idd HALT vs. temperature
8.000
100
f=512kHz
Temperature[°C]
Idd HALT vs. frequency, 512kHz base
0
f=800kHz
4.000
5.5V
3.3V
2.0V
300
200
2.000
100
0.000
0
0
200
400
600
800
-40
Frequency [kHz]
Copyright © 2006, EM Microelectronic-Marin SA
-20
0
20
40
60
80
100
Temperature[°C]
49
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EM6580
17.2 Pull-up and Pull-down resistors (Typical)
Pull-down Resistor vs. VDD
500
200
400
150
300
95°C
25°C
-30°C
200
100
Rpu[kohm]
Rpu[kohm]
Pull-up Resistor vs. VDD
95°C
25°C
-30°C
100
0
50
0
1.8
2.8
3.8
4.8
5.8
1.8
2.8
3.8
VDD[V]
4.8
5.8
VDD[V]
17.3 Output current (Typical)
Output buffer current on PA0 vs. tem perature
Tem perature[°C]
80
60
80
-20
100
2.0V
3.0V
5.5V
60
IOL[mA]
IOH[mA]
-40
Tem perature[°C]
0
-20
0
20
40
-10
Output buffer current on PA0 vs. tem perature
5.5V
3.0V
2.0V
40
20
0
-40
-30
-20
0
20
40
60
80
VOH=VDD-1.0V
VOL=1.0V
Output buffer current on PA1 vs. tem perature
Output buffer current on PA1 vs. tem perature
Tem perature[°C]
150
60
80
100
2.0V
3.0V
5.5V
-20
-30
IOL[mA]
IOH[mA]
-40
Tem perature[°C]
0
-20
0
20
40
-10
100
5.5V
3.0V
2.0V
50
0
-40
-40
-20
0
20
40
60
80
VOH=VDD-1.0V
60
80
-20
-30
100
2.0V
3.0V
5.5V
Output buffer current on PA3 vs. tem perature
IOL[mA]
IOH[mA]
-40
-40
-40
VOH=VDD-1.0V
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100
VOL=1.0V
Output buffer current on PA3 vs. tem perature
Tem perature[°C]
0
-20
0
20
40
-10
100
Tem perature[°C]
100
80
60
40
20
0
-20
0
20
40
5.5V
3.0V
2.0V
60
80
100
VOL=1.0V
50
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EM6580
17.4 Oscillator Frequency (Typical)
Calibrate d RC oscillator with 512kHz base fre que ncy
v s. te mpe rature
Calibrate d RC oscillator with 800kHz base fre que ncy
v s. te mpe rature
6.00%
6.00%
4.00%
4.00%
-40
0.00%
-20
-2.00% 0
V D D =5.7V
20
40
60
80
-4.00%
100
-40
V D D =3.0V
0.00%
-20
-2.00% 0
20
40
Te m pe ra ture [°C]
60
80
100 V D D =3.0V
V D D =1.9V
-4.00%
V D D =1.9V
Copyright © 2006, EM Microelectronic-Marin SA
V D D =5.7V
2.00%
df/f
df/f
2.00%
Te m pe ra ture [°C]
51
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EM6580
18. Electrical Specification
18.1 Absolute Maximum Ratings
Min.
- 0.2
VSS – 0.2
- 40
-2000
Power supply VDD-VSS
Input voltage
Storage temperature
Electrostatic discharge to
Mil-Std-883C method 3015.7 with ref. to VSS
Maximum soldering conditions
Packages are Green-Mold and Lead-free
Max.
+ 6.0
VDD+0.2
+ 125
+2000
Units
V
V
°C
V
As per Jedec J-STD-020C
Stresses above these listed maximum ratings may cause permanent damage to the device.
Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction.
18.2 Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions
should be taken as for any other CMOS component.
Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply
voltage range.
18.3 Standard Operating Conditions
Parameter
Temperature
VDD _Range1
VDD _Range2
Vreg
VPP
Cext
MIN
-20
2.0
2.7
TYP
25
3.0
3.0
1.9
15
MAX
85
5.5
3.3
470
Unit
°C
V
V
V
V
nF
Description
Application working range
Flash programming range
Regulated Voltage
High Voltage for Flash programming
External capacitor on Vreg port
18.4 DC Characteristics - Power Supply
Conditions: T=25°C, Frequency 32kHz
Parameter
POR static level
Power-Check level
RAM data retention
Conditions
-20 to 85°C
-20 to 85°C
Symbol
VPOR
VPC
Vrd1
Min.
1.68
1.0
Typ.
1.50
2.00
Max.
1.80
2.30
Unit
V
V
V
Typ.
5.8
Max.
7.0
8.0
4.5
5.5
0.6
1.5
Unit
μA
μA
μA
μA
μA
μA
Max.
75
100
7.5
8.5
0.6
1.5
Unit
μA
μA
μA
μA
μA
μA
Conditions: Vdd =3.0V, Frequency 32kHz
Parameter
ACTIVE Supply Current
STANDBY Supply Current
SLEEP Supply Current
Conditions
25°C
-20 to 85°C
25°C
-20 to 85°C
25°C
-20 to 85°C
Symbol
IVDDa2
IVDDa2
IVDDh2
IVDDh2
IVDDs1
IVDDs2
Min.
Symbol
IVDDa2
IVDDa2
IVDDh2
IVDDh2
IVDDs1
IVDDs2
Min.
3.3
0.32
Conditions: VDD=3.0V, Frequency = 800kHz
Parameter
ACTIVE Supply Current
STANDBY Supply Current
SLEEP Supply Current
Copyright © 2006, EM Microelectronic-Marin SA
Conditions
25°C
-20 to 85°C
25°C
-20 to 85°C
25°C
-20 to 85°C
52
Typ.
56
6.1
0.32
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EM6580
18.5 Supply Voltage Level Detector
Conditions: Vdd =3.0V, T=25°C, rising signal on PA[4] and VDD.
Parameter
ADC voltage Level0
ADC voltage Level1
ADC voltage Level2
ADC voltage Level3
ADC voltage Level4
ADC voltage Level5
ADC voltage Level6
ADC voltage Level7
ADC voltage Level8
ADC voltage Level9
ADC/SVLD voltage Level10
ADC/SVLD voltage Level11
ADC/SVLD voltage Level12
ADC/SVLD voltage Level13
ADC/SVLD voltage Level14
ADC/SVLD voltage Level15
ADC/SVLD voltage Level15b
ADC/SVLD negative hysteresis
Conditions
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
ADC input impedance
Symbol
VVLD0
VVLD1
VVLD2
VVLD3
VVLD4
VVLD5
VVLD6
VVLD7
VVLD8
VVLD9
VVLD10
VVLD11
VVLD12
VVLD13
VVLD14
VVLD15
VVLD15b
Vvld_hsyt
Min.
0.420
0.550
0.680
0.800
0.930
1.050
1.180
1.300
1.430
1.550
1.680
1.800
1.950
2.080
2.200
2.340
2.550
Typ.
0.500
0.650
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.85
2.00
2.15
2.30
2.45
2.60
2.75
3.00
50
Radc_pa4
Max.
0.580
0.750
0.900
1.100
1.260
1.450
1.600
1.780
1.950
2.120
2.300
2.460
2.640
2.800
2.980
3.150
3.420
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mV
MΩ
1
18.6 DC characteristics - I/O Pins
Conditions: T= -20 to 85°C (unless otherwise specified) VDD =3.0V
Parameter
Conditions
Symb.
Min.
VIL
Typ.
Max.
Unit
Vss
0.2 VDD
V
VIH
0.7 VDD
VDD
V
VDD =3.0V, Pin at 3.0V, 25°C
RPD
80
125
180
kΩ
VDD =3.0V, Pin at 0.0V, 25°C
RPU
80
175
280
kΩ
VDD =3.0V , VOL =0.15V
IOL
6.7
mA
VDD =3.0V , VOL =0.30V
IOL
13.1
mA
VDD =3.0V , VOL =0.50V
IOL
VDD =3.0V , VOL =1.00V
IOL
VDD =3.0V , VOL =0.15V
Input Low voltage
Port A[5:0]
Input High voltage
Port A[5:0]
Input Pull-down
PA[5:0] strong
Input Pull-up
PA[5:0] strong
Output Low Current
PA[0]
Output Low Current
PA[2,1]
Output Low Current
PA[3]
Output Low Current
PA[5]
20.8
mA
36.0
mA
IOL
13.6
mA
VDD =3.0V , VOL =0.30V
IOL
26.4
mA
VDD =3.0V , VOL =0.50V
IOL
42.6
mA
20.0
VDD =3.0V , VOL =1.00V
IOL
73.0
mA
VDD =3.0V , VOL =0.15V
IOL
8.2
mA
VDD =3.0V , VOL =0.30V
IOL
15.9
mA
VDD =3.0V , VOL =0.50V
IOL
25.0
mA
VDD =3.0V , VOL =1.00V
IOL
42.7
mA
VDD =3.0V , VOL =0.15V
IOL
7.6
mA
VDD =3.0V , VOL =0.30V
IOL
14.8
mA
VDD =3.0V , VOL =0.50V
IOL
23.5
mA
VDD =3.0V , VOL =1.00V
IOL
39.0
mA
Copyright © 2006, EM Microelectronic-Marin SA
53
45.0
25.0
20.0
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EM6580
Conditions: T= -20 to 85°C (unless otherwise specified) VDD =3.0V
Parameter
Conditions
Output High Current
PA[0]
VDD =3.0V, VOH = VDD -0.15V
IOH
-2.75
mA
VDD =3.0V , VOH = VDD -0.30V
IOH
-5.3
mA
VDD =3.0V , VOH = VDD -0.50V
IOH
-8.5
VDD =3.0V , VOH = VDD -1.00V
IOH
-15.3
VDD =3.0V, VOH = VDD -0.15V
IOH
-4.0
mA
VDD =3.0V , VOH = VDD -0.30V
IOH
-7.7
mA
VDD =3.0V , VOH = VDD -0.50V
IOH
-12.7
mA
Output High Current
PA[2,1]
Output High Current
PA[3]
Output High Current
PA[5]
Symb.
Min.
Typ.
Max.
Unit
mA
-10.0
-15.0
mA
VDD =3.0V , VOH = VDD -1.00V
IOH
-23.6
VDD =3.0V, VOH = VDD -0.15V
IOH
-3.2
mA
VDD =3.0V , VOH = VDD -0.30V
IOH
-6.3
mA
VDD =3.0V , VOH = VDD -0.50V
IOH
-10.1
mA
VDD =3.0V , VOH = VDD -1.00V
IOH
-18.5
VDD =3.0V, VOH = VDD -0.15V
IOH
-3.2
mA
VDD =3.0V , VOH = VDD -0.30V
IOH
-6.0
mA
VDD =3.0V , VOH = VDD -0.50V
IOH
-9.5
mA
VDD =3.0V , VOH = VDD -1.00V
IOH
-17.2
-12.0
-11.0
mA
mA
mA
18.7 RC oscillator frequency
Conditions: VDD =3.0V, T=25°C (unless otherwise specified)
Parameter
512 kHz untrimmed
512 kHz trimmed
Conditions
-20 to 85°C
Symbol
f512
f512tr
f512tr
Min.
-40%
-5%
-10%
Typ.
512
512
512
Max.
+40%
+5%
+10%
Unit
kHz
kHz
kHz
-20 to 85°C
f800
f800tr
f800tr
-40%
-5%
-10%
800
800
800
-40%
+5%
+10%
kHz
kHz
kHz
Ustart
tdsys
VDDmin
VDD > VDDMin
0.5
6.0
V
ms
800 kHz untrimmed
800 kHz trimmed
Oscillator start voltage
System start time
(oscillator + cold-start + reset)
18.8 Sleep Counter Reset - SCR
Conditions: VDD =3.0V
Parameter
SCR timeout 0
SCR timeout 1
SCR timeout 2
SCR timeout 3
Conditions
-20 to 85°C
-20 to 85°C
-20 to 85°C
-20 to 85°C
Copyright © 2006, EM Microelectronic-Marin SA
Symbol
tSCR00
tSCR01
tSCR10
tSCR11
Min.
12
123
1.01
8.2
54
Typ.
23
237
1.95
15.7
Max.
34
350
2.88
23.21
Unit
ms
ms
s
s
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EM6580
19. Pad Location Diagram
Information upon request to EM Microelectronic-Marin SA.
20. Package Dimensions
20.1 SO-8/14
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EM6580
21. Ordering Information
Packaged Device:
Device in DIE Form:
EM6580 SO8 A+
EM6580 WS 11
Package:
SO8 = 8 pin SOIC
SO14 = 14 pin SOIC
Die form:
WW = Wafer
WS = Sawn Wafer/Frame
WP = Waffle Pack
Thickness:
11 = 11 mils (280um), by default
27 = 27 mils (686um), not backlapped
(for other thickness, contact EM)
Delivery Form:
A = Stick
B = Tape&Reel
In its packaged form, EM6580 comes in green mold /lead free (symbolized by a “+” at the end of the part number).
Ordering Part Number (selected examples)
Part Number
EM6580SO8A +
EM6580SO8B +
EM6580SO14A +
EM6580SO14B +
EM6580WS11
EM6580WP11
Package/Die Form
8 pin SOIC
8 pin SOIC
14 pin SOIC
14 pin SOIC
Sawn wafer
Die in waffle pack
Delivery Form/ Thickness
Stick
Tape&Reel
Stick
Tape&Reel
11 mils
11 mils
Please make sure to give the complete Part Number when ordering.
21.1 Package Marking
8-pin SOIC marking:
First line:
Second line:
Third line:
6 5 8 0 0 1
P P P P P P
R 1 A
Y
14-pin SOIC marking:
First line:
Second line:
Third line:
E M 6 5 8 0 0 1
P P P P P P P P
R 1 A
Y P
Where: PP…P = Production identification (date & lot number) of EM Microelectronic-Marin SA
Y = year of assembly
EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in
the Company's standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site.
EM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or
specifications detailed herein at any time without notice, and does not make any commitment to update the information
contained herein. No licenses to patents or other intellectual property of EM are granted in connection with the sale of EM
products, expressly or by implications. EM's products are not authorized for use as components in life support devices or
systems.
© EM Microelectronic-Marin SA, 01/06, Rev. F
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