®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
Disclaimer
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera
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relying on any published information and before placing orders for products or services.
The pin connection guidelines are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification. The use of the pin connection
guidelines for any particular design should be verified for device operation, with the datasheet and Altera.
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Pin Connection Guidelines Agreement © 2015 Altera Corporation. All rights reserved.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 1 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Pin Connection Guidelines
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Clock and PLL Pins
CLK [0..7]p
Clock, I/O
Dedicated global clock input pins that
can also be used for the positive terminal
inputs for differential global clock input or
user input pins. When these clock input
pins are used as single-ended pins, you
can disregard the p notation.
Connect unused pins to the VCCIO of the bank
in which the pins reside or GND.
See Notes 2 and 3.
CLK[0..7]p pins can function as regular
I/O pins.
CLK[0..7]n
Clock, I/O
Dedicated global clock input pins that
can also be used for the negative
terminal inputs for differential global
clock input or user input pins. When
these clock input pins are used as
single-ended pins, you can disregard the
n notation.
Connect unused pins to the VCCIO of the bank
in which the pins reside or GND.
See Notes 2 and 3.
CLK[0..7]n pins can function as regular
I/O pins.
DPCLK[0..3]
PCG-01018-1.3
Copyright © 2015 Altera Corp.
I/O, Input
DPCLK pins can connect to the global
clock network for high fan-out control
signals such as clocks, asynchronous
clears, presets, and clock enables.
DPCLK pins cannot feed a PLL input.
Connect unused pins to the VCCIO of the bank
they reside in or GND.
These pins can function as regular I/O pins.
See Note 3.
Page 2 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
PLL_[L,R,B,T]_CLKOUTp
PLL_[L,R,B,T]_CLKOUTn
Pin Type (1st and
2nd Function)
I/O, Output
I/O, Output
Pin Description
Optional positive terminal for external
clock outputs from PLL [1..4]. These pins
can be assigned to single-ended or
differential I/O standards if it is being fed
by a PLL output.
The availability for
PLL_[L,R,B,T]_CLKOUTp pins varies for
each device density and package
combination. For details, refer to the
specific device pinout file.
Optional negative terminal for external
clock outputs from PLL [1..4]. These pins
can be assigned to single-ended or
differential I/O standards if it is being fed
by a PLL output.
The availability for
PLL_[L,R,B,T]_CLKOUTn pins varies for
each device density and package
combination. For details, refer to the
specific device pinout file.
Connection Guidelines
Connect unused pins to GND.
These pins can function as regular I/O pins.
See Note 3.
Connect unused pins to GND.
These pins can function as regular I/O pins.
See Note 3.
Configuration/JTAG Pins (Note 8)
This is a dual-purpose pin. Use this pin
to choose the configuration image in the
dual-configuration images mode.
CONFIG_SEL
Input, I/O
If the CONFIG_SEL pin is set to low, the
first configuration image is configuration
image 0. If the CONFIG_SEL pin is set to
high, the first configuration image is
configuration image 1.
Connect a weak 10-KΩ pull-up or weak 10-KΩ
pull-down to this pin externally during the powerup phase.
By default this pin is tri-stated.
See Note 10.
This pin is read before user mode and
before the nSTATUS pin is asserted.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 3 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
The CONF_DONE pin should be pulled high by
an external 10-KΩ pull-up resistor.
CONF_DONE
CRC_ERROR
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Bidirectional
(open-drain), I/O
Output
(open-drain), I/O
This is a dual-purpose pin. The
CONF_DONE pin drives low before and
during configuration. After all
configuration data is received without
error and the initialization cycle starts,
the CONF_DONE pin is released.
This is a dual-purpose pin. Active high
signal indicates that the error detection
circuitry has detected errors in the
configuration SRAM bits.
The CRC_ERROR pin is an optional pin
and is used when the cyclic redundancy
check (CRC) error detection circuitry is
enabled.
The MAX 10 device will not enter the initialization
and user mode if the CONF_DONE pin is pulled
low.
Hot socketing is disabled for the CONF_DONE
pin. Due to this, a glitch maybe observed at the
CONF_DONE pin. To monitor the status of the
pin, Altera recommends to implement input buffer
with hysteresis and digital filtering with the
sampling duration larger than 5.5 ms in the
external device to avoid false trip.
Altera recommends you to tie the CRC_ERROR
pin to VCCIO, GND, or leave the pin
unconnected when the CRC error detection
circuitry is disabled or when you are not using
the CRC_ERROR pin.
Page 4 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
This is a dual-purpose pin. Optional
chip-wide reset pin that allows you to
override all clears on all device registers.
DEV_CLRn
Input, I/O
When this pin is driven low, all registers
are cleared. When this pin is driven high,
all registers behave as programmed.
The DEV_CLRn pin does not affect
JTAG boundary-scan or programming
operations. You can enable this pin by
turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II
software.
This is a dual-purpose pin. Optional pin
that allows you to override all tri-states
on the device.
DEV_OE
Input, I/O
When this pin is driven low, all I/O pins
are tri-stated. When this pin is driven
high, all I/O pins behave as programmed.
You can enable this pin by turning on the
Enable device-wide output enable
(DEV_OE) option in the Quartus II
software.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Altera recommends you to tie the DEV_CLRn pin
to VCCIO, GND, or leave the DEV_CLRn pin
unconnected when you are not using this pin and
when the pin is not used as an I/O pin.
By default the DEV_CLRn pin is tri-stated.
Altera recommends you to tie the DEV_OE pin to
VCCIO, GND, or leave the DEV_OE pin
unconnected when you are not using this pin and
when the pin is not used as an I/O pin.
By default the DEV_OE pin is tri-stated.
Page 5 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
This is a dual-purpose pin. This pin
functions according to the setting of the
JTAG pin sharing option bit.
JTAGEN
I/O
If the JTAG pin sharing is not enabled,
the JTAGEN pin is a regular I/O pin and
JTAG pins function as JTAG dedicated
pins.
If the JTAG pin sharing is enabled and
the JTAGEN pin is pulled low, JTAG pins
function as dual-purpose pins.
In user mode, to use JTAG pins as regular I/O
pins, tie the JTAGEN pin to a weak 1-kΩ
pull-down. To use JTAG pins as dedicated pins,
tie the JTAGEN pin to a weak 10-kΩ pull-up.
If the JTAG pin sharing is enabled and
the JTAGEN pin is pulled high, JTAG
pins function as JTAG dedicated pins.
This is a dual-purpose pin, as an
nCONFIG pin or a single-ended input pin
in user mode. Before user mode, these
pins function as configuration pins.
nCONFIG
Input, I/O
During configuration mode, the pin name
is nCONFIG. During user mode, the pin
name is Input_only.
Upon power up, the nCONFIG pin must be pulled
high. Connect this pin directly or through a 10-kΩ
resistor to VCCIO.
If you pull this pin low during user mode
the device will lose its configuration data,
enter a reset state, and tri-state all I/O
pins. Pulling this pin to a logic-high level
initiates reconfiguration.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 6 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
This is a dual-purpose pin, as an
nSTATUS pin or a regular user I/O pin in
user mode. By default, the nSTATUS pin
is a dedicated configuration pin in user
mode.
nSTATUS
Bidirectional
(open-drain), I/O
The device drives the nSTATUS pin low
immediately after power up and releases
the pin after power-on reset (POR) time.
As a status output, the nSTATUS pin is
pulled low if an error occurs during
configuration.
Connection Guidelines
Pull the nSTATUS pin high using an external
10-kΩ pull-up resistor.
Hot socketing is disabled for the nSTATUS pin.
Due to this, a glitch maybe observed at the
nSTATUS pin. To monitor the status of the pin,
Altera recommends to implement input buffer
with hysteresis and digital filtering with the
sampling duration larger than 5.5 ms in the
external device to avoid false trip.
As a status input, the device enters an
error state when the nSTATUS pin is
driven low by an external source during
configuration or initialization.
TCK
Input, I/O
JTAG test clock input pin. This is a dualpurpose pin.
This TCK pin does not support internal weak
pull-down. Connect this pin to an external
1-KΩ – 10-KΩ pull-down resistor.
By default this pin is tri-stated.
TDO
Output, I/O
This is a dual-purpose pin, as a JTAG
TDO pin or a regular user I/O pin in user
mode.
Altera recommends you to leave this pin
unconnected if not used.
By default this pin is tri-stated.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 7 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
TDI
Pin Type (1st and
2nd Function)
Input, I/O
Pin Description
This is a dual-purpose pin, as a JTAG
TDI pin or a regular user I/O pin in user
mode.
You can disable the JTAG circuitry by
connecting the TDI pin to VCC.
TMS
Input, I/O
This is a dual-purpose pin, as a JTAG
TMS pin or a regular user I/O pin in user
mode.
You can disable the JTAG circuitry by
connecting the TMS pin to VCC.
Connection Guidelines
This pin has a weak internal pull-up. For
configuration voltage of 2.5 V, 3.0 V, or 3.3 V,
connect this pin through a 10-kΩ resistor to
VCCA supply. For configuration voltage of 1.5 V
and 1.8 V, connect this pin through a 10-kΩ
resistor to VCCIO supply.
This pin has a weak internal pull-up. For
configuration voltage of 2.5 V, 3.0 V, or 3.3 V,
connect this pin through a 10-kΩ resistor to
VCCA supply. For configuration voltage of 1.5 V
and 1.8 V, connect this pin through a 10-kΩ
resistor to VCCIO supply.
Differential I/O Pins
DIFFIO_RX_L[#:#][n,p],
DIFFOUT_L[#:#][n,p]
PCG-01018-1.3
Copyright © 2015 Altera Corp.
I/O, dedicated RX
channel, emulated
LVDS output
channel
When used as differential inputs, these
are true LVDS receiver channels on left
I/O banks. Pins with a “p” suffix carry the
positive signal for the differential
channel. Pins with an “n” suffix carry the
negative signal for the differential
channel. If not used for differential
signaling, these pins are available as
user I/O pins.
When used as differential outputs, these
are emulated LVDS output channels on
left I/O banks. External resistor network
is needed for emulated LVDS output
buffers. Pins with a “p” suffix carry the
positive signal for the differential
channel. Pins with an “n” suffix carry the
negative signal for the differential
channel. If not used for differential
signaling, these pins are available as
user I/O pins.
Connect unused pins as defined in the Quartus II
software.
For the number of LVDS pair count for each MAX
10 device, refer to the respective device pinout
file.
Page 8 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
DIFFIO_RX_R[#:#][n,p],
DIFFOUT_R[#:#][n,p]
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Pin Type (1st and
2nd Function)
I/O, dedicated RX
channel, emulated
LVDS output
channel
Pin Description
When used as differential inputs, these
are true LVDS receiver channels on right
I/O banks. Pins with a “p” suffix carry the
positive signal for the differential
channel. Pins with an “n” suffix carry the
negative signal for the differential
channel. If not used for differential
signaling, these pins are available as
user I/O pins.
When used as differential outputs, these
are emulated LVDS output channels on
right I/O banks. External resistor network
is needed for emulated LVDS output
buffers. Pins with a “p” suffix carry the
positive signal for the differential
channel. Pins with an “n” suffix carry the
negative signal for the differential
channel. If not used for differential
signaling, these pins are available as
user I/O pins.
Connection Guidelines
Connect unused pins as defined in the Quartus II
software.
For the number of LVDS pair count for each MAX
10 device, refer to the respective device pinout
file.
Page 9 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
DIFFIO_RX_T[#:#][n,p],
DIFFOUT_T[#:#][n,p]
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Pin Type (1st and
2nd Function)
I/O, dedicated RX
channel, emulated
LVDS output
channel
Pin Description
When used as differential inputs, these
are true LVDS receiver channels on top
I/O banks. Pins with a “p” suffix carry the
positive signal for the differential
channel. Pins with an “n” suffix carry the
negative signal for the differential
channel. If not used for differential
signaling, these pins are available as
user I/O pins.
When used as differential outputs, these
are emulated LVDS output channels on
top I/O banks. External resistor network
is needed for emulated LVDS output
buffers. Pins with a “p” suffix carry the
positive signal for the differential
channel. Pins with an “n” suffix carry the
negative signal for the differential
channel. If not used for differential
signaling, these pins are available as
user I/O pins.
Connection Guidelines
Connect unused pins as defined in the Quartus II
software.
For the number of LVDS pair count for each MAX
10 device, refer to the respective device pinout
file.
Page 10 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
When used as differential inputs, these
are true LVDS receiver channels on
bottom I/O banks. Pins with a “p” suffix
carry the positive signal for the
differential channel. Pins with an “n”
suffix carry the negative signal for the
differential channel. If not used for
differential signaling, these pins are
available as user I/O pins.
DIFFIO_RX_B[#:#][n,p],
DIFFOUT_B[#:#][n,p]
DIFFIO_TX_RX_B[#:#][n,p]
PCG-01018-1.3
Copyright © 2015 Altera Corp.
I/O, dedicated RX
channel, emulated
LVDS output
channel
I/O, dedicated
TX/RX channel
When used as differential outputs, these
are emulated LVDS output channels on
bottom I/O banks. External resistor
network is needed for emulated LVDS
output buffers. Pins with a “p” suffix carry
the positive signal for the differential
channel. Pins with an “n” suffix carry the
negative signal for the differential
channel. If not used for differential
signaling, these pins are available as
user I/O pins.
These are true LVDS transmitter
channels or true LVDS receiver channels
on bottom I/O banks. Pins with a “p”
suffix carry the positive signal for the
differential channel. Pins with an “n”
suffix carry the negative signal for the
differential channel. If not used for
differential signaling, these pins are
available as user I/O pins.
Connection Guidelines
Connect unused pins as defined in the Quartus II
software.
For the number of LVDS pair count for each MAX
10 device, refer to the respective device pinout
file.
Connect unused pins as defined in the Quartus II
software.
For the number of LVDS pair count for each MAX
10 device, refer to the respective device pinout
file.
Page 11 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
High_Speed
Pin Type (1st and
2nd Function)
I/O
Pin Description
These are I/O pins. High_Speed I/O pins
have higher performance compared to
Low_Speed I/O pins.
Connection Guidelines
Connect unused pins as defined in the Quartus II
software.
High_Speed I/O pins reside in Banks 2,
3, 4, 5, 6, and 7.
Low_Speed
I/O
These are I/O pins. Low_Speed I/O pins
have lower performance compared to
High_Speed I/O pins.
Connect unused pins as defined in the Quartus II
software.
Low_Speed I/O pins reside in Banks 1A,
1B, and 8.
This pin is required for each OCT RS
calibration block. OCT is only applicable
for right I/O banks (banks 5 and 6) of
10M16, 10M25, and 10M50 devices.
RDN
PCG-01018-1.3
Copyright © 2015 Altera Corp.
I/O, Input
This pin is a dual-purpose pin, you can
use the RDN pin as a regular I/O pin if
the OCT calibration is not used. When
you use OCT calibration, connect the
RDN pin to GND through an external
resistor.
When you use OCT, tie these pins to GND
through either a 25-, 34-, 40-, 48-, or 50-Ω
resistor depending on the desired I/O standard.
When the device does not use this dedicated
input pin for the external precision resistor or as
an I/O pin, Altera recommends you to connect
the RDN pin to GND.
Page 12 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
This pin is required for each OCT RS
calibration block. OCT is only applicable
for right I/O banks (banks 5 and 6) of
10M16, 10M25, and 10M50 devices.
RUP
I/O, Input
This pin is a dual-purpose pin, you can
use the RUP pin as a regular I/O pin if
the OCT calibration is not used. When
you use OCT calibration, connect the
RUP pin to VCCN through an external
resistor.
These pins are dual-purpose pins. For
Banks 1A and 1B, VREF pins are
shared.
VREFB<#>N0
Power, I/O
Input reference voltage for each I/O
bank. If a bank uses a voltage
referenced I/O standard for input
operation, then these pins are used as
the voltage-reference pins for the bank.
Connection Guidelines
When you use OCT, tie these pins to the
required VCCIO banks through either a 25-, 34-,
40-, 48-, or 50-Ω resistor depending on the
desired I/O standard. When the device does not
use this dedicated input pin for the external
precision resistor or as an I/O pin, Altera
recommends you to connect the RUP pin to
VCCIO of the bank in which the RUP pin resides
or GND.
If you are not using the VREF pins in banks or
shared banks, connect unused pins as defined in
the Quartus II software.
When VREF pins are used as I/O pins, they have
higher capacitance than regular I/O pins which
will slow the edge rates and affect I/O timing.
External Memory Interface Pins
DQ[#]R
PCG-01018-1.3
Copyright © 2015 Altera Corp.
I/O, DQ
Optional data signal for use in external
memory interfacing. The order of the DQ
bits within a designated DQ bus is not
important. However, use with caution
when making pin assignments if you plan
on migrating to a different memory
interface that has a different DQ bus
width.
Connect unused pins as defined in the Quartus II
software.
Page 13 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
DQS[#]R
I/O, DQS
Optional data strobe signal for use in
external memory interfacing.
DQSn[#]R
I/O, DQSn
Optional complementary data strobe
signal for use in external memory
interfacing.
DM[#]R
I/O, DM
A low signal on the DM pin indicates that
the write is valid. Driving the DM pin high
results in the memory masking of the DQ
signals.
CK_[6]
I/O, Output
CK#_[6]
I/O, Output
Pin Description
Input clock for external memory devices.
Input clock for external memory devices,
inverted CK.
Connection Guidelines
Connect unused pins as defined in the Quartus II
software.
Connect unused pins as defined in the Quartus II
software.
Connect unused pins as defined in the Quartus II
software.
Connect unused pins as defined in the Quartus II
software.
Connect unused pins as defined in the Quartus II
software.
Reference Pins
GND
Ground
Device ground pins.
Altera recommends you to tie REFGND to the
GND pin with an isolating ferrite bead for the best
ADC performance.
Connect all GND pins to the board GND plane.
NC
PCG-01018-1.3
Copyright © 2015 Altera Corp.
No Connect
Do not drive signals into these pins.
When designing for device migration you may
connect these pins to power, ground, or a signal
trace depending on the pin assignment of the
devices selected for migration. However, if
device migration is not a concern, leave these
pins floating.
Page 14 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
These multi-purpose pins support singleended analog input and can be used as
regular digital I/O pins. When not used
as analog input pins, these pins can be
used as any other digital I/O pins.
All digital I/O pins will be tri-stated if any of these
pins is configured as an analog input pin.
For unused ADCIN pins, Altera recommends you
to connect them to GND.
Voltage Sensor Pins
ADCIN[8] and ADCIN[16] pins support
the prescalar feature.
ADC[1..2]IN[1..16]
I/O, Input
For 10M08 and 10M16 devices,
ADC1IN[1..8] pins are available for the
single power supply devices and
ADC1IN[1..16] pins are available for the
dual power supply devices.
For 10M25 and 10M50 devices,
ADC1IN[1..8] and ADC2IN[1..8] pins are
available for both single and dual power
supply devices.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
No parallel routing between analog input signals
and I/O traces. Crosstalk requirement is from
-100 dB to 2 GHz. Route the analog input signal
adjacent to the REFGND.
Total RC value including package, trace, and
driver parasitic values should be less than
42.4 ns. This is to ensure the input signal is fully
settled during the sampling phase.
Low pass filter is required for each analog input
pin. The filter ground reference is REFGND.
For details about the board design guidelines,
refer to the MAX 10 ADC User Guide.
Page 15 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Tie the ADC_VREF pin to an external accurate
voltage reference source. If you are not using the
external reference, this pin is a no connect (NC).
ADC_VREF
Input
Analog-to-digital converter (ADC) voltage
reference input.
No parallel routing between analog input signals
and I/O traces. Crosstalk requirement is from
-100 dB to 2 GHz.
For more information, refer to the Guidelines:
Board Design for ADC Reference Voltage Pin
section of the MAX 10 Analog to Digital
Converter User Guide.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 16 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
If this pin is not used, Altera recommends you to
connect them to GND.
No parallel routing between analog input signals
and I/O traces. Crosstalk requirement is from
-100 dB to 2 GHz. Route the analog input signal
adjacent to the REFGND.
ANAIN[1]
Input
This is a dedicated single-ended analog
input pin for ADC1.
Total RC value including package, trace, and
driver parasitic values should be less than
42.4 ns. This is to ensure the input signal is fully
settled during the sampling phase.
Low pass filter is required for each analog input
pin. The filter ground reference is REFGND.
For details about the board design guidelines,
refer to the MAX 10 ADC User Guide.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 17 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
This is a dedicated single-ended analog
input pin for ADC2.
ANAIN[2]
Input
This pin is not available in each device
density and package combination. For
details, refer to the specific device pinout
file.
Connection Guidelines
If this pin is not used, Altera recommends you to
connect them to GND.
No parallel routing between analog input signals
and I/O traces. Crosstalk requirement is from
-100 dB to 2 GHz. The RC filter ground reference
is REFGND.
Total RC value including package, trace, and
driver parasitic values should be less than
42.4 ns. This is to ensure the input signal is fully
settled during the sampling phase.
Low pass filter is required for each analog input
pin. The filter ground reference is REFGND.
For more information, refer to the MAX 10 Analog
to Digital Converter User Guide.
REFGND
Input
This pin is the ADC ground reference pin
for ANAIN pins.
Altera recommends you to tie REFGND to the
GND pin with an isolating ferrite bead for the best
ADC performance.
If you are not using ADC, tie this pin directly to
GND.
MAX 10S (Single Supply) FPGA
Power supply pin for core and periphery
through an on-die regulator.
VCC_ONE
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Power
The voltage is internally regulated to
1.2V to supply power to the core and
periphery.
The VCC_ONE power supply pin supports E144,
M153, and U169 package-types only.
Connect all VCC_ONE pins to either 3.0- or
3.3-V power supply. Tie VCC_ONE and VCCA
with filter using the same power supply on board
level.
Page 18 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect these pins to 1.2-, 1.35-, 1.5-, 1.8-, 2.5-,
3.0-, or 3.3-V power supplies, depending on the
I/O standard assigned to each I/O bank.
If you are migrating from other MAX 10 devices
to the 10M02 device, the VCCIO1A and
VCCIO1B pins are shorted to the VCCIO1 pin of
the 10M02 device.
If you do not enable the ADC feature, connect
VCCIO1A and VCCIO1B pins to the same
voltage level.
VCCIO[#]
Power
I/O supply voltage pins for banks 1
through 8. Each bank supports different
voltage level.
If you enable the ADC feature, connect
VCCIO1A and VCCIO1B to either 3.0- or 3.3-V
depending on the VCCA_ADC pins used.
The VCCIO pin supplies power to the
input and output buffers for all I/O
standards.
The power supply sharing between VCCIO1A
and VCCIO1B pins requires filtering to isolate the
noise. The filter should be located near to
VCCIO1A pins. Only 10M02 devices do not
require filtering if VCCIO1A and VCCIO1B share
the same power supply. When the ADC feature is
enabled, filter is required.
The VCCIO pin powers up the JTAG and
configuration pins.
If you are migrating from the 10M08 or 10M16
device to the 10M02 device with ADC enabled,
replace the filter with 0-Ω resistor in the 10M02
device.
For details about the available VCCIO pins for
each MAX 10 device, refer to the respective
device pinout file. See Note 4.
Decoupling of these pins depends on the design
decoupling requirements of the specific board.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 19 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect these pins to a 3.0- or 3.3-V power
supplies even if the PLL and ADC are not used.
These pins must be powered up and powered
down at the same time. Connect all VCCA pins
together.
VCCA[1..6]
Power
Power supply pins for PLL and ADC
block.
VCCA power supply to the FPGA should be
isolated for better jitter performance. See Notes 5
and 6.
VCCA[1..4] is available for M153 and U169
packages while VCCA[1..6] is available for the
E144 package.
MAX 10D (Dual Supply) FPGA
Connect all VCC pins to 1.2-V power supply.
VCC
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Power
Power supply pin for core and periphery.
Decoupling of these pins depends on the design
decoupling requirements of the specific board.
See Note 4.
Page 20 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect these pins to 1.2-, 1.35-, 1.5-, 1.8-, 2.5-,
3.0-, or 3.3-V power supplies, depending on the
I/O standard assigned to each I/O bank.
If you are migrating from other MAX 10 devices
to the 10M02 device, the VCCIO1A and
VCCIO1B pins are shorted to the VCCIO1 pin of
the 10M02 device.
If you do not enable the ADC feature, connect
VCCIO1A and VCCIO1B pins to the same
voltage level.
I/O supply voltage pins for banks 1
through 8. Each bank supports different
voltage level.
VCCIO[#]
Power
The VCCIO pin supplies power to the
input and output buffers for all I/O
standards.
The VCCIO pin powers up the JTAG and
configuration pins.
If you enable the ADC feature, connect
VCCIO1A and VCCIO1B to 2.5-V.
The power supply sharing between VCCIO1A
and VCCIO1B pins requires filtering to isolate the
noise. The filter should be located near to
VCCIO1A pins. Only 10M02 devices do not
require filtering if VCCIO1A and VCCIO1B share
the same power supply. When the ADC feature is
enabled, filter is required.
If you are migrating from the 10M08 or 10M16
device to the 10M02 device with ADC enabled,
replace the filter with 0-Ω resistor in the 10M02
device.
For details about the available VCCIO pins for
each MAX 10 device, refer to the respective
device pinout file.
Decoupling of these pins depends on the design
decoupling requirements of the specific board.
See Note 4.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 21 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
VCCA[1..4]
Pin Type (1st and
2nd Function)
Power
Pin Description
Power supply pins for PLL analog block.
Connection Guidelines
Connect these pins to a 2.5-V power supply even
if the PLL is not used. These pins must be
powered up and powered down at the same
time. Connect all VCCA pins together.
VCCA power supply to the FPGA should be
isolated for better jitter performance. See Notes 5
and 6.
Connect VCCD_PLL[1..4] pins to 1.2-V power
supply even if the PLL is not used.
VCCD_PLL[1..4]
Power
Power supply pins for PLL digital block.
Connect all VCCD_PLL[1..4] pins together.
Altera recommends you to keep these pins
isolated from other VCC pins for better jitter
performance. See Notes 5 and 7.
Connect the VCCA_ADC pin to the
recommended power supply specification for the
best ADC performance.
VCCA_ADC
Power
Power supply pin for ADC analog block.
Tie the VCCA_ADC pin to any 2.5V power
domain if you are not using ADC, and do not tie
the VCCA_ADC pin to GND.
Decoupling of these pins depends on the design
decoupling requirements of the specific board.
See Note 4.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 22 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect the VCCINT pin to the recommended
power supply specification for the best ADC
performance.
VCCINT
Power
Power supply pin for ADC digital block.
Tie the VCCINT pin to any 1.2V power domain if
you are not using ADC.
Decoupling of these pins depends on the design
decoupling requirements of the specific board.
See Note 4.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 23 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Notes to Pin Connection Guidelines
Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper
device functionality.
1.
2.
3.
These pin connection guidelines are created based on the MAX 10 FPGA device family.
The number of dedicated global clocks for each device density is different.
The unused pins must be connected as specified in the Quartus II software settings. The default Quartus II setting for unused pins is ‘As inputs tri-stated with weak pull-up resistors’,
unless for specific pins that the Quartus II software connects them to GND automatically.
4. Capacitance values for the power supply decoupling capacitors should be selected after consideration of the amount of power needed to supply over the frequency of operation of the
particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and voltage drop requirements of the device/supply. The power
plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the
mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To assist in
decoupling analysis, Altera's "Power Distribution Network (PDN) Design Tool" serves as an excellent decoupling analysis tool. The PDN design tool can be obtained at Power
Distribution Network Design Tool.
To calculate the target impedance of each MAX 10 device supply, you should use the following transient current and voltage ripple percentages:
MAX 10 Supply Rail
Transient Current (%)
Voltage Ripple (%)
VCC
50
5
VCCIO
100
5
VCCA
10
5
VCCD_PLL
10
3
VCCA_ADC
50
2
VCCINT
50
3
Setting Ftarget to 70 MHz or higher should result in a robust PDN.
5. Use separate power islands for VCCA and VCCD_PLL. PLL power supply may originate from another plane on the board but must be isolated using a ferrite bead or other equivalent
methods. If using a ferrite bead, choose an 0402 package with low DC resistance, higher current rating than the maximum steady state current for the supply it is connected to(VCCA
or VCCD_PLL) and high impedance at 100 MHz.
6. The VCCA power island can be decoupled with a combination of decoupling capacitors. Please refer to the Power Distribution Network Design Tool to determine the decoupling
capacitors value. Use 0402 package for 0.1 uF and smaller capacitors for lower mounting inductance. Place 0.1 uF and smaller capacitors as close to the device as possible. On-board
capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design techniques such as interplane
capacitance with low inductance should be considered for higher frequency decoupling. To minimize impact on jitter, a 20 mV ripple voltage was used in the analysis for VCCA
decoupling.
7. The VCCD_PLL power island can be decoupled with a combination of decoupling capacitors. Please refer to the “Power Distribution Network Design Tool” at Power Distribution
Network Design Tool to determine the decoupling capacitors value. Place 0.1 uF and smaller capacitors as close to the device as possible. On-board capacitors do not decouple
higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance
should be considered for higher frequency decoupling. To minimize impact on jitter, a 20 mV ripple voltage was used in the analysis for VCCD_PLL decoupling.
8. All configuration pins used in user mode are low-speed I/Os.
9. Low Noise Switching Regulator - defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and
other support components. The switching frequency is usually between 800kHz and 1MHz and has fast transient response. The switching frequency range is not an Altera
requirement. However, Altera does require the Line Regulation and Load Regulation meet the following specifications:
•
Line Regulation < 0.4%
•
Load Regulation < 1.2%
10. If you disable the “Auto-reconfigure from secondary image when initial image fails” option in the Quartus II software when generating the POF file, the FPGA will always load the
configuration image 0 without sampling the physical CONFIG_SEL pin during power up.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 24 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 FPGA
Example 1. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – The ADC Feature is Not Used
Example Requiring 3 Power Regulators
Power Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
1
1.2
± 50mV
Switcher (*)
VCC
VCCINT
VCCA_ADC
VCCIO
Notes
Share
VCCD_PLL
VCCA
Regulator Sharing
Isolate
You have the option to share VCCINT and VCCD_PLL with VCC using
proper isolation filters.
Isolate
2
3
2.5
2.5
Varies
± 5%
Switcher (*)
Share
You have the option to share VCCA_ADC with VCCA.
± 5%
Switcher (*)
Share
Individual power rail.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
Notes:
(1) Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
(2) Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
MAX 10 FPGA device is provided in Figure 1.
(3) The voltage level for each power rail is preliminary.
(4) The MAX 10 performance is guaranteed with the recommended Enpirion power solutions. For a list of recommended Enpirion solutions for MAX 10 devices, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer page. The recommended Enpirion solutions are included in the summary report. For more details about the Enpirion power solutions, refer to the
Enpirion Power page.
(5) For LPDDR2 interface targeting 200MHz,you need to constraint the memory device I/O and core power supply to ± 3% variation.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 25 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Figure 1. Example Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – The ADC Feature is Not Used
The ADC power supply requires 0.1uF decoupling cap near the package and ferrite bead filter at power supply.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 26 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 FPGA
Example 2. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 2.5V
Example Requiring 3 Power Regulators
Power Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
1
1.2
± 50mV
Switcher (*)
VCC
VCCINT
VCCA_ADC
Notes
Share
VCCD_PLL
VCCA
Regulator Sharing
Isolate
You have the option to share VCCINT and VCCD_PLL with VCC with
proper isolation filters.
Isolate
2
2.5
2.5
VCCIO1B
2.5
VCCIO[2..8]
2.5
3
VCCIO1A
± 5%
± 5%
2.5
Switcher (*)
Share
Isolate
You have the option to share VCCA_ADC with VCCA with proper isolation
filters.
Share
You have the option to share VCCIO1B and VCCIO[2..8] when
these pins are powered up at 2.5V.
Isolate
You have the option to share VCCIO1A with VCCIO1B and
VCCIO[2..8] using proper isolation filter.
Switcher (*)
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
Notes:
(1) Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
(2) Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
MAX 10 FPGA device is provided in Figure 2.
(3) The voltage level for each power rail is preliminary.
(4) The MAX 10 performance is guaranteed with the recommended Enpirion power solutions. For a list of recommended Enpirion solutions for MAX 10 devices, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer page. The recommended Enpirion solutions are included in the summary report. For more details about the Enpirion power solutions, refer to the
Enpirion Power page.
(5) For LPDDR2 interface targeting 200MHz,you need to constraint the memory device I/O and core power supply to ± 3% variation.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 27 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Figure 2. Example Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 2.5V
The ADC power supply requires 0.1uF decoupling cap near the package and ferrite bead filter at power supply.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
(**) Ferrite beads should be connected in series followed by a 10uF capacitor to ground. Place the decoupling of 0.1uF cap closer to the pin.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 28 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 FPGA
Example 3. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 1.2V/1.35V/1.5V/1.8V/3.0V/3.3V
Example Requiring 4 Power Regulators
Power Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
1
1.2
± 50mV
Switcher (*)
VCC
VCCINT
VCCA_ADC
VCCIO1B
VCCIO1A
VCCIO[2..8]
Notes
Share
VCCD_PLL
VCCA
Regulator Sharing
Isolate
You have the option to share VCCINT and VCCD_PLL with VCC using
proper isolation filters.
Isolate
2
2.5
± 5%
Switcher (*)
3
2.5
± 5%
Switcher (*)
4
Varies
± 5%
Switcher (*)
Share
Isolate
Share
You have the option to share VCCA_ADC with VCCA using proper
isolation filters.
Isolate
You have the option to share VCCIO1A with VCCIO1B using proper
isolation filter.
Share
Individual power rail.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
Notes:
(1) Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
(2) Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
MAX 10 FPGA device is provided in Figure 3.
(3) The voltage level for each power rail is preliminary.
(4) The MAX 10 performance is guaranteed with the recommended Enpirion power solutions. For a list of recommended Enpirion solutions for MAX 10 devices, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer page. The recommended Enpirion solutions are included in the summary report. For more details about the Enpirion power solutions, refer to the
Enpirion Power page.
(5) For LPDDR2 interface targeting 200MHz,you need to constraint the memory device I/O and core power supply to ± 3% variation.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 29 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Figure 3. Example Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at
1.2V/1.35V/1.5V/1.8V/3.0V/3.3V
The ADC power supply requires 0.1uF decoupling cap near the package and ferrite bead filter at power supply.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
(**) Ferrite beads should be connected in series followed by a 10uF capacitor to ground. Place the decoupling of 0.1uF cap closer to the pin.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 30 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 FPGA
Example 4. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA (E144, M153, and U169 Packages) – The ADC Feature is Not Used
Example Requiring 2 Power Regulator
Power Pin Name
VCC_ONE
VCCA
VCCIO
Regulator Count
1
2
Voltage
Level (V)
3.0/3.3
3.0/3.3
Varies
Supply
Tolerance
Power
Source
± 5%
Switcher (*)
± 5%
Switcher (*)
Regulator Sharing
Share
Notes
Isolate
Both VCCA and VCC_ONE must share a single power source using
proper isolation filter.
Share
Individual power rail.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
Notes:
(1) Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
(2) Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
MAX 10 FPGA device is provided in Figure 4.
(3) The voltage level for each power rail is preliminary.
(4) The MAX 10 performance is guaranteed with the recommended Enpirion power solutions. For a list of recommended Enpirion solutions for MAX 10 devices, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer page. The recommended Enpirion solutions are included in the summary report. For more details about the Enpirion power solutions, refer to the
Enpirion Power page.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 31 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Figure 4. Example Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA (E144, M153, and U169 Packages) – The ADC Feature is Not Used
(*) When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
(**) The VCCA power supply requires ferrite bead filter for noise isolation.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 32 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 FPGA
Example 5. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 3.0V/3.3V
(E144, M153, and U169 Packages)
Example Requiring 2 Power Regulator
Power Pin Name
VCC_ONE
VCCA
Regulator
Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
1
3.0/3.3
± 5%
Switcher (*)
2
3.0/3.3
± 5%
Switcher (*)
Regulator
Sharing
Share
Isolate
VCCIO1B
VCCIO[2..8]
VCCIO1A
Notes
Both VCCA and VCC_ONE must share a single power source using proper isolation
filter.
Share
You have the option to share VCCIO1B and VCCIO[2..8] when these pins
are powered up at 3.0V/3.3V.
Isolate
You have the option to share VCCIO1A with VCCIO1B and VCCIO[2..8] using proper
isolation filter.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
Notes:
(1) Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
(2) Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
MAX 10 FPGA device is provided in Figure 5.
(3) The voltage level for each power rail is preliminary.
(4) The MAX 10 performance is guaranteed with the recommended Enpirion power solutions. For a list of recommended Enpirion solutions for MAX 10 devices, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer page. The recommended Enpirion solutions are included in the summary report. For more details about the Enpirion power solutions, refer to the
Enpirion Power page.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 33 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Figure 5. Example Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 3.0V/3.3V (E144, M153, and
U169 Packages)
(*) When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
(**) The VCCA power supply requires ferrite bead filter for noise isolation.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 34 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
MAX 10 FPGA
Example 6. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 1.2V/1.35V/1.5V/1.8V/2.5V
(E144, M153, and U169 Packages)
Example Requiring 3 Power Regulator
Power Pin Name
VCC_ONE
VCCA
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
1
3.0/3.3
± 5%
Switcher (*)
2
3.0/3.3
± 5%
Switcher (*)
VCCIO1B
Share
Isolate
Share
VCCIO1A
VCCIO1[2..8]
Regulator
Sharing
3
Varies
± 5%
Switcher (*)
Notes
Both VCCA and VCC_ONE must share a single power source using proper
isolation filter.
Isolate
You have the option to share VCCIO1A with VCCIO1B using proper
isolation filter.
Share
Individual power rail.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
Notes:
(1) Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
(2) Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
MAX 10 FPGA device is provided in Figure 6.
(3) The voltage level for each power rail is preliminary.
(4) The MAX 10 performance is guaranteed with the recommended Enpirion power solutions. For a list of recommended Enpirion solutions for MAX 10 devices, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer page. The recommended Enpirion solutions are included in the summary report. For more details about the Enpirion power solutions, refer to the
Enpirion Power page.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 35 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Figure 6. Example Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 1.2V/1.35V/1.5V/1.8V/2.5V
(E144, M153, and U169 Packages)
(*) When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to Pin Connection Guidelines.
(**) The VCCA power supply requires ferrite bead filter for noise isolation.
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 36 of 37
®
MAX 10 FPGA Device Family Pin Connection Guidelines
Preliminary PCG-01018-1.3
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Revision History
Revision
1.0
Description of Changes
Initial release.
Date
9/22/2014
1.1
•
•
•
•
•
•
•
•
Added note 10 in the Notes to Pin Connection Guidelines.
Added note (**) to Figure 2.
Updated the pin name from BOOT_SEL to CONFIG_SEL.
Updated the pin description of the CONFIG_SEL pin.
Updated the connection guidelines of the VCC_ONE pin.
Updated the connection guidelines of the nSTATUs pin.
Updated the connection guidelines of the CONF_DONE pin.
Updated note 4 in the Notes to Pin Connection Guidelines.
12/15/2014
1.2
•
•
•
•
Updated the connection guidelines of the DPCLK[0..3] pins.
Updated the connection guidelines of the PLL_[L,R,B,T]_CLKOUTp and PLL_[L,R,B,T]_CLKOUTn pins.
Updated the connection guidelines of the VREFB<#>N0 pins.
Updated the pin description of the ADC[1..2]IN[1..16] pins.
1/29/2015
•
Added the following power sharing guidelines:
o
Example 2. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and
VCCIO[2..8] Pins are Powered Up at 2.5V
o
Example 3. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and
VCCIO[2..8] Pins are Powered Up at 1.2V/1.35V/1.5V/1.8V/3.0V/3.3V
o
Example 5. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and
VCCIO[2..8] Pins are Powered Up 3.0V/3.3V (E144, M153, and U169 Packages)
o
Example 6. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and
VCCIO[2..8] Pins are Powered Up 1.2V/1.35V/1.5V/1.8V/2.5V (E144, M153, and U169 Packages)
Updated the following power sharing guidelines:
o
Example 1. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – The ADC Feature is Not Used
Updated the pin description of the DPCLK[0..3] pins.
Updated the connection guidelines of the VCCIO[#] pins.
Updated the connection guidelines of the ADC[1..2]IN[1..16] pins.
Updated the connection guidelines of the ADC_VREF pin.
5/6/2015
1.3
•
•
•
•
•
PCG-01018-1.3
Copyright © 2015 Altera Corp.
Page 37 of 37