Arria 10 GX, GT, and SX Device Family Pin Connection

®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Disclaimer
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera
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respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard
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information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before
relying on any published information and before placing orders for products or services.
The pin connection guidelines are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification. The use of the pin connection
guidelines for any particular design should be verified for device operation, with the datasheet and Altera.
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1.
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device-based design. You may not use this pin connection guideline for any other purpose.
2.
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Pin Connection Guidelines Agreement © 2015 Altera Corporation. All rights reserved.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 1 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 GX and GT Pin Connection Guidelines
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Clock and PLL Pins
CLK_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]p
I/O, Clock Input
Dedicated high speed clock input pins
that can be used for data inputs or
outputs. Differential input OCT Rd,
single-ended input OCT Rt, and
single-ended output OCT Rs are
supported on these pins.
CLK_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]n
PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_FB[0,1]
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Copyright © 2015 Altera Corp.
I/O, Clock Input
I/O, Clock
Dual-purpose I/O pins that can be used
as single-ended inputs, single-ended
outputs, or external feedback input pin.
For more information about the
supported pins, refer to the device pinout
file.
Tie the unused pins to GND or leave them
unconnected. If the pins are not connected, use
the Quartus II software programmable options to
internally bias these pins. These pins can be
reserved as inputs tristate with weak pull-up
resistor enabled, or as outputs driving GND.
Tie the unused pins to GND or leave them
unconnected. If the pins are not connected, use
the Quartus II software programmable options to
internally bias these pins. These pins can be
reserved as inputs tristate with weak pull-up
resistor enabled, or as outputs driving GND.
Tie these pins to GND or leave them
unconnected. If the pins are not connected, use
the Quartus II software programmable options to
internally bias these pins. These pins can be
reserved as inputs tristate with weak pull-up
resistor enabled, or as outputs driving GND.
Page 2 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_CLKOUT[0:1],
PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_CLKOUT[0,1]p
Pin Type (1st and
2nd Function)
Pin Description
I/O, Clock
I/O pins that can be used as two
single-ended clock output pins or one
differential clock output pair. For more
information about the supported pins,
refer to the device pinout file.
PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_CLKOUT[0,1]n
I/O, Clock
Connection Guidelines
Tie these pins to GND or leave them
unconnected. If the pins are not connected, use
the Quartus II software programmable options to
internally bias these pins. These pins can be
reserved as inputs tristate with weak pull-up
resistor enabled, or as outputs driving GND.
Tie these pins to GND or leave them
unconnected. If the pins are not connected, use
the Quartus II software programmable options to
internally bias these pins. These pins can be
reserved as inputs tristate with weak pull-up
resistor enabled, or as outputs driving GND.
Dedicated Configuration/JTAG Pins
nIO_PULLUP
Input
Dedicated input pin that determines the
internal pull-ups on user I/O pins and
dual-purpose I/O pins (DATA[0:31],
CLKUSR, INIT_DONE, DEV_OE, and
DEV_CLRn) are on or off before and
during configuration.
A logic high turns off the weak pull-up,
while a logic low turns on the weak
pull-up.
TEMPDIODEp
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Input
Pin used for temperature sensing diode
(bias-high input) inside the FPGA.
Tie the nIO-PULLUP pin directly to VCC using a
1 kΩ pull-up resistor, or directly to GND. This pin
has an internal 25-kΩ pull-down.
If you tie this pin to VCC, ensure all user I/O pins
and dual-purpose I/O pins are at a valid logic
(0 or 1) before and during configuration.
If you do not use the temperature sensing diode
with an external temperature sensing device,
connect this pin to GND.
Page 3 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
TEMPDIODEn
Input
Pin used for temperature sensing diode
(bias-low input) inside the FPGA.
If you do not use the temperature sensing diode
with an external temperature sensing device,
connect this pin to GND.
These pins are internally connected through a
25-kΩ resistor to GND. Do not leave these pins
floating. When these pins are unused, connect
them to GND.
MSEL[0:2]
Input
Configuration input pins that set the
configuration scheme for the FPGA
device.
Depending on the configuration scheme used, tie
these pins to VCCPGM or GND. For more
information about the configuration scheme
options, refer to the Configuration, Design
Security, and Remote System Upgrades for Arria
10 Devices chapter.
If you use JTAG configuration scheme, connect
these pins to GND.
nCE
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Input
Dedicated active-low chip enable pin.
When the nCE pin is low, the device is
enabled. When the nCE pin is high, the
device is disabled.
In multi-device configuration, the nCE pin of the
first device is tied low while its nCEO pin drives
the nCE pin of the next device in the chain.
In single-device configuration and JTAG
programming, connect the nCE pin to GND.
Page 4 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
nCONFIG
Pin Type (1st and
2nd Function)
Input
Pin Description
Dedicated configuration control input pin.
Pulling this pin low during user mode
causes the FPGA to lose its
configuration data, enter a reset state,
and tri-state all I/O pins. Returning this
pin to a logic high level initiates
reconfiguration.
Connection Guidelines
Connect the nCONFIG pin directly to the
configuration controller when the FPGA uses a
passive configuration scheme.
Connect the nCONFIG pin through a
10-kΩ resistor tied to VCCPGM when the FPGA
uses an active serial (AS) configuration scheme.
If you do not use this pin, connect the pin directly
or through a 10-kΩ resistor to VCCPGM.
Dedicated configuration done pin.
CONF_DONE
Bidirectional
(open-drain)
As a status output, the CONF_DONE pin
drives low before and during
configuration. After all configuration data
is received without error and the
initialization cycle starts, CONF_DONE is
released.
As a status input, the CONF_DONE pin
goes high after all data is received. Then
the device initializes and enters user
mode. This pin is not available as a user
I/O pin.
When device configuration is complete,
the nCEO pin drives low.
nCEO
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Copyright © 2015 Altera Corp.
I/O, Output
(open-drain)
If you do not use this pin as a
configuration pin, you can use this pin as
a user I/O pin.
Connect an external 10-kΩ pull-up resistors to
VCCPGM. VCCPGM must be high enough to
meet the VIH specification of the I/O on the
device and the external host.
When you use passive configuration schemes,
the configuration controller monitors this pin.
In multi-device configuration, the nCEO pin feeds
the nCE pin of a subsequent FPGA.
Connect this pin through an external 10-kΩ
pull-up resistor to VCCPGM.
In single-device configuration, you can leave this
pin floating.
Page 5 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Dedicated configuration status pin.
The FPGA drives the nSTATUS pin low
immediately after power-up, and
releases the pin after power-on reset
(POR) time.
nSTATUS
Bidirectional
(open-drain)
As a status output, the nSTATUS pin is
pulled low if an error occurs during
configuration.
As a status input, the device enters an
error state when the nSTATUS pin is
driven low by an external source during
configuration or initialization. This pin is
not available as a user I/O pin.
Connection Guidelines
Connect an external 10-kΩ pull-up resistors to
VCCPGM. VCCPGM must be high enough to
meet the VIH specification of the I/O on the
device and the external host.
When you use passive configuration schemes,
the configuration controller monitors this pin.
Connect this pin through a 1-kΩ pull-down
resistor to GND. This pin has an internal 25-kΩ
pull-down.
TCK
Input
Dedicated JTAG test clock input pin.
Do not drive voltage higher than 1.8-, 1.5-, or
1.2-V VCCPGM supply for the TCK pin. The TCK
input pin is powered by the VCCPGM supply.
Connect this pin to a 1-kΩ - 10-kΩ pull-up
resistor to VCCPGM.
TMS
Input
Dedicated JTAG test mode select input
pin.
If the JTAG interface is not used, connect the
TMS pin to VCCPGM using a 1-kΩ resistor. This
pin has an internal 25-kΩ pull-up.
Do not drive voltage higher than 1.8-, 1.5-, or
1.2-V VCCPGM supply for the TMS pin. The
TMS input pin is powered by the VCCPGM
supply.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 6 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect this pin to a 1-kΩ - 10-kΩ pull-up
resistor to VCCPGM.
TDI
Input
Dedicated JTAG test data input pin.
If the JTAG interface is not used, connect the TDI
pin to VCCPGM using a 1-kΩ resistor. This pin
has an internal 25-kΩ pull-up.
Do not drive voltage higher than 1.8-, 1.5-, or
1.2-V VCCPGM supply for the TDI pin. The TDI
input pin is powered by the VCCPGM supply.
TDO
Output
Dedicated JTAG test data output pin.
If the JTAG interface is not used, leave the TDO
pin unconnected.
Utilization of the TRST pin is optional. If you do
not use this pin, tie this pin through a
1-kΩ pull-up resistor to VCCPGM.
TRST
Input
Dedicated active low JTAG test reset
input pin. The TRST pin is used to
asynchronously reset the JTAG
boundary-scan circuit.
When you use this pin, ensure that the TMS pin
is held high or the TCK pin is static when the
TRST pin is changing from low to high.
To disable the JTAG circuitry, tie this pin to GND.
This pin has an internal 25-kΩ pull-up.
Do not drive voltage higher than 1.8-, 1.5-, or
1.2-V VCCPGM supply for the TRST pin. The
TRST input pin is powered by the VCCPGM
supply.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 7 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
nCSO[0:2]
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Output
Dedicated output control signal from the
FPGA to the EPCQ-L device in AS
configuration scheme that enables the
EPCQ-L device.
When you are not programming the FPGA in the
AS configuration scheme, the nCSO pin is not
used. When you do not use this pin as an output
pin, leave this pin unconnected.
Optional/Dual-Purpose Configuration Pins
DCLK
Input (PS, FPP);
Output (AS)
Dedicated configuration clock pin. In
passive serial (PS) and fast passive
parallel (FPP) configuration schemes,
DCLK is used to clock configuration data
from an external source into the FPGA.
Do not leave this pin floating. Drive this pin either
high or low.
In the AS configuration scheme, DCLK is
an output from the FPGA that provides
timing for the configuration interface.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 8 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Active high signal indicates the error
detection circuit has detected errors in
the configuration RAM (CRAM) bits.
CRC_ERROR
I/O, Output
(open-drain)
Falling edge of this signal indicates the
information about the error location and
type are available in the error message
register (EMR).
This dual-purpose pin is only used when
you enable error detection in user mode.
Connection Guidelines
When you use the open-drain output dualpurpose CRC_ERROR pin as an optional pin,
connect this pin through an external 10-kΩ pullup resistor to VCCPGM.
When you do not use the open-drain output dualpurpose CRC_ERROR pin as an optional pin,
and the CRC_ERROR pin is not used as an I/O
pin, connect this pin as defined in the Quartus II
software.
This pin can be used as a user I/O pin.
Optional pin that allows you to override
all clears on all device registers.
DEV_CLRn
I/O, Input
When this pin is driven low, all registers
are cleared. When this pin is driven high
(VCCPGM), all registers behave as
programmed.
When you do not use the dual-purpose
DEV_CLRn pin and when this pin is not used as
an I/O pin, tie this pin to GND.
Optional pin that allows you to override
all tri-states on the device.
DEV_OE
PCG-01017-1.6
Copyright © 2015 Altera Corp.
I/O, Input
When this pin is driven low, all I/O pins
are tri-stated. When this pin is driven
high (VCCPGM), all I/O pins behave as
programmed.
When you do not use the dual-purpose DEV_OE
pin and when this pin is not used as an I/O pin,
tie this pin to GND.
Page 9 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
DATA0
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
I/O, Input
Dual-purpose configuration data input
pin. You can use the DATA0 pin for PS
or FPP configuration scheme, or as an
I/O pin after configuration is complete.
When you do not use the dedicated input
DATA[0] pin and when this pin is not used as an
I/O pin, leave this pin unconnected.
Dual-purpose configuration data input
pins.
DATA[1:31]
I/O, Input
Use DATA [1:7] pins for FPP x8, DATA
[1:15] pins for FPP x16, and DATA [1:31]
pins for FPP x32 configuration or as
regular I/O pins. These pins can also be
used as user I/O pins after configuration.
This is a dual-purpose pin and can be
used as an I/O pin when not enabled as
the INIT_DONE pin.
INIT_DONE
PCG-01017-1.6
Copyright © 2015 Altera Corp.
I/O, Output
(open-drain)
When you enable this pin, a transition
from low to high at the pin indicates the
device has entered user mode. If the
INIT_DONE output is enabled, the
INIT_DONE pin cannot be used as a
user I/O pin after configuration.
When you do not use the dual-purpose
DATA[1:31] pins and when these pins are not
used as I/O pins, leave these pins unconnected.
When you use the optionally open-drain output
dedicated INIT_DONE pin, connect this pin to an
external 10-kΩ pull-up resistor to VCCPGM.
When you use this pin in an AS or PS
multi-device configuration mode, ensure you
enable the INIT_DONE pin in the Quartus II
designs. When you do not use the dedicated
INIT_DONE optionally open-drain output, and
when this pin is not used as an I/O pin, connect
this pin as defined in the Quartus II software.
Page 10 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect this pin as defined in the Quartus II
software. This pin is powered by 1.8V supply and
must be driven by 1.8V compatible I/O standards.
Connect the PCIe nPERST pin to a level
translator to shift down the voltage from 3.3V
LVTTL to 1.8V to interface with this pin.
Dual-purpose fundamental reset pin that
is only available when you use together
®
®
with PCI Express (PCIe ) hard IP (HIP).
nPERST[L,R][0:1]
I/O, Input
When the pin is low, the transceivers are
in reset. When the pin is high, the
transceivers are out of reset. When you
do not use this pin as the fundamental
reset, you can use this pin as a user I/O
pin.
Only one nPERST pin is used per PCIe HIP. The
Arria 10 components always have all four pins
listed even when the specific component might
only have 1 or 2 PCIe HIPs.
nPERSTL0 = Bottom Left PCIe HIP & CvP;
nPERSTL1 = Top Left PCIe HIP (When
available);
nPERSTR0 = Bottom Right PCIe HIP (When
available);
nPERSTR1 = Top Right PCIe HIP (When
available).
For maximum compatibility, always use the
bottom left PCIe HIP first, as this is the only
location that supports Configuration via Protocol
(CvP) using the PCIe link.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 11 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
AS_DATA0/ASDO
AS_DATA[1:3]
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Bidirectional
Dedicated AS configuration pin. When
using an EPCQ-L device (x1 mode), this
is the ASDO pin and is used to send
address and control signals between the
FPGA device and the EPCQ-L device.
When you do not program the device in the AS
configuration mode, the ASDO pin is not used.
When you do not use this pin, leave the pin
unconnected.
Bidirectional
Dedicated AS configuration data pins.
Configuration data is transported on
these pins when connected to the
EPCQ-L devices.
When you do not use this pin, leave the pin
unconnected.
Partial Reconfiguration Pins
Partial reconfiguration request pin.
PR_REQUEST
I/O, Input
Drive this pin high to start partial
reconfiguration. Drive this pin low to end
reconfiguration.
When you do not use the dedicated input
PR_REQUEST pin, and when this pin is not used
as an I/O pin, tie this pin to GND.
You can only use this pin in partial
reconfiguration using an external host
mode in FPP x16 configuration scheme.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 12 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
PR_READY
PR_ERROR
PR_DONE
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Pin Type (1st and
2nd Function)
Pin Description
I/O, Output or
Output
(open-drain)
The partial reconfiguration ready pin is
driven low until the device is ready to
begin partial reconfiguration. When the
device is ready to start reconfiguration,
this signal is released and pulled high by
an external pull-up resistor.
I/O, Output or
Output
(open-drain)
The partial reconfiguration error pin is
driven low during partial reconfiguration
unless the device detects an error. If an
error is detected, this signal is released
and pulled high by an external pull-up
resistor.
I/O, Output or
Output
(open-drain)
The partial reconfiguration done pin is
driven low until the partial reconfiguration
is complete. When the reconfiguration is
complete, this signal is released and
pulled high by an external pull-up
resistor.
Connection Guidelines
When you use as optionally open-drain output
dedicated PR_READY pin, connect this pin to an
external 10-kΩ pull-up resistor to VCCPGM.
When you do not use as the dedicated
PR_READY optionally open-drain output, and
when this pin is not used as an I/O pin, connect
this pin as defined in the Quartus II software.
When you use as optionally open-drain output
dedicated PR_ERROR pin, connect this pin to an
external 10-kΩ pull-up resistor to VCCPGM.
When you do not use as the dedicated
PR_ERROR optionally open-drain output, and
when this pin is not used as an I/O pin, connect
this pin as defined in the Quartus II software.
When you use as optionally open-drain output
dedicated PR_DONE pin, connect this pin to an
external 10-kΩ pull-up resistor to VCCPGM.
When you do not use as the dedicated
PR_DONE optionally open-drain output, and
when this pin is not used as an I/O pin, connect
this pin as defined in the Quartus II software.
Page 13 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
CvP_CONFDONE
Pin Type (1st and
2nd Function)
I/O, Output
(open-drain)
Pin Description
CvP done pin is driven low during
configuration. When the CvP
configuration is complete, this signal is
released and pulled high by an external
pull-up resistor.
Status of this pin is only valid if the
CONF_DONE pin is high.
Connection Guidelines
When you use as optionally open-drain output
dedicated CvP_CONFDONE pin, connect this pin
to an external 10-kΩ pull-up resistor to
VCCPGM.
When you do not use as the dedicated
CvP_CONFDONE optionally open-drain output,
and when this pin is not used as an I/O pin,
connect this pin as defined in the Quartus II
software.
Differential I/O Pins
LVDS[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_[1:24]p,
LVDS[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_[1:24]n
PCG-01017-1.6
Copyright © 2015 Altera Corp.
I/O, RX/TX
channel
These are true LVDS receiver/transmitter
channels on column I/O banks. Each I/O
pair can be configured as LVDS receiver
or LVDS transmitter. Pins with a "p"
suffix carry the positive signal for the
differential channel. Pins with an "n"
suffix carry the negative signal for the
differential channel. If not used for
differential signaling, these pins are
available as user I/O pins.
Connect unused pins as defined in the Quartus II
software.
Page 14 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
I/O,bi-directional
Optional data strobe signal for use in
external memory interfacing. These pins
drive to dedicated DQS phase shift
circuitry.
Connect unused pins as defined in the Quartus II
software.
I/O,bi-directional
Optional complementary data strobe
signal for use in external memory
interfacing. These pins drive to dedicated
DQS phase shift circuitry.
Connect unused pins as defined in the Quartus II
software.
DQ[#]
I/O,bi-directional
Optional data signal for use in external
memory interfacing. The order of the DQ
bits within a designated DQ bus is not
important. However, if you plan on
migrating to a different memory interface
that has a different DQ bus width, you
will need to reevaluate your pin
assignments. Analyze the available DQ
pins across all pertinent DQS columns in
the pin list.
Connect unused pins as defined in the Quartus II
software.
CQ[#]
I/O, Input
Optional data strobe signal for use in
QDRII SRAM. These are the pins for
echo clocks.
Connect unused pins as defined in the Quartus II
software.
CQn[#]
I/O, Input
Optional complementary data strobe
signal for use in QDRII SRAM. These are
the pins for echo clocks.
Connect unused pins as defined in the Quartus II
software.
Arria 10 Pin Name
External Memory Interface Pins
DQS[#]
DQSn[#]
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 15 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
I/O, bidirectional
Optional data strobe signal for use in
external memory interfacing. These pins
drive to dedicated DQS phase shift
circuitry. The shifted DQS signal can also
drive to internal logic.
Connect unused pins as defined in the Quartus II
software.
I/O, bidirectional
Optional complementary data strobe
signal for use in external memory
interfacing. These pins drive to dedicated
DQS phase shift circuitry.
Connect unused pins as defined in the Quartus II
software.
DQ[#]_[#]_[#]
I/O, bidirectional
Optional data signal for use in external
memory interfacing. The order of the DQ
bits within a designated DQ bus is not
important. However, if you plan on
migrating to a different memory interface
that has a different DQ bus width, you
will need to reevaluate your pin
assignments. Analyze the available DQ
pins across all pertinent DQS columns in
the pin list.
Connect unused pins as defined in the Quartus II
software.
CQ[#]_[#]/CQn[#]_[#]
I/O, Input
Optional data strobe signal for use in
QDRII SRAM. These are the pins for
echo clocks.
Connect unused pins as defined in the Quartus II
software.
QK[#]_[#]
I/O, Input
Optional data strobe signal for use in
RLDRAM II.
Connect unused pins as defined in the Quartus II
software.
QKn[#]_[#]
I/O, Input
Optional complementary data strobe
signal for use in RLDRAM II.
Connect unused pins as defined in the Quartus II
software.
Arria 10 Pin Name
Hard Memory PHY Pins
DQS[#]_[#]
DQSn[#]_[#]
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 16 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
DM[#]_[#]
I/O, Output
Optional write data mask, edge-aligned
to DQ during write.
Connect unused pins as defined in the Quartus II
software.
RESET_N_0
IO, Output
Active low reset signal.
Connect unused pins as defined in the Quartus II
software.
A_[#]
IO, Output
Address input for DDR2, DDR3, DDR4,
SDRAM, RLDRAM II, QDRII/+ SRAM,
and RLDRAM3.
Connect unused pins as defined in the Quartus II
software.
BA_[#]
IO, Output
Bank address input for DDR2, DDR3
SDRAM, and RLDRAM II.
Connect unused pins as defined in the Quartus II
software.
CK_[#]
IO, Output
Input clock for external memory devices.
Connect unused pins as defined in the Quartus II
software.
CK_N_[#]
IO, Output
Input clock for external memory devices,
inverted CK.
Connect unused pins as defined in the Quartus II
software.
CKE_[#]
IO, Output
High signal enables clock, low signal
disables clock.
Connect unused pins as defined in the Quartus II
software.
CS_N_[#]
IO, Output
Active low chip select.
Connect unused pins as defined in the Quartus II
software.
CA_[#]_[#]
IO, Output
Command and address input for LPDDR
SDRAM.
Connect unused pins as defined in the Quartus II
software.
REF#
IO, Output
Auto-refresh control input for RLDRAM II.
Connect unused pins as defined in the Quartus II
software.
ODT_[#]
IO, Output
On die termination signal to set the
termination resistors to each pin.
Connect unused pins as defined in the Quartus II
software.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 17 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
WE_N_0
IO, Output
Write-enable input for DDR2, DDR3
SDRAM and RLDRAM II and all
supported protocols.
Connect unused pins as defined in the Quartus II
software.
CAS_N_0
IO, Output
Column address strobe for DDR2 and
DDR3 SDRAM.
Connect unused pins as defined in the Quartus II
software.
RAS_N_0
IO, Output
Row address strobe for DDR2 and DDR3
SDRAM.
Connect unused pins as defined in the Quartus II
software.
RPS_N_0
IO, Output
Read signal to QDRII memory. Active
low and reset in the inactive state.
Connect unused pins as defined in the Quartus II
software.
WPS_N_0
IO, Output
Write signal to QDRII memory. Active
low and reset in the inactive state.
Connect unused pins as defined in the Quartus II
software.
ALERT_N_0
IO, Output
Alert output that indicate to the system's
memory controller that a specific alert or
event has occurred.
Connect unused pins as defined in the Quartus II
software.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 18 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
PAR_0
IO, Input
Command and Address Parity Input :
DDR4 supports even parity check in
DRAMs with MR setting. Once PAR is
enabled via Register in MR5, then DRAM
calculates parity with
ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A
14,BG0-BG1,BA0-BA1,A17-A0. Input
parity should maintain at the rising edge
of the clock and at the same time with
command and address with CS_n low.
Connect unused pins as defined in the Quartus II
software.
ACT_N_0
IO, Input
Command input that indicates an
ACTIVATE command. Applies for DDR4.
Connect unused pins as defined in the Quartus II
software.
BG_[#]
IO, Input
Bank group address inputs that define
the bank group to which a REFRESH,
ACTIVATE, READ, WRITE, or
PRECHARGE command is being
applied. Applies for DDR4.
Connect unused pins as defined in the Quartus II
software.
C_[#]
IO, Output
Stack address inputs that are used when
devices are stacked. Applies for DDR4.
Connect unused pins as defined in the Quartus II
software.
RM_[1,0]
IO, Output
Rank multiplication.
Connect unused pins as defined in the Quartus II
software.
Arria 10 Pin Name
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 19 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
PE_N_0
IO, Input
Address parity error.
Connect unused pins as defined in the Quartus II
software.
AP_0
IO, Output
Address parity.
Connect unused pins as defined in the Quartus II
software.
AINV_0
IO, Output
Address inversion state for address bus.
Connect unused pins as defined in the Quartus II
software.
RW[A,B]_N_0
IO, Output
Synchronous read/write input.
Connect unused pins as defined in the Quartus II
software.
DOFF_N_0
IO, Output
Phase-locked loop (PLL) turn off for
QDR II/ II + SDRAM.
Connect unused pins as defined in the Quartus II
software.
LD[A,B]_N_0
IO, Output
Synchronous load input.
Connect unused pins as defined in the Quartus II
software.
REF_N_0
IO, Output
Auto-refresh control input for RLDRAM II.
Connect unused pins as defined in the Quartus II
software.
CFG_N_0
IO, Output
Configuration bit.
Connect unused pins as defined in the Quartus II
software.
LBK[#]_N_0
IO, Output
Loop-back mode.
Connect unused pins as defined in the Quartus II
software.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 20 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Voltage Sensor Pins
VREFP_ADC
Input
Dedicated precision analog voltage
reference.
Tie VREFP_ADC to an external 1.25V accurate
reference source (+/- 0.2%) for better ADC
performance. Treat VREFP_ADC as an analog
signal that together with the VREFN_ADC signal
provides a differential 1.25V voltage. If no
external reference is supplied, always connect
VREFP_ADC to GND. An on-chip reference
source (+/-10%) is activated by connecting this
pin to GND.
VREFP_ADC must be equal to or lower than
VCCA_PLL to prevent damage.
VREFN_ADC
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Input
Tie VREFN_ADC to the GND pin of an external
1.25V accurate reference source (+/- 0.2%) for
better ADC performance. Treat VREFN_ADC as
an analog signal that together with the
VREFP_ADC signal provides a differential 1.25V
voltage. If no external reference is supplied,
always connect VREFN_ADC to GND.
Page 21 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
VSIGP_[0,1]
Input
Pin Description
2 pairs of analog differential inputs pins
used with the voltage sensor inside the
FPGA to monitor external analog
voltages.
VSIGN_[0,1]
Input
Connection Guidelines
Tie these pins to GND of the voltage sensor
feature if not used. For details on the usage of
these pins, refer to the Power Management in
Arria 10 Devices chapter.
Do not drive VSIGP and VSIGN pins until the
VCCA_PLL power rail has reached 1.62V to
prevent damage.
Reference Pins
Reference pins for I/O banks. The RZQ
pins share the same VCCIO with the I/O
bank where they are located. Connect
the external precision resistor to the
designated pin within the bank. If not
required, this pin is a regular I/O pin.
RZQ_[#],
VID_EN
I/O, Input or
Output
The VID_EN pin is not a physical pin.
The VID_EN pin is a multi-function
shared pin with the RZQ_2A pin.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
When not used as dedicated input for the
external precision resistor or as an I/O, connect
this pin to GND. When using OCT tie these pins
to GND through either a 240Ω or 100Ω resistor,
depending on the desired OCT impedence. Refer
to the Arria 10 handbook for the OCT impedence
options for the desired OCT scheme.
If you are using the SmartVID feature, you have
the option to enable the VID_EN function using
the RZQ_2A pin. If you use the RZQ_2A pin as
the VID_EN pin, you cannot use the RZQ_2A pin
for OCT calibration.
If you are using the RZQ_2A pin for OCT
calibration, you have the option to use other
available general-purpose I/O pins for the
VID_EN function.
Page 22 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
DNU
Do Not Use
Do Not Use (DNU).
Do not connect to power, GND, or any other
signal. These pins must be left floating.
NC
No Connect
Do not drive signals into these pins.
When designing for device migration, you have
the option to connect these pins to either power,
GND, or a signal trace depending on the pin
assignment of the devices selected for migration.
However, if device migration is not a concern,
leave these pins floating.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 23 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Supply Pins (See Notes 4 through 10)
VCC, VCCP, and VCCERAM must operate at the
same voltage level, should share the same
power plane on the board, and be sourced from
the same regulator unless the VCC Power
Manager or SmartVID feature is used, as
described below.
You can operate -1 and -2 speed grade devices
at 0.9V or 0.95V typical value. You can operate
-3 speed grade device at only 0.9V typical value.
Operating at 0.95V results in higher core
performance and higher power consumption. For
more information about the performance and
power consumption, refer to the Quartus II
software timing reports and Arria 10 Early Power
Estimator (EPE).
VCCP
Power
VCCP supplies power to the periphery.
You have the option to source VCCR_GXB,
VCCT_GXB, VCCERAM, and VCCL_HPS from
the same regulator as VCCP or VCC when the
power rails require the same voltage level. If the
VCC Power Manager or SmartVID feature is
used, VCCR_GXB, VCCT_GXB, VCCERAM,
and VCCL_HPS cannot be sourced from the
same regulator.
For details about the recommended operating
conditions, refer to the Electrical Characteristics
in the device datasheet.
Use the Arria 10 Early Power Estimator (EPE) to
determine the current requirements for VCCP
and other power supplies. Decoupling for these
pins depends on the decoupling requirements of
the specific board. See Notes 2, 3, 4, 5, 6, and
10.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 24 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
VCC, VCCP, and VCCERAM must operate at the
same voltage level, should share the same
power plane on the board, and be sourced from
the same regulator unless the VCC Power
Manager or SmartVID feature is used, as
described below.
You can operate -1 and -2 speed grade devices
at 0.9V or 0.95V typical value. You can operate
-3 speed grade device at only 0.9V typical value.
Operating at 0.95V results in higher core
performance and higher power consumption. For
more information about the performance and
power consumption, refer to the Quartus II
software timing reports and Arria 10 Early Power
Estimator (EPE).
VCC
Power
VCC supplies power to the core.
You have the option to source VCCR_GXB,
VCCT_GXB, VCCERAM, and VCCL_HPS from
the same regulator as VCC or VCCP when the
power rails require the same voltage level. If the
VCC Power Manager or SmartVID feature is
used, VCCR_GXB, VCCT_GXB, VCCERAM,
and VCCL_HPS cannot be sourced from the
same regulator.
For details about the recommended operating
conditions, refer to the Electrical Characteristics
in the device datasheet.
Use the Arria 10 Early Power Estimator (EPE) to
determine the current requirements for VCC and
other power supplies. Decoupling for these pins
depends on the decoupling requirements of the
specific board. See Notes 2, 3, 4, 5, 6, and 10.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 25 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect VCCPT to a 1.8V low noise switching
regulator. You have the option to source the
following from the same regulator as VCCPT:
• VCCH_GXB, VCCA_PLL, VCCPLL_HPS
with proper isolation filtering
• VCCIOREF_HPS
• VCCBAT if it is using the same voltage level
and the design security key feature is not
required.
VCCPT
Power
Power supply for the programmable
power technology and I/O pre-drivers.
If you are not using HPS, do not share
VCCPLL_HPS and VCCIOREF_HPS with
VCCPT.
Provide a minimum decoupling of 1uF for the
VCCPT power rail near the VCCPT pin.
For the power rail sharing, refer to the Power
Supply Sharing Guidelines for Arria 10 Devices.
See Notes 2, 3, 4, 7, and 10.
VCCA_PLL
Power
PLL Analog power.
Connect VCCA_PLL to a 1.8V low noise
switching regulator. With proper isolation filtering,
you have the option to source VCCA_PLL from
the same regulator as VCCPT.
See Notes 2, 3, 4, 7, and 10.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 26 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
VCCIO([2][A, F,G,H,I,J,K, L, AF, KL],
[3][A, B,C,D,E,F,G, H, AB, GH])
Pin Type (1st and
2nd Function)
Power
Pin Description
These are I/O supply voltage pins for
banks 1 through 12. Each bank can
support a different voltage level.
Supports VCCIO standards that include
Diff HSTL/HSTL(12, 15, 18),
Diff SSTL/SSTL(12, 125, 135, 15, 18),
Diff HSUL/HSUL(12), Diff POD 12,
LVDS/Mini_LVDS/RSDS, 1.2V, 1.5V,
1.8V, 2.5V, 3.0V I/O standards.
Connection Guidelines
Connect these pins to 1.2V, 1.25V, 1.35V, 1.5V,
1.8V, 2.5V, or 3.0V supplies, depending on the
I/O standard required by the specified bank.
When these pins require the same voltage level
as VCCPGM, you have the option to tie them to
the same regulator as VCCPGM. Not all I/O
banks support 2.5V or 3.0V supplies. Not all
devices support 3.0V I/O standard. For more
details, refer to the I/O and High Speed I/O in
Arria 10 Devices.
For the power rail sharing, refer to the Power
Supply Sharing Guidelines for Arria 10 Devices.
See Notes 2, 3, 4, 8, and 10.
Connect these pins to a 1.2V, 1.5V, or 1.8V
power supply. When dual-purpose configuration
pins are used for configuration, tie VCCIO of the
bank to the same regulator as VCCPGM, ranging
from 1.2V, 1.5V, or 1.8V. When you do not use
dual-purpose configuration pins for configuration,
connect VCCIO to 1.2V, 1.25V, 1.35V, 1.5V, or
1.8V.
VCCPGM
Power
Configuration pins power supply.
When these pins require the same voltage level
as VCCIO, you have the option to tie them to the
same regulator as VCCIO.
Provide a minimum decoupling of 47nF for the
VCCPGM power rail near the VCCPGM pin.
For the power rail sharing, refer to the Power
Supply Sharing Guidelines for Arria 10 Devices.
See Notes 2, 3, 4, and 10.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 27 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect all VCCERAM pins to a 0.9V or 0.95V
linear or low noise switching power supply.
You have the option to share VCCL_HPS with
VCCERAM plane if the VCCL_HPS voltage is at
the same level for Arria 10 SX devices.
VCCERAM
Power
Memory power pins.
VCC, VCCP, and VCCERAM must operate at the
same voltage level, should share the same
power plane on the board, and be sourced from
the same regulator. When sharing the same
regulator for VCCERAM, VCC, and VCCP, the
SmartVID or VCC Power Manager feature is not
available. If you use the SmartVID feature, then
VCC and VCCP need to be sourced by a
dedicated regulator that is separate from the
VCCERAM regulator.
When you use the SmartVID or the VCC
PowerManager feature, VCCERAM must be
equal to 0.9V.
See Notes 2, 3, 7, and 10.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 28 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
When using the design security volatile key,
connect this pin to a non-volatile battery power
source in the range of 1.2V - 1.8V.
VCCBAT
Power
Battery back-up power supply for design
security volatile key register.
When not using the volatile key, tie this pin to a
supply ranging from more than 1.5V to 1.8V. If
1.8V is selected when the design security key is
unused, you have the option to source this pin
from the same regulator as VCCPT.
This pin must be properly powered as per the
recommended voltage range as the POR circuitry
of the Arria 10 devices monitors VCCBAT.
Provide a minimum decoupling of 47nF for the
VCCBAT power rail near the VCCBAT pin.
For the power rail sharing, refer to the Power
Supply Sharing Guidelines for Arria 10 Devices.
GND
Ground
Device ground pins.
All GND pins should be connected to the board
ground plane.
If VREF pins are not used, connect them to
either the VCCIO in the bank in which the pin
resides or GND. See Note 2, 8, and 10.
VREFB[[2][A, F,G,H,I,J,K, L],
[3][A, B,C,D,E,F,G, H]]N0
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Power
Input reference voltage for each I/O
bank. If a bank uses a
voltage-referenced I/O standard, then
use these pins as voltage-reference pins
for the bank.
The following lists the four pairs of VREF pins in
the RF40 package of the Arria 10 GX devices
that must be connected to the same voltage
source on the board:
•
VREFB2AN0 and VREFB2FN0
•
VREFB2KN0 and VREFB2LN0
•
VREFB3AN0 and VREFB3BN0
•
VREFB3GN0 and VREFB3HN0
Page 29 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
VCCLSENSE
Pin Type (1st and
2nd Function)
Pin Description
VCCLSENSE and GNDSENSE are differential
remote sense pins for the VCC power. Connect
your regulators’ differential remote sense lines to
the respective VCCLSENSE and GNDSENSE
pins. This compensates for the DC IR drop
associated with the PCB and device package
from the VCC power. Route these connections
as differential pair traces and keep them isolated
from any other noise source.
Power
Differential sense line to external
regulator.
GNDSENSE
Ground
Connection Guidelines
Connect VCCLSENSE and GNDSENSE lines to
the regulator’s remote sense inputs when ICC
current >30A or when the SmartVID or VCC
Power Manager feature is used.
VCCLSENSE and GNDSENSE line connections
are optional if ICC current <=30A and both
SmartVID and VCC Power Manager features are
not used. However, Altera recommends
connecting the VCCLSENSE and GNDSENSE
for regulators that support remote sense line
feature.
If you do not use the VCCLSENSE or
GNDSENSE pin, leave the VCCLSENSE or
GNDSENSE pin unconnected.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 30 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
ADCGND
Pin Type (1st and
2nd Function)
Ground
Pin Description
Dedicated quiet ground.
Connection Guidelines
If you are using voltage sensor, you must
connect ADCGND plane to board GND through a
proper isolation filter with ferrite bead. Select the
ferrite bead according to the frequency of the
noise profile when it shows the maximum noise
level.
If you are not using voltage sensor, isolation filter
with ferrite bead is optional on GND rail.
Transceiver Pins (See Notes 4 through 10)
Connect VCCR_GXB pins to a 0.9V, 1.03V, or
1.11V low noise switching regulator. For
transceivers data rates in respect to each voltage
level, refer to the Notes to Power Supply Sharing
Guidelines.
With a proper isolation filtering, VCCR_GXB can
be shared with VCCP and VCC power when
these voltages are at the same level. When
VCCR_GXB is shared with VCC and VCCP, the
VCC Power Manager and SmartVID features
cannot be used.
VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J]
Power
Analog power, receiver, specific to each
transceiver bank of the left (L) side or
right (R) side of the device.
VCCR_GXB is bank-based power rail. Most
VCCR_GXB and VCCT_GXB pins that are
associated with unused transceiver channels can
be connected to GND on a per side basis. To
minimize power consumption of your specific
design, Altera recommends connecting these
pins to GND according to the Quartus II Pin-Out
File Report for your project. Contact Altera
Service for details.
VCCR_GXB and VCCT_GXB pins in the same
bank of the device must have the same voltage.
See Notes 2, 3, 4, 7, and 10.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 31 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect VCCT_GXB pins to a 0.9V, 1.03V, or
1.11V low noise switching regulator. For
transceivers data rates in respect to each voltage
level, refer to the Notes to Power Supply Sharing
Guidelines.
With a proper isolation filtering, VCCT_GXB can
be shared with VCCP and VCC power when
these voltages are at the same level. When
VCCT_GXB is shared with VCC and VCCP, the
VCC Power Manager and SmartVID features
cannot be used.
VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J]
Power
Analog power, transmitter, specific to
each transceiver bank of the left (L) side
or right (R) side of the device.
VCCT_GXB is bank-based power rail. Most
VCCR_GXB and VCCT_GXB pins that are
associated with unused transceiver channels can
be connected to GND on a per side basis. To
minimize power consumption of your specific
design, Altera recommends connecting these
pins to GND according to the Quartus II Pin-Out
File Report for your project. Contact Altera
Service for details.
VCCR_GXB and VCCT_GXB pins in the same
bank of the device must have the same voltage.
See Notes 2, 3, 4, 7, and 10.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 32 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Connect VCCH_GXB to 1.8V low noise switching
regulator. With a proper isolation filtering, you
have the option to source VCCH_GXB from the
same regulator as VCCPT.
VCCH_GXB[L,R]
Power
Analog power, block level transmitter
buffers, specific to the left (L) side or
right (R) side of the device.
VCCH_GXB is side-based power rail. To
minimize power consumption of your specific
design, Altera recommends connecting
VCCH_GXB pins to GND if the Quartus II PinOut File Report recommends that. Contact Altera
Service for details about the specific situation
that VCCH_GXB can be grounded.
When you do not use the whole side of the
transceiver banks, VCCH_GXB can be grounded
only if related I/O banks do not use LVDS, DDR,
PLL, and I/O calibration features. If you need to
use PLL, VCCH_GXB cannot be grounded.
Contact Altera Service for details.
Provide a minimum decoupling of 2.2nF for the
VCCH_GXB power rail near the VCCH_GXB pin.
See Notes 2, 3, 4, 7, and 10.
GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]p,
GXB[L,R][1][C,D,E,F,G,H,I,J]_REFCLK_CH[0:5]p
GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]n,
GXB[L,R][1][C,D,E,F,G,H,I,J]_REFCLK_CH[0:5]n
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Input
High speed positive differential receiver
channels. Specific to each transceiver
bank of the left (L) side or right (R) side
of the device.
These pins can be AC-coupled or DC-coupled
when used. Connect all unused GXB_RXp pins
directly to GND, VCCR_GXB, or VCCT_GXB
pins.
Input
High speed negative differential receiver
channels. Specific to each transceiver
bank of the left (L) side or right (R) side
of the device.
These pins can be AC-coupled or DC-coupled
when used. Connect all unused GXB_RXn pins
directly to GND.
Page 33 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]p
GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]n
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
Output
High speed positive differential
transmitter channels. Specific to each
transceiver bank of the left (L) side or
right (R) side of the device.
Leave all unused GXB_TXp pins floating.
Output
High speed negative differential
transmitter channels. Specific to each
transceiver bank of the left (L) side or
right (R) side of the device.
Leave all unused GXB_TXn pins floating.
High speed differential reference clock
positive receiver channels, specific to
each transceiver bank of the left (L) side
or right (R) side of the device.
REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]p
Input
REFCLK_GXB can be used as dedicated
clock input pins with fPLL for core clock
generation even when the transceiver
channel is not available.
REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]n
Input
High speed differential reference clock
complement, complementary receiver
channel, specific to each transceiver
bank of the left (L) side or right (R) side
of the device.
REFCLK_GXB can be used as dedicated
clock input pins with fPLL for core clock
generation even when the transceiver
channel is not available.
These pins should be AC-coupled or DC-coupled
when used. For HCSL I/O standard, it only
supports DC coupling. In the PCI Express
configuration, DC-coupling is allowed on the
REFCLK if the selected REFCLK I/O standard is
HCSL.
Connect all unused pins either individually to
GND or tie all unused pins together through a
single 10-kΩ resistor to GND. Ensure that the
trace from the pins to the resistor(s) are as short
as possible.
See Note 9.
These pins should be AC-coupled or DC-coupled
when used. For HCSL I/O standard, it only
supports DC coupling. In the PCI Express
configuration, DC-coupling is allowed on the
REFCLK if the selected REFCLK I/O standard is
HCSL.
Connect all unused pins either individually to
GND or tie all unused pins together through a
single 10-kΩ resistor to GND. Ensure that the
trace from the pins to the resistor(s) are as short
as possible.
See Note 9.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 34 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
Pin Type (1st and
2nd Function)
Pin Description
Connection Guidelines
If you are using the CLKUSR pin for
configuration and transceiver calibration, you
must supply an external free running and stable
clock to the CLKUSR pin at start of device
configuration. If the clock is not present at device
power-up, transceiver calibration will be delayed
until the clock is available. This may impact
protocol compliance.
CLKUSR
I/O, Input
This pin is used as the clock for
transceiver calibration, and is a
mandatory requirement when using
transceivers. This pin is optionally used
for EMIF HMC calibration, as well as a
configuration clock input for
synchronizing the initialization of more
than one device. This is a user-supplied
clock and the input frequency range must
be in the range from 100 MHz to 125
MHz.
This pin can be used as a GPIO pin only
if you are not using transceivers, not
using EMIF HMC, and not using this pin
as a user-supplied configuration clock.
You need to ensure supplying the CLKUSR pin
with a common clock frequency that is applicable
for both the configuration mode and transceiver
calibration.
If you are not using the CLKUSR pin for
configuration but using the CLKUSR pin for
transceiver calibration, you must supply an
external free running and stable clock to the
CLKUSR pin at start of device configuration. If
the clock is not present at device power-up,
transceiver calibration will be delayed until the
clock is available. This may impact protocol
compliance.
If you are using the CLKUSR pin for
configuration but not using the CLKUSR pin for
transceiver calibration, you must use a
user-supplied clock input.
For more information, refer to the Configuration,
Design Security, and Remote System Upgrades
for Arria 10 Devices chapter.
Connect the CLKUSR pin to GND if you are not
using the CLKUSR pin for any of the following:
•
Configuration clock input
•
Transceiver calibration clock
•
An I/O pin
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 35 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 Pin Name
RREF_[T,B][L,R]
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Pin Type (1st and
2nd Function)
Input
Pin Description
Connection Guidelines
Reference resistor for fPLL, IOPLL, and
transceiver, specific to the top (T) side or
bottom (B) side and left (L) side or right
(R) side of the device.
If any REFCLK pin or transceiver channel on one
side (left or right) of the device or IOPLL is used,
you must connect each RREF pin on that side of
the device to its own individual 2kΩ resistor to
GND. Otherwise, you can connect each RREF
pin on that side of the device directly to GND. In
the PCB layout, the trace from this pin to the
resistor needs to be routed so that it avoids any
aggressor signals.
Page 36 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Notes to Arria 10 GX and GT Pin Connection Guidelines
Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper
device functionality.
1.
2.
These pin connection guidelines are created based on the Arria 10 GX and GT device variants.
Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being
decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the
appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper
board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
3. Use the Arria 10 Early Power Estimator (EPE) to determine the preliminary current requirements for VCC and other power supplies. Use the Quartus II PowerPlay Power Analyzer for
the most accurate current requirements for this and other power supplies.
4. These supplies may share power planes across multiple Arria 10 devices.
5. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
6. Example 1 through Example 5 and Figure 1 through Figure 5 illustrate the power supply sharing guidelines for the Arria 10 GX and Arria 10 GT devices.
7. Low Noise Switching Regulator - defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and
other support components. The switching frequency is usually between 800kHz and 1MHz and has fast transient response. The switching frequency range is not an Altera
requirement. However, Altera does require the Line Regulation and Load Regulation meet the following specifications:
•
Line Regulation < 0.4%
•
Load Regulation < 1.2%
8. The number of modular I/O banks on Arria 10 devices depends on the device density. For the indexes available for a specific device, please refer to the I/O Bank section
in the Arria 10 device handbook.
9. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter
side of the interface that permits adapters to be plugged and unplugged.
10. Decoupling for these pins depends on the design decoupling requirements of the specific board.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 37 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 SX Pin Connection Guidelines
Pin Type (1st
Pin Description
and 2nd
Function)
Supply Pins (See Notes 4 through 7)
Arria 10 HPS Pin
Name
Connection Guidelines
Connect all VCCL_HPS pins to a 0.9V/0.95V low noise switching
regulator. Power up VCCL_HPS at 0.9V to support HPS processor speed
at 1.2GHz or 0.95V to support HPS processor speed at 1.5GHz.
VCCL_HPS
Power
VCCL_HPS supplies power to the HPS core.
If you are not using HPS, do not share power with FPGA. If you are not
using HPS, you must connect VCCL_HPS to GND.
Use the Arria 10 Early Power Estimator (EPE) to determine the current
requirements for VCCL_HPS and other power supplies. Decoupling for
these pins depends on the design decoupling requirements of the specific
board. See Notes 2, 3, 4, and 6.
VCCIO_HPS
Power
HPS dedicated I/Os. It can support a different voltage
level from 1.8V to 3.0V. The supported I/O standard is
LVTTL/ LVCMOS (3.0, 2.5, 1.8).
Connect these pins to a 1.8V, 2.5V, or 3.0V power supply, depending on
the I/O standard required by the specified bank. If these pins have the
same voltage requirement as VCCIO and VCCPGM, you have the option
to source VCCIO_HPS pins from the same regulator as VCCIO and
VCCPGM. If you are not using HPS, do not share power with FPGA. If
you are not using HPS, you must connect VCCIO_HPS to GND.
Decoupling for these pins depends on the design decoupling
requirements of the specific board. See Notes 2, 3, 4, and 8.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 38 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
VCCPLL_HPS
Pin Type (1st
and 2nd
Function)
Power
Pin Description
Connection Guidelines
VCCPLL_HPS supplies analog power to the HPS core
PLLs.
Connect these pins to a 1.8V low noise switching power supply through a
proper isolation filter. Share VCCPLL_HPS with the same regulator as
VCCPT when all power rails require 1.8V but only with a proper isolation
filter. If you are not using HPS, do not share power with FPGA. If you are
not using HPS, you must connect VCCPLL_HPS to GND.
Decoupling for these pins depends on the design decoupling
requirements of the specific board. See Notes 2, 3, 4, and 7.
VCCIOREF_HPS
Power
HPS power supply for I/O pre-drivers.
The VCCIOREF_HPS pins require 1.8V. When these pins have the same
voltage requirements as VCCIO_HPS, you have the option to tie them to
the same regulator. If these pins have the same voltage requirement as
VCCPT, you have the option to tie them to the same regulator. If you are
not using HPS, do not share power with FPGA. If you are not using HPS,
you must connect VCCIOREF_HPS to GND.
Decoupling for these pins depends on the design decoupling
requirements of the specific board. See Notes 2, 3, 4, and 8.
Dedicated I/O Bank
HPS_CLK1
Input, Clock
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Dedicated clock input pin that drives the main PLL.
This provides clocks to the MPU, L3/L4 sub-systems,
debug sub-system and the Flash controllers. It can
also be programmed to drive the peripheral.
Connect a single-ended clock source to this pin. The I/O standard of the
clock source must be compatible with VCCIO_HPS. Refer to the valid
frequency range of the clock source in Arria 10 Device Datasheet. The
input clock must be present at this pin for HPS operation.
Page 39 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
HPS_ nRST
HPS_ nPOR
Pin Type (1st
and 2nd
Function)
Pin Description
Connection Guidelines
Bidirectional
Warm reset to the HPS block. Active low bi-directional
pin. When driven from the board the system reset
domains which allow debugging to operate is affected.
HPS pulls down the output during the duration of cold
reset and may pull down the output during the duration
of warm reset.
Connect this pin through a 1-kΩ pull-up resistor to VCCIO_HPS.
Input
Cold reset to the HPS block. Active low input that will
reset all HPS logics that can be reset. Places the HPS
in a default state sufficient for software to boot. This
pin has an internal 25-kΩ pull-up resistor that is always
active.
Connect this pin through a 1-kΩ - 10-kΩ pull-up resistor to VCCIO_HPS.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 40 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Pin Type
(1st and
2nd
Function)
Peripherals Pins (See Note 12)
Arria 10 HPS Pin
Name
Power Up
HPS_DEDICATED_4
HPS_DEDICATED_5
Connection
Guidelines
Pin Description
Function
8
Function
7
Function
6
Function
5
Function
4
Function
3
Function
2
Function
1
Function
0
I/O
QSPI
Clock
SDMMC
Data Bit 0
NAND Data
Bit 0
General
Purpose
IO 2 Bit 0
When configured as
the QSPI Clock and if
single memory
topology is used,
connect a 50 Ω
series termination
resistor near this
Arria 10 SoC FPGA
device pin.
For other topologies
use a 25 Ω resistor.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
I/O
QSPI
Data IO
Bit 0
SDMMC
Command
Line
NAND Data
Bit 1
General
Purpose
IO 2 Bit 1
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 41 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
Pin Type
(1st and
2nd
Function)
Connection
Guidelines
Pin Description
QSPI
Slave
Select 0
SDMMC
Clock Out
NAND
Write
Enable
General
Purpose
IO 2 Bit 2
Connect a pull-up or
pull-down resistor to
4.7-kΩ to select the
desired boot select
values. Refer to the
Booting and
Configuration
appendix in the Arria
10 Device Handbook
for Boot Select
values. This resistor
will not interfere with
the slow speed
interface signals that
could share this pin.
I/O
QSPI
Data IO
Bit 1
SDMMC
Data Bit 1
NAND
Read
Enable
General
Purpose
IO 2 Bit 3
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_DEDICATED_8
I/O
QSPI
Data IO
Bit
2/Write
Protect
SDMMC
Data Bit 2
NAND Data
Bit 2
General
Purpose
IO 2 Bit 4
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_DEDICATED_9
I/O
QSPI
Data IO
Bit
3/Hold
SDMMC
Data Bit 3
NAND Data
Bit 3
General
Purpose
IO 2 Bit 5
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
BOOTSEL2 (BSEL2)/
HPS_DEDICATED_6
I/O
HPS_DEDICATED_7
PCG-01017-1.6
Copyright © 2015 Altera Corp.
BOOTSEL2
(BSEL2)
During a
cold reset
this signal
is sampled
as a boot
select
input.
Page 42 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
BOOTSEL1 (BSEL1)/
HPS_DEDICATED_10
BOOTSEL0 (BSEL0)/
HPS_DEDICATED_11
Pin Type
(1st and
2nd
Function)
I/O
I/O
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Pin Description
Connection
Guidelines
BOOTSEL1
(BSEL1)
During a
cold reset
this signal
is sampled
as a boot
select
input.
General
Purpose
IO 2 Bit 6
Connect a pull-up or
pull-down resistor to
4.7-kΩ to select the
desired boot select
values. Refer to the
Booting and
Configuration
appendix in the Arria
10 Device Handbook
for Boot Select
values. This resistor
will not interfere with
the slow speed
interface signals that
could share this pin.
General
Purpose
IO 2 Bit 7
Connect a pull-up or
pull-down resistor to
4.7-kΩ to select the
desired boot select
values. Refer to the
Booting and
Configuration
appendix in the Arria
10 Device Handbook
for Boot Select
values. This resistor
will not interfere with
the slow speed
interface signals that
could share this pin.
BOOTSEL0
(BSEL0)
During a
cold reset
this signal
is sampled
as a boot
select
input.
SDMMC
Power
Enable
PLL
Clock 0
QSPI
Slave
Select 1
SPIM0
Slave
Select 1
SPIS0
Master In
Slave
Out
SPIM0
Clock
NAND
Command
Latch
Enable
NAND
Address
Latch
Enable
Page 43 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
Pin Type
(1st and
2nd
Function)
Connection
Guidelines
Pin Description
I2C
EMAC1
Serial
Data
SDMMC
Data Bit 4
MDIO1
MDIO
SPIM0
Master
Out
Slave In
UART1
Transmit
NAND
Ready/Busy
General
Purpose
IO 2 Bit 8
If used as the NAND
Ready/Busy input,
connect this pin
through a 1-kΩ - 10kΩ pull-up resistor to
VCCIO_HPS in the
dedicated I/O bank
which the NAND_RB
pin resides. If
unused, program it in
the Quartus II
software as an input
with a weak pull-up.
HPS_DEDICATED_12
I/O
PLL
Clock 1
HPS_DEDICATED_13
I/O
PLL
Clock 2
I2C
EMAC1
Serial
Clock
SDMMC
Data Bit 5
MDIO1
MDC
SPIM0
Master In
Slave
Out
UART1
Request
to Send
NAND Chip
Enable
General
Purpose
IO 2 Bit 9
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
I/O
PLL
Clock 3
I2C
EMAC2
Serial
Data
SDMMC
Data Bit 6
MDIO2
MDIO
SPIM0
Slave
Select 0
UART1
Clear to
Send
NAND Data
Bit 4
General
Purpose
IO 2 Bit
10
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
I/O
PLL
Clock 4
I2C
EMAC2
Serial
Clock
SDMMC
Data Bit 7
MDIO2
MDC
SPIS0
Clock
UART1
Receive
NAND Data
Bit 5
General
Purpose
IO 2 Bit
11
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_DEDICATED_14
HPS_DEDICATED_15
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 44 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
HPS_DEDICATED_16
HPS_DEDICATED_17
Pin Type
(1st and
2nd
Function)
Connection
Guidelines
Pin Description
I/O
QSPI
Slave
Select 2
I2C
EMAC0
Serial
Data
MDIO0
MDIO
SPIS0
Master
Out
Slave In
I/O
QSPI
Slave
Select 3
I2C
EMAC0
Serial
Clock
MDIO0
MDC
SPIS0
Slave
Select 0
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Transmit
NAND Data
Bit 6
General
Purpose
IO 2 Bit
12
UART1
Receive
NAND Data
Bit 7
General
Purpose
IO 2 Bit
13
UART1
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
Page 45 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
Pin Type
(1st and
2nd
Function)
Pin Description
Connection Guidelines
Shared 3V I/O Bank
Function 7
HPS_Shared_Q1_1
I/O
Function 6
Function 5
Function 4
Function 3
Function 2
SPIM0
Slave
Select 1
SDMMC
Data Bit 0
USB0
Clock
SPIS0
Clock
SDMMC
Command
Line
USB0
Stop Data
SPIS0
Master
Out
Slave In
UART0
Request
to Send
UART0
Clear
to
Send
Function
1
NAND
Data Bit 0
Function 0
General
Purpose
IO 0 Bit
0
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q1_2
I/O
SPIM1
Slave
Select 1
HPS_Shared_Q1_3
I/O
I2C1
Serial
Data
SDMMC
Clock Out
USB0
Direction
SPIS0
Slave
Select
0
UART0
Transmit
NAND
Write
Enable
General
Purpose
IO 0 Bit
2
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q1_4
I/O
I2C1
Serial
Clock
SDMMC
Data Bit 1
USB0
Data Bit 0
SPIS0
Master
In Slave
Out
UART0
Receive
NAND
Read
Enable
General
Purpose
IO 0 Bit
3
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q1_5
I/O
QSPI
Slave
Select 2
I2C0
Serial
Data
SDMMC
Data Bit 2
USB0
Data Bit 1
SPIM0
Clock
UART1
Clear
to
Send
NAND
Write
Protect
General
Purpose
IO 0 Bit
4
I/O
QSPI
Slave
Select 3
I2C0
Serial
Clock
SDMMC
Data Bit 3
USB0
Next Data
SPIM0
Master
Out
Slave In
UART1
Request
to Send
NAND
Data Bit 2
General
Purpose
IO 0 Bit
5
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
EMAC
2
MDIO
I2C
EMAC2
Serial
Data
SDMMC
Data Bit 4
USB0
Data Bit 2
SPIM0
Master
In
SlaveOut
UART1
Transmit
NAND
Data Bit 3
General
Purpose
IO 0 Bit
6
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q1_6
HPS_Shared_Q1_7
I/O
PCG-01017-1.6
Copyright © 2015 Altera Corp.
NAND
Data Bit 1
General
Purpose
IO 0 Bit
1
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
Page 46 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
Pin Type
(1st and
2nd
Function)
Pin Description
Connection Guidelines
I/O
EMAC
2 MDC
I2C
EMAC2
Serial
Clock
SDMMC
Data Bit 5
USB0
Data Bit 3
SPIM0
Slave
Select
0
UART1
Receive
NAND
Command
Latch
Enable
HPS_Shared_Q1_9
I/O
EMAC
1
MDIO
I2C
EMAC1
Serial
Data
SDMMC
Data Bit 6
USB0
Data Bit 4
SPIM1
Clock
SPIS1
Clock
NAND
Data Bit 4
HPS_Shared_Q1_10
I/O
EMAC
1 MDC
I2C
EMAC1
Serial
Clock
SDMMC
Data Bit 7
USB0
Data Bit 5
SPIM1
Master
Out
Slave In
SPIS1
Master
Out
Slave
In
EMAC
0
MDIO
I2C
EMAC0
Serial
Data
USB0
Data Bit 6
SPIM1
Master
In Slave
Out
SPIS1
Slave
Select
0
EMAC
0 MDC
I2C
EMAC0
Serial
Clock
USB0
Data Bit 7
SPIM1
Slave
Select
0
HPS_Shared_Q1_8
HPS_Shared_Q1_11
I/O
HPS_Shared_Q1_12
I/O
HPS_Shared_Q2_1
I/O
PCG-01017-1.6
Copyright © 2015 Altera Corp.
EMAC0
Transmit
Clock
USB1
Clock
SPIS1
Master
In Slave
Out
General
Purpose
IO 0 Bit
7
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
General
Purpose
IO 0 Bit
8
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit 5
General
Purpose
IO 0 Bit
9
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit 6
General
Purpose
IO 0 Bit
10
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit 7
General
Purpose
IO 0 Bit
11
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
General
Purpose
IO 0 Bit
12
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Address
Latch
Enable
Page 47 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
Pin Type
(1st and
2nd
Function)
Pin Description
Connection Guidelines
HPS_Shared_Q2_2
I/O
EMAC0
Transmit
Control
USB1
Stop Data
NAND
Ready/
Busy
General
Purpose
IO 0 Bit
13
HPS_Shared_Q2_3
I/O
EMAC0
Receive
Clock
USB1
Direction
NAND
Chip
Enable
General
Purpose
IO 0 Bit
14
HPS_Shared_Q2_4
I/O
EMAC0
Receive
Control
USB1
Data Bit 0
HPS_Shared_Q2_5
I/O
EMAC0
Transmit
Data Bit 0
USB1
Data Bit 1
NAND
Data Bit 8
HPS_Shared_Q2_6
I/O
EMAC0
Transmit
Data Bit 1
USB1
Next Data
NAND
Data Bit 9
HPS_Shared_Q2_7
I/O
EMAC0
Receive
Data Bit 0
USB1
Data Bit 2
NAND
Data Bit
10
PCG-01017-1.6
Copyright © 2015 Altera Corp.
General
Purpose
IO 0 Bit
15
General
Purpose
IO 0 Bit
16
General
Purpose
IO 0 Bit
17
General
Purpose
IO 0 Bit
18
If used as the NAND
Ready/Busy input,
connect this pin
through a 1-kΩ - 10kΩ pull- up resistor to
VCCIO_HPS in the
dedicated I/O bank
which the NAND_RB
pin resides. If
unused, program it in
the Quartus II software
as an input with a
weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
Page 48 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
Pin Type
(1st and
2nd
Function)
Pin Description
Connection Guidelines
SPIM1
Slave
Select 1
NAND
Data Bit
11
General
Purpose
IO 0 Bit
19
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
SPIS0
Clock
NAND
Data Bit
12
General
Purpose
IO 0 Bit
20
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
SPIM1
Master
Out
Slave In
SPIS0
Master
Out
Slave
In
NAND
Data Bit
13
General
Purpose
IO 0 Bit
21
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
USB1
Data Bit 6
SPIM1
Master
In Slave
Out
SPIS0
Slave
Select
0
NAND
Data Bit
14
General
Purpose
IO 0 Bit
22
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
USB1
Data Bit 7
SPIM1
Slave
Select
0
SPIS0
Master
In Slave
Out
NAND
Data Bit
15
General
Purpose
IO 0 Bit
23
SPIM1
Clock
NAND
Data Bit 0
General
Purpose
IO 1 Bit
0
SPIM1
Master
Out
Slave In
NAND
Data Bit 1
EMAC0
Receive
Data Bit 1
USB1
Data Bit 3
HPS_Shared_Q2_8
I/O
HPS_Shared_Q2_9
I/O
UART0
Clear to
Send
I2C1
Serial
Data
EMAC0
Transmit
Data Bit 2
USB1
Data Bit 4
SPIM1
Clock
HPS_Shared_Q2_10
I/O
UART0
Request
to Send
I2C1
Serial
Clock
EMAC0
Transmit
Data Bit 3
USB1
Data Bit 5
HPS_Shared_Q2_11
I/O
UART0
Transmit
I2C0
Serial
Data
EMAC0
Receive
Data Bit 2
HPS_Shared_Q2_12
I/O
UART0
Receive
I2C0
Serial
Clock
EMAC0
Receive
Data Bit 3
HPS_Shared_Q3_1
I/O
UART0
Clear to
Send
EMAC1
Transmit
Clock
HPS_Shared_Q3_2
I/O
UART0
Request
to Send
EMAC1
Transmit
Control
PCG-01017-1.6
Copyright © 2015 Altera Corp.
General
Purpose
IO 1 Bit
1
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
Page 49 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
Pin Type
(1st and
2nd
Function)
Pin Description
Connection Guidelines
HPS_Shared_Q3_3
I/O
UART0
Transmit
I2C0
Serial
Data
EMAC1
Receive
Clock
SPIM1
Master
In Slave
Out
NAND
Write
Enable
General
Purpose
IO 1 Bit
2
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q3_4
I/O
UART0
Receive
I2C0
Serial
Clock
EMAC1
Receive
Control
SPIM1
Slave
Select
0
NAND
Read
Enable
General
Purpose
IO 1 Bit
3
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q3_5
I/O
UART1
Clear to
Send
EMAC1
Transmit
Data Bit 0
SPIM1
slave
select 1
NAND
Write
Protect
General
Purpose
IO 1 Bit
4
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q3_6
I/O
UART1
Request
to Send
EMAC1
Transmit
Data Bit 1
NAND
Data Bit 2
General
Purpose
IO 1 Bit
5
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q3_7
I/O
UART1
Transmit
I2C1
Serial
Data
EMAC1
Receive
Data Bit 0
SPIS1
Slave
Select
0
NAND
Data Bit 3
General
Purpose
IO 1 Bit
6
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q3_8
I/O
UART1
Receive
I2C1
Serial
Clock
EMAC1
Receive
Data Bit 1
SPIS1
Master
In Slave
Out
NAND
Command
Latch
Enable
General
Purpose
IO 1 Bit
7
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
I/O
EMAC
2
MDIO
I2C
EMAC2
Serial
Data
EMAC1
Transmit
Data Bit 2
SPIS0
Clock
NAND
Data Bit 4
General
Purpose
IO 1 Bit
8
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
HPS_Shared_Q3_9
PCG-01017-1.6
Copyright © 2015 Altera Corp.
SPIS1
Clock
SPIS1
Master
Out
Slave
In
Page 50 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
HPS_Shared_Q3_10
Pin Type
(1st and
2nd
Function)
I/O
Pin Description
EMAC
2 MDC
HPS_Shared_Q3_11
I/O
EMAC
0
MDIO
HPS_Shared_Q3_12
I/O
EMAC
0 MDC
Connection Guidelines
I2C
EMAC2
Serial
Clock
EMAC1
Transmit
Data Bit 3
I2C
EMAC0
Serial
Data
EMAC1
Receive
Data Bit 2
SPIS0
Slave
Select
0
NAND
Data Bit 6
General
Purpose
IO 1 Bit
10
I2C
EMAC0
Serial
Clock
EMAC1
Receive
Data Bit 3
SPIS0
Master
In Slave
Out
NAND
Data Bit 7
General
Purpose
IO 1 Bit
11
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
EMAC2
Transmit
Clock
SDMMC
Data Bit 0
NAND
Address
Latch
Enable
General
Purpose
IO 1 Bit
12
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
EMAC2
Transmit
Control
SDMMC
Command
Line
NAND
Ready/
Busy
General
Purpose
IO 1 Bit
13
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Chip
Enable
General
Purpose
IO 1 Bit
14
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
General
Purpose
IO 1 Bit
15
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
SPIS0
Master
Out
Slave
In
HPS_Shared_Q4_1
I/O
I2C1
Serial
Data
HPS_Shared_Q4_2
I/O
I2C1
Serial
Clock
HPS_Shared_Q4_3
I/O
EMAC2
Receive
Clock
SDMMC
Clock Out
UART1
Transmit
I/O
EMAC2
Receive
Control
SDMMC
Data Bit 1
UART1
Receive
HPS_Shared_Q4_4
PCG-01017-1.6
Copyright © 2015 Altera Corp.
NAND
Data Bit 5
Trace clock
General
Purpose
IO 1 Bit
9
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
Page 51 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
HPS_Shared_Q4_5
HPS_Shared_Q4_6
HPS_Shared_Q4_7
HPS_Shared_Q4_8
Pin Type
(1st and
2nd
Function)
Pin Description
I/O
QSPI
Slave
Select 2
EMAC2
Transmit
Data Bit 0
SDMMC
Data Bit 2
UART1
Clear
to
Send
I/O
QSPI
Slave
Select 3
EMAC2
Transmit
Data Bit 1
SDMMC
Data Bit 3
UART1
Request
to Send
I/O
EMAC
1
MDIO
I2C
EMAC1
Serial
Data
EMAC2
Receive
Data Bit 0
SDMMC
Data Bit 4
SPIM0
Master
In Slave
Out
EMAC
1 MDC
I2C
EMAC1
Serial
Clock
EMAC2
Receive
Data Bit 1
SDMMC
Data Bit 5
SPIM0
Slave
Select
0
I2C
EMAC2
Serial
Data
EMAC2
Transmit
Data Bit 2
SDMMC
Data Bit 6
SPIM0
Clock
SPIS1
Clock
I2C
EMAC2
Serial
Clock
EMAC2
Transmit
Data Bit 3
SDMMC
Data Bit 7
SPIM0
Master
Out
Slave In
SPIS1
Master
Out
Slave
In
I2C
EMAC0
Serial
Data
EMAC2
Receive
Data Bit 2
Trace data
2
SPIM0
Master
In Slave
Out
SPIS1
Slave
Select
0
I/O
Trace data 0
HPS_Shared_Q4_9
I/O
Trace data 1
HPS_Shared_Q4_10
HPS_Shared_Q4_11
Connection Guidelines
I/O
I/O
PCG-01017-1.6
Copyright © 2015 Altera Corp.
EMAC0
MDIO
SPIM0
slave select
1
Trace
clock
NAND
Data Bit 8
General
Purpose
IO 1 Bit
16
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit 9
General
Purpose
IO 1 Bit
17
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit
10
General
Purpose
IO 1 Bit
18
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit
11
General
Purpose
IO 1 Bit
19
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit
12
General
Purpose
IO 1 Bit
20
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit
13
General
Purpose
IO 1 Bit
21
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
NAND
Data Bit
14
General
Purpose
IO 1 Bit
22
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
Page 52 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Arria 10 HPS Pin
Name
HPS_Shared_Q4_12
Pin Type
(1st and
2nd
Function)
I/O
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Pin Description
EMAC
0 MDC
Connection Guidelines
I2C
EMAC0
Serial
Clock
EMAC2
Receive
Data Bit 3
Trace data
3
SPIM0
Slave
Select
0
SPIS1
Master
In Slave
Out
NAND
Data Bit
15
General
Purpose
IO 1 Bit
23
If unused, program it
in the Quartus II
software as an input
with a weak pull-up.
Page 53 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
®
Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin
connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage
assignments, and other factors that are not fully described in this document or the device handbook.
Notes to Arria 10 SX Pin Connection Guidelines
Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper
device functionality.
1.
2.
These pin connection guidelines are based on the Arria 10 SX device variant.
Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being
decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the
appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper
board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
3. Use the Arria 10 Early Power Estimator (EPE) to determine the preliminary current requirements for VCC and other power supplies. Use the Quartus II PowerPlay Power Analyzer for
the most accurate current requirements for this and other power supplies.
4. These supplies may share power planes across multiple Arria 10 devices.
5. Power pins should not share breakout vias from the BGA. Each ball on the BGA must have its own dedicated breakout via.
6. Example 6, Example 7, Figure 6, and Figure 7 illustrate the power supply sharing guidelines for the Arria 10 SX devices.
7. Low Noise Switching Regulator - a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support
components. The switching frequency is usually between 800 kHz and 1 MHz and has fast transient response. The switching frequency range is not an Altera requirement. However,
Altera does require the Line Regulation and Load Regulation meet the following specifications:
•
Line Regulation < 0.4%
•
Load Regulation < 1.2%
8. The number of modular I/O banks on Arria 10 devices depends on the device density. For the indexes available for a specific device, refer to the I/O Bank section in the Arria 10
handbook.
9. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires that the AC-coupling capacitor is placed on the transmitter
side of the interface that permits adapters to be plugged and unplugged.
10. For item [#], refer to the device pin table for the pin-out mapping.
11. The peripheral pins are programmable through pin multiplexors. Each pin may have multiple functions. HPS dedicated I/O pin multiplexing is programmable using the HPS software.
The pin mux will determine how the pins are used.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 54 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Power Supply Sharing Guidelines for Arria 10 Devices
Arria 10 GX
Example 1. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
Example Requiring 2 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator Sharing
Notes
Share
You have the option to source VCC and VCCP from the same regulator as
VCCERAM when all the power rails require the same voltage level. When
sharing the same regulator for VCCERAM, VCC, and VCCP, the SmartVID
feature is not available. If you use the SmartVID feature, then VCC and
VCCP needs to be sourced by a separate dedicated regulator.
VCC
0.9
VCCP
VCCERAM
VCCR_GXB[L,R]
1
± 30mV
Switcher (*)
0.9
Isolate
VCCT_GXB[L,R]
When implementing a filtered supply topology, you must consider the IR
drop across the filter. For designs that have high-current for VCCR_GXB or
VCCT_GXB, you should consider the IR drop through the supply planes
and compensate for it.
VCCBAT
Varies
VCCPT
VCCIO
VCCPGM
Option provided to share VCCR_GXB and VCCT_GXB with the same
regulator as VCC, VCCP, and VCCERAM when all power rails require 0.9V
with a proper isolation filter. For details, refer to note 1 of the Notes to
Power Supply Sharing Guidelines. For better performance and in order to
meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB
from each other with at least 30dB of isolation for a 1MHz to 100MHz
bandwidth.
1.8
2
VCCH_GXB[L,R]
VCCA_PLL
Varies
1.8
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, and VCCPGM to share the
same regulator when all power rails required 1.8V. Depending on the
regulator capabilities, you have the option to share this supply with multiple
Arria 10 devices.
Isolate
Option provided to share VCCH_GXB and VCCA_PLL with the same
regulator as VCCBAT, VCCPT, VCCIO, and VCCPGM when all power rails
require 1.8V with a proper isolation filter.
Switcher (*)
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 GX device is provided in Figure 1.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 55 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 1. Example Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane
Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 56 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 GX
Example 2. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
Example Requiring 3 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator Sharing
Notes
Share
You have the option to source VCC and VCCP from the same regulator as
VCCERAM when all the power rails require the same voltage level. When
sharing the same regulator for VCCERAM, VCC, and VCCP, the SmartVID
feature is not available. If you use the SmartVID feature, then VCC and
VCCP needs to be sourced by a separate dedicated regulator.
VCC
VCCP
1
0.95
± 30mV
Switcher (*)
VCCERAM
For better performance and in order to meet PCIe Gen 3 jitter
specifications, isolate VCCR_GXB and VCCT_GXB from each other with at
least 30dB of isolation for a 1MHz to 100MHz bandwidth.
VCCR_GXB[L,R]
2
0.9
± 30mV
Switcher (*)
Share
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate for
it.
VCCT_GXB[L,R]
VCCBAT
Varies
VCCPT
VCCIO
VCCPGM
1.8
3
VCCH_GXB[L,R]
VCCA_PLL
Varies
1.8
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, and VCCPGM to share the
same regulator when all power rails required 1.8V. Depending on the
regulator capabilities, you have the option to share this supply with multiple
Arria 10 devices.
Isolate
Option provided to share VCCH_GXB and VCCA_PLL with the same
regulator as VCCBAT, VCCPT, VCCIO, and VCCPGM when all power rails
require 1.8V with a proper isolation filter.
Switcher (*)
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 GX device is provided in Figure 2.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 57 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 2. Example Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane
Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 58 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 GX
Example 3. Power Supply Sharing Guidelines for Arria 10 GX with 11.3 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications
(10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for Backplane Applications)
Example Requiring 3 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator Sharing
VCC, VCCP, and VCCERAM support 0.9V and 0.95V. You have the
option to source VCC and VCCP from the same regulator as VCCERAM
when all the power rails require the same voltage level. For more details,
refer to the Electrical Specifications in the Arria 10 device datasheet.
VCC
VCCP
1
0.9/0.95
± 30mV
Switcher (*)
Share
VCCERAM
VCCR_GXB[L,R]
2
1.03
± 30mV
Switcher (*)
Share
VCCT_GXB[L,R]
When sharing the same regulator for VCCERAM, VCC, and VCCP, the
SmartVID feature is not available. If you use the SmartVID feature, then
VCC and VCCP needs to be sourced by a separate dedicated regulator.
Option provided for VCCR_GXB and VCCT_GXB to share the same
regulator when all power rails required the same voltage level. For details,
refer to note 4 of the Notes to Power Supply Sharing Guidelines. For better
performance and in order to meet PCIe Gen 3 jitter specifications, isolate
VCCR_GXB and VCCT_GXB from each other with at least 30dB of
isolation for a 1MHz to 100MHz bandwidth.
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate
for it.
VCCBAT
Varies
VCCPT
1.8
VCCIO
VCCPGM
Notes
3
Varies
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO and VCCPGM to share the
same regulator when all power rails require 1.8V. Depending on the
regulator capabilities, you have the option to share this supply with
multiple Arria 10 devices.
Isolate
Option provided to share VCCH_GXB and VCCA_PLL with the same
regulator as VCCBAT, VCCPT, VCCIO, and VCCPGM when all power
rails require 1.8V with a proper isolation filter.
Switcher (*)
VCCH_GXB[L,R]
1.8
VCCA_PLL
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 GX device is provided in Figure 3.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 59 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 3. Example Power Supply Sharing Guidelines for Arria 10 GX with 11.3 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications
(10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for Backplane Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 60 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 GT
Example 4. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
(10.3125 Gbps for Backplane Applications)
Example Requiring 2 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator
Sharing
Notes
Share
You have the option to source VCC and VCCP from the same regulator as
VCCERAM when all the power rails require the same voltage level. When
sharing the same regulator for VCCERAM, VCC, and VCCP, the SmartVID
feature is not available. If you use the SmartVID feature, then VCC and
VCCP needs to be sourced by a separate dedicated regulator.
VCC
0.9
VCCP
VCCERAM
VCCR_GXB[L,R]
1
± 30mV
Switcher (*)
0.9
Isolate
VCCT_GXB[L,R]
When implementing a filtered supply topology, you must consider the IR
drop across the filter. For designs that have high-current for VCCR_GXB or
VCCT_GXB, you should consider the IR drop through the supply planes
and compensate for it.
VCCBAT
Varies
VCCPT
1.8
VCCIO
VCCPGM
Option provided to share VCCR_GXB and VCCT_GXB with the same
regulator as VCC, VCCP, and VCCERAM when all power rails require 0.9V
with a proper isolation filter. For details, refer to note 1 of the Notes to
Power Supply Sharing Guidelines. For better performance and in order to
meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB
from each other with at least 30dB of isolation for a 1MHz to 100MHz
bandwidth.
2
Varies
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, and VCCPGM to share the
same regulator when all power rails require 1.8V. Depending on the
regulator capabilities, you have the option to share this supply with multiple
Arria 10 devices.
Isolate
Option provided to share VCCH_GXB and VCCA_PLL with the same
regulator as VCCBAT, VCCPT, VCCIO, and VCCPGM when all power rails
require 1.8V with a proper isolation filter.
Switcher (*)
VCCH_GXB[L,R]
1.8
VCCA_PLL
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 GT device is provided in Figure 4.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 61 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 4. Example Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane
Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 62 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 GT
Example 5. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
(10.3125 Gbps for Backplane Applications)
Example Requiring 3 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator
Sharing
Notes
Share
You have the option to source VCC and VCCP from the same regulator as
VCCERAM when all the power rails require the same voltage level. When
sharing the same regulator for VCCERAM, VCC, and VCCP, the SmartVID
feature is not available. If you use the SmartVID feature, then VCC and
VCCP needs to be sourced by a separate dedicated regulator.
VCC
VCCP
1
0.95
± 30mV
Switcher (*)
VCCERAM
For better performance and in order to meet PCIe Gen 3 jitter
specifications, isolate VCCR_GXB and VCCT_GXB from each other with at
least 30dB of isolation for a 1MHz to 100MHz bandwidth.
VCCR_GXB[L,R]
2
0.9
± 30mV
Switcher (*)
Share
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate for
it.
VCCT_GXB[L,R]
VCCBAT
Varies
VCCPT
1.8
VCCIO
VCCPGM
3
Varies
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, and VCCPGM to share the
same regulator when all power rails require 1.8V. Depending on the
regulator capabilities, you have the option to share this supply with multiple
Arria 10 devices.
Isolate
Option provided to share VCCH_GXB and VCCA_PLL with the same
regulator as VCCBAT, VCCPT, VCCIO, and VCCPGM when all power rails
require 1.8V with a proper isolation filter.
Switcher (*)
VCCH_GXB[L,R]
1.8
VCCA_PLL
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 GT device is provided in Figure 5.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 63 of 82
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Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 5. Example Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane
Applications)
PCG-01017-1.6
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Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 GT
Example 6. Power Supply Sharing Guidelines for Arria 10 GT with 11.3 Gbps < Transceiver Data Rate <= 15.0 Gbps(**) for Chip-to-Chip Applications
(10.3125 Gbps < Transceiver Data Rate <= 14.2 Gbps(**) for Backplane Applications)
Example Requiring 3 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator
Sharing
VCC
VCCP
1
0.9/0.95
± 30mV
Switcher (*)
Share
VCCERAM
VCCR_GXB[L,R]
2
1.03
± 30mV
Switcher (*)
Share
VCCT_GXB[L,R]
VCC, VCCP, and VCCERAM support 0.9V and 0.95V. You have the option
to source VCC and VCCP from the same regulator as VCCERAM when all
the power rails require the same voltage level. For more details, refer to the
Electrical Specifications in the Arria 10 device datasheet.
When sharing the same regulator for VCCERAM, VCC, and VCCP, the
SmartVID feature is not available. If you use the SmartVID feature, then
VCC and VCCP needs to be sourced by a separate dedicated regulator.
Option provided for VCCR_GXB and VCCT_GXB to share the same
regulator when all power rails require the same voltage level. For details,
refer to note 4 of the Notes to Power Supply Sharing Guidelines. For better
performance and in order to meet PCIe Gen 3 jitter specifications, isolate
VCCR_GXB and VCCT_GXB from each other with at least 30dB of
isolation for a 1MHz to 100MHz bandwidth.
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate for
it.
VCCBAT
Varies
VCCPT
1.8
VCCIO
VCCPGM
Notes
3
Varies
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, and VCCPGM to share the
same regulator when all power rails require 1.8V. Depending on the
regulator capabilities, you have the option to share this supply with multiple
Arria 10 devices.
Isolate
Option provided to share VCCH_GXB and VCCA_PLL with the same
regulator as VCCBAT, VCCPT, VCCIO, and VCCPGM when all power rails
require 1.8V with a proper isolation filter.
Switcher (*)
VCCH_GXB[L,R]
1.8
VCCA_PLL
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 GT device is provided in Figure 6.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
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Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 6. Example Power Supply Sharing Guidelines for Arria 10 GT with 11.3 Gbps < Transceiver Data Rate <= 15.0 Gbps(**) for Chip-to-Chip Applications
(10.3125 Gbps < Transceiver Data Rate <= 14.2 Gbps(**) for Backplane Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 GT
Example 7. Power Supply Sharing Guidelines for Arria 10 GT with 15.0 Gbps < Transceiver Data Rate <= 17.4 Gbps(**)/28.3 Gbps for Chip-to-Chip Applications
(14.2 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Backplane Applications)
Example Requiring 4 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator
Sharing
VCC
VCCP
1
0.9/0.95
± 30mV
Switcher (*)
Share
VCC, VCCP, and VCCERAM support 0.9V and 0.95V. You have the option
to source VCC and VCCP from the same regulator as VCCERAM when all
the power rails require the same voltage level. For more details, refer to the
Electrical Specifications in the Arria 10 device datasheet.
When sharing the same regulator for VCCERAM, VCC, and VCCP, the
SmartVID feature is not available. If you use the SmartVID feature, then
VCC and VCCP needs to be sourced by a separate dedicated regulator.
You have the option to source VCCR_GXB from a switcher. For details,
refer to note 6 of the Notes to Power Supply Sharing Guidelines.
VCCERAM
VCCR_GXB[L,R]
2
1.11
± 30mV
Switcher (*)
Isolate
VCCT_GXB[L,R]
3
1.11
± 30mV
Switcher (*)
Isolate
VCCBAT
Varies
VCCPT
1.8
VCCIO
VCCPGM
Notes
4
Varies
± 5% (**)
VCCA_PLL
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate for
it.
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, and VCCPGM to share the
same regulator when all power rails require 1.8V. Depending on the
regulator capabilities, you have the option to share this supply with multiple
Arria 10 devices.
Isolate
Option provided to share VCCH_GXB and VCCA_PLL with the same
regulator as VCCBAT, VCCPT, VCCIO, and VCCPGM when all power rails
require 1.8V with a proper isolation filter.
Switcher (*)
VCCH_GXB[L,R]
1.8
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate for
it.
You have the option to source VCCT_GXB from a switcher. For details,
refer to note 6 of the Notes to Power Supply Sharing Guidelines.
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 GT device is provided in Figure 7.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
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Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 7. Example Supply Sharing Guidelines for Arria 10 GT with 15.0 Gbps < Transceiver Data Rate <= 17.4 Gbps(**)/28.3 Gbps for Chip-to-Chip Applications
(14.2 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Backplane Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 SX
Example 8. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
Example Requiring 2 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator
Sharing
Notes
Share
if 0.9V
You have the option to source VCC, VCCP, and VCCERAM from the same
regulator as VCCL_HPS when all the power rails require the same voltage
level. When sharing the same regulator for VCCERAM, VCCL_HPS, VCC,
and VCCP, the SmartVID feature is not available. If you use the SmartVID
feature, then VCC and VCCP needs to be sourced by a separate dedicated
regulator.
VCC
VCCP
VCCERAM
VCCL_HPS
VCCR_GXB[L,R]
1
0.9
± 30mV
Switcher (*)
Isolate
Option provided to share VCCR_GXB and VCCT_GXB with the same
regulator as VCC, VCCP, VCCERAM and VCCL_HPS when all power rails
require 0.9V but only with a proper isolation filter. For details, refer to note 1
of the Notes to Power Supply Sharing Guidelines. For better performance
and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB
and VCCT_GXB from each other with at least 30dB of isolation for a 1MHz
to 100MHz bandwidth.
VCCT_GXB[L,R]
When implementing a filtered supply topology, you must consider the IR
drop across the filter. For designs that have high-current for VCCR_GXB or
VCCT_GXB, you should consider the IR drop through the supply planes
and compensate for it.
VCCBAT
Varies
VCCPT
1.8
VCCIO
Varies
VCCPGM
VCCIO_HPS
2
VCCIOREF_HPS
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, VCCPGM, VCCIO_HPS,
and VCCIOREF_HPS to share the same regulator when all power rails
require 1.8V. Depending on the regulator capabilities, you have the option
to share this supply with multiple Arria 10 devices.
Isolate
Option provided to share VCCH_GXB, VCCA_PLL, and VCCPLL_HPS with
the same regulator as VCCBAT, VCCPT, VCCIO, VCCPGM, VCCIO_HPS,
and VCCIOREF_HPS when all power rails require 1.8V with a proper
isolation filter.
Switcher (*)
1.8
VCCH_GXB[L,R]
VCCA_PLL
VCCPLL_HPS
1.8
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to HPS Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 SX device is provided in Figure 8.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 8. Example Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane
Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 SX
Example 9. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
Example Requiring 3 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator
Sharing
Notes
Share
if 0.95V
You have the option to source VCC, VCCP, and VCCERAM from the same
regulator as VCCL_HPS when all the power rails require the same voltage
level. When sharing the same regulator for VCCERAM, VCCL_HPS, VCC,
and VCCP, the SmartVID feature is not available. If you use the SmartVID
feature, then VCC and VCCP needs to be sourced by a separate dedicated
regulator.
VCC
VCCP
1
0.95
± 30mV
Switcher (*)
VCCERAM
VCCL_HPS
For better performance and in order to meet PCIe Gen 3 jitter
specifications, isolate VCCR_GXB and VCCT_GXB from each other with at
least 30dB of isolation for a 1MHz to 100MHz bandwidth.
VCCR_GXB[L,R]
2
0.9
± 30mV
Switcher (*)
Share
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate for
it.
VCCT_GXB[L,R]
VCCBAT
Varies
VCCPT
1.8
VCCIO
Varies
VCCPGM
VCCIO_HPS
3
VCCIOREF_HPS
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, VCCPGM, VCCIO_HPS,
and VCCIOREF_HPS to share the same regulator when all power rails
require 1.8V. Depending on the regulator capabilities, you have the option
to share this supply with multiple Arria 10 devices.
Isolate
Option provided to share VCCH_GXB, VCCA_PLL, and VCCPLL_HPS with
the same regulator as VCCBAT, VCCPT, VCCIO, VCCPGM, VCCIO_HPS,
and VCCIOREF_HPS when all power rails require 1.8V with a proper
isolation filter.
Switcher (*)
1.8
VCCH_GXB[L,R]
VCCA_PLL
VCCPLL_HPS
1.8
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to HPS Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 SX device is provided in Figure 9.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 9. Example Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane
Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 SX
Example 10. Power Supply Sharing Guidelines for Arria 10 SX with 11.3 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications
(10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for Backplane Applications)
Example Requiring 3 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator
Sharing
VCC
VCCP
VCCERAM
1
0.9/0.95
± 30mV
Switcher (*)
Share
VCCL_HPS
VCCR_GXB[L,R]
2
1.03
± 30mV
Switcher (*)
Share
VCCT_GXB[L,R]
VCC, VCCP, VCCERAM, and VCCL_HPS support 0.9V and 0.95V. You
have the option to source VCC, VCCP, and VCCERAM from the same
regulator as VCCL_HPS when all the power rails require the same voltage
level. For more details, refer to the Electrical Specifications in the Arria 10
device datasheet.
When sharing the same regulator for VCCERAM, VCCL_HPS, VCC, and
VCCP, the SmartVID feature is not available. If you use the SmartVID
feature, then VCC and VCCP needs to be sourced by a separate dedicated
regulator.
Option provided for VCCR_GXB and VCCT_GXB to share the same
regulator when all power rails require the same voltage level. For details,
refer to note 4 of the Notes to Power Supply Sharing Guidelines. For better
performance and in order to meet PCIe Gen 3 jitter specifications, isolate
VCCR_GXB and VCCT_GXB from each other with at least 30dB of isolation
for a 1MHz to 100MHz bandwidth.
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate for
it.
VCCBAT
Varies
VCCPT
1.8
VCCIO
Varies
VCCPGM
VCCIO_HPS
Notes
3
VCCIOREF_HPS
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, VCCPGM, VCCIO_HPS,
and VCCIOREF_HPS to share the same regulator when all power rails
require 1.8V. Depending on the regulator capabilities, you have the option
to share this supply with multiple Arria 10 devices.
Isolate
Option provided to share VCCH_GXB, VCCA_PLL, and VCCPLL_HPS with
the same regulator as VCCBAT, VCCPT, VCCIO, VCCPGM, VCCIO_HPS,
and VCCIOREF_HPS when all power rails require 1.8V with a proper
isolation filter.
Switcher (*)
1.8
VCCH_GXB[L,R]
VCCA_PLL
VCCPLL_HPS
1.8
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to HPS Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 SX device is provided in Figure 10.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 10. Example Power Supply Sharing Guidelines for Arria 10 SX with 11.3 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications
(10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for Backplane Applications)
PCG-01017-1.6
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Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Arria 10 GX (Using the SmartVID Feature)
Example 11. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
Using the SmartVID Feature (***)
Example Requiring 3 Power Regulators
Power
Pin Name
Regulator Count
Voltage
Level (V)
Supply
Tolerance
Power
Source
Regulator Sharing
Notes
Share
If you use the SmartVID feature, VCC and VCCP needs to be sourced from
a separate dedicated regulator. For more details about the VCC and VCCP
voltage range when the SmartVID feature is enabled, refer to the device
datasheet.
VCC
1
Varies
± 30mV
Switcher (*)
VCCP
VCCERAM
VCCR_GXB[L,R]
2
0.9
± 30mV
Switcher (*)
Share
For designs that have high-current for VCCR_GXB or VCCT_GXB, you
should consider the IR drop through the supply planes and compensate for
it.
VCCT_GXB[L,R]
VCCBAT
Varies
VCCPT
VCCIO
VCCPGM
Option provided to share VCCR_GXB and VCCT_GXB with the same
regulator VCCERAM when all power rails require 0.9V. For details, refer to
note 1 of the Notes to Power Supply Sharing Guidelines. For better
performance and in order to meet PCIe Gen 3 jitter specifications, isolate
VCCR_GXB and VCCT_GXB from each other with at least 30dB of
isolation for a 1MHz to 100MHz bandwidth.
1.8
3
VCCH_GXB[L,R]
VCCA_PLL
Varies
1.8
± 5% (**)
Share
if 1.8V
Option provided for VCCBAT, VCCPT, VCCIO, and VCCPGM to share the
same regulator when all power rails required 1.8V. Depending on the
regulator capabilities, you have the option to share this supply with multiple
Arria 10 devices.
Isolate
Option provided to share VCCH_GXB and VCCA_PLL with the same
regulator as VCCBAT, VCCPT, VCCIO, and VCCPGM when all power rails
require 1.8V with a proper isolation filter.
Switcher (*)
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Arria 10 Device Datasheet.
(***) This is an example using the Arria 10 GX device when you are using the SmartVID feature. If you are using the SmartVID feature for other Arria 10 devices, do take note that you need to
source VCC and VCCP from a separate dedicated regulator.
Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the
Arria 10 GX device is provided in Figure 11.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Figure 11. Example Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane
Applications) Using the SmartVID Feature
PCG-01017-1.6
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Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Notes to Power Supply Sharing Guidelines
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 7 of the Notes to Pin Connection Guidelines.
1.
VCCR_GXB and VCCT_GXB must be at least 0.9V for the following transceiver data rates:
•
Arria 10 GX(**) and SX(**) devices: ≤10.3125 Gbps/6.5536 Gbps for backplane applications and ≤11.3 Gbps/8 Gbps for chip-to-chip applications.
•
Arria 10 GT(***) devices: ≤10.3125 Gbps for backplane applications and ≤11.3 Gbps for chip-to-chip applications.
When VCCR_GXB and VCCT_GXB is 0.9V, they may share the same regulator as VCC and VCCP with proper filtering, if VCC and VCCP is at the same voltage level.
2. Assumes VCCIO, VCCPGM, and VCCIO_HPS are 1.8V. Only if these power rails share the same regulator as VCCPT can their power sequence ramp with VCCPT in Group 2. If any
of these rails are other than 1.8V, then these rails must be separately regulated and must follow the power sequence requirement in Group 3. For more information about the power
sequence requirements, refer to the Power Management for Arria 10 Devices chapter in the Arria 10 Core Fabric and General Purpose I/O Handbook.
3. The VCC Power Manager and SmartVID features are supported for VCC and VCCP. In these cases, VCC and VCCP can be 0.83V-0.9V depending on the device requirements. The
VCC Power Manager and SmartVID features are not supported when VCCR_GXB and VCCT_GXB are shared with VCC and VCCP.
4. VCCR_GXB and VCCT_GXB must be at least 1.03V for the following transceiver data rates:
•
Arria 10 GX(**) and SX(**) devices: 10.3125 Gbps/6.5536 Gbps < transceiver data rate ≤ 16.0 Gbps/14.2 Gbps/12.5 Gbps/8 Gbps for backplane applications and
11.3 Gbps/8 Gbps < transceiver data rate ≤ 17.4 Gbps/15 Gbps/14.2 Gbps/12.5 Gbps/8 Gbps for chip-to-chip applications.
•
Arria 10 GT(***) devices: 10.3125 Gbps < transceiver data rate ≤ 12.5 Gbps/14.2 Gbps for backplane applications and
11.3 Gbps < transceiver data rate ≤ 12.5 Gbps/14.2 Gbps/15 Gbps for chip-to-chip applications.
5. The Arria 10 GT devices with transceiver data rate ≤ 11.3 Gbps for chip-to-chip applications (10.3125 Gbps for backplane applications) and 11.3 Gbps < transceiver data rate ≤ 12.5
Gbps/14.2 Gbps/15 Gbps for chip-to-chip applications (10.3125 Gbps < transceiver data rate ≤ 12.5 Gbps/14.2 Gbps for backplane applications), the maximum transceiver channel
supported on non 28.3 Gbps transceiver side is 48 channels.
6. VCCR_GXB and VCCT_GXB must be at least 1.11V for the following transceiver data rates (applicable only to Arria 10 GT devices):
•
For 12.5 Gbps/14.2 Gbps/15.0 Gbps < transceiver data rate ≤ 15 Gbps/17.4 Gbps for chip-to-chip applications, the maximum transceiver channel supported is 80 channels.
•
For 12.5 Gbps/14.2 Gbps/15.0 Gbps < transceiver data rate ≤ 20 Gbps/26 Gbps/28.3 Gbps for chip-to-chip applications, the maximum transceiver channel supported is 16
channels.
•
For 10.3125 Gbps/12.5 Gbps/14.2 Gbps < transceiver data rate ≤ 14.2 Gbps/17.4 Gbps for backplane applications, the maximum transceiver channel supported is 96 channels.
7. You have the option to source VCC and VCCP from the same regulator as VCCERAM when all the power rails require the same voltage level. When sharing the same regulator for
VCCERAM, VCC, and VCCP, the SmartVID feature is not available. If you use the SmartVID feature, then VCC and VCCP needs to be sourced by a separate dedicated regulator.
(**)Actual transceiver data rate for the Arria 10 GX and SX devices is dependent on the device’s transceiver speed grade and core speed grade. Valid combinations of transceiver and core
speed grades are as follows:
•
For -1 transceiver and -1 core speed grades
– the maximum data rate is 17.4 Gbps for chip-to-chip applications and 16 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.03V.
– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.
•
For -2 transceiver and -1 core speed grades
– the maximum data rate is 15 Gbps for chip-to-chip applications and 14.2 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.03V.
– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.
•
For -3 transceiver and -2 core speed grades
– the maximum data rate is 14.2 Gbps for chip-to-chip applications and 12.5 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.03V.
– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.
•
For -4 transceiver and -3 core speed grades
– the maximum data rate is 12.5 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.03V.
– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.
•
For -5 transceiver and -3 core speed grades
– the maximum data rate is 8 Gbps for chip-to-chip applications and 6.5536 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.03V/0.9V.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
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®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
(***)Actual transceiver data rate for the Arria 10 GT device is dependent on the device’s transceiver speed grade and core speed grade. Valid combinations of transceiver and core speed
grades are as follows:
•
For -2 transceiver and -1 core speed grades
– the maximum data rate is 28.3 Gbps for chip-to-chip applications and 17.4 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.11V.
– the maximum data rate is 15 Gbps for chip-to-chip applications and 14.2 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.03V.
– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.
•
For -3 transceiver and -2 core speed grades
– the maximum data rate is 26 Gbps for chip-to-chip applications and 14.2 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.11V.
– the maximum data rate is 14.2 Gbps for chip-to-chip applications and 12.5 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.03V.
– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.
•
For -4 transceiver and -3 core speed grades
– the maximum data rate is 20 Gbps for chip-to-chip applications and 14.2 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.11V.
– the maximum data rate is 12.5 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.03V.
– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.
The voltage level for each power rail is preliminary.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 78 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Revision History
Revision
Description of Changes
Date
1.0
Initial release.
12/2/2013
1.1
Updated the connection guidelines for VCC and VCCP pins.
12/18/2013
1.2
Updated the pin description and connection guidelines for the CLKUSR pin.
5/23/2014
•
•
•
•
•
•
•
•
1.3
Added note (7) to the Notes to Power Supply Sharing Guidelines section.
Updated the pin description for the PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_FB0 pins.
Updated the connection guidelines for the TCK, TMS, TDI, TDO, and TRST pins.
Updated the connection guidelines for the VCCR_GXB[L,R][1:4][C,D,E,F,G,H,I,J] and
VCCT_GXB[L,R][1:4][C,D,E,F,G,H,I,J] pins.
Updated the connection guidelines for the VCCLSENSE and GNDSENSE pins.
Updated the connection guidelines for the VCCBAT, VCCPGM, VCCPT, and VCCH_GXB[L,R] pins.
Updated the CRCERROR pin name.
Updated the following power sharing guidelines:
o
Example 1. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
o
Example 2. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate 11.3 Gbps < Data
Rates <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Data Rates <= 17.4 Gbps (**) for
Backplane Applications)
o
Example 3. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
o
Example 4. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate 11.3 Gbps < Data
Rates <= 15.0 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps < Data Rates <= 14.2 Gbps(**) for
Backplane Applications)
o
Example 5. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate 15.0 Gbps < Data
Rates <= 17.4 Gbps(**)/28 Gbps for Chip-to-Chip Applications (14.2 Gbps < Data Rates <= 17.4 Gbps(**) for
Backplane Applications)
o
Example 6. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
o
Example 7. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate 11.3 Gbps < Data
Rates <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Data Rates <= 17.4 Gbps (**) for
Backplane Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
6/24/2014
Page 79 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Revision
Description of Changes
•
1.4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.5
•
•
•
•
•
•
•
•
•
•
Date
Added Example 8. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications) Using the SmartVID Feature.
Updated the transceiver data rate to 28.3 Gbps.
Updated the pin name and pin description of the PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_FB[0,1] pins.
Updated the connection guidelines for the TCK, TMS, TDI, TDO, and TRST pins.
Updated the pin name and connection guidelines of the CRC_ERROR pin.
Updated the connection guidelines of the nPERST[L,R][0:1] pins.
Updated the connection guidelines of the VREFP_ADC pin.
Updated the connection guidelines of the VSIGP_[0,1] and VSIGN_[0,1] pins.
Updated the connection guidelines of the VCCP and VCC pins.
Updated the pin name of the VCCIO([2][A,F,G,H,I,J,K,L,AF,KL],[3][A,B,C,D,E,F,G,H,AB,GH]) pins.
Updated the connection guidelines of the VCCERAM pins.
Updated the connection guidelines of the VREFB([2][A,F,G,H,I,J,K,L],[3][A,B,C,D,E,F,G,H])N0 pins.
Updated the connection guidelines of the VCCLSENSE and GNDSENSE pins.
Updated the connection guidelines for the ADCGND pin.
Updated the pin name, pin description, and connection guidelines of the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.
Updated the pin name, pin description, and connection guidelines of the VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.
Updated the pin description and connection guidelines of the VCCH_GXB[L,R] pins.
Updated the pin name and pin description of the GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]p,
GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]n, GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]p,
GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]n pins.
Updated the pin name, pin description, and connection guidelines for the
REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]p and REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]n pins.
Updated the connection guidelines of the CLKUSR pins.
Updated the pin description and connection guidelines for the RREF_[T,B][L,R] pins.
Updated the Function 2 pin description of the HPS_DEDICATED_16 pin.
8/18/2014
Updated the connection guidelines for VCCIO([2][A, F,G,H,I,J,K, L, AF, KL], [3][A, B,C,D,E,F,G, H, AB, GH]) pins.
Updated the connection guidelines for the CONF_DONE pin.
Updated the connection guidelines for the nSTATUS pin.
Updated the connection guidelines for VREFP_ADC and VREFN_ADC pins.
Updated the pin type for VSIGP and VSIGN pins.
Updated the pin type for the HPS_nRST pin.
Updated the pin type for the HPS_nPOR pin.
Updated the pin description of the CRC_ERROR pin.
Updated the pin description of the HPS_nRST pin.
Updated the connection guidelines for VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] and VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J]
pins.
1/23/2015
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 80 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Revision
Description of Changes
•
•
•
•
Date
Updated the pin description for VCCIOREF_HPS pin.
Updated note (11) in the Notes to Arria 10 SX Pin Connection Guidelines.
Updated the following power sharing guidelines to include 0.95V support for VCC and VCCP:
o
Example 1. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
o
Example 3. Power Supply Sharing Guidelines for Arria 10 GX with 11.3 Gbps < Transceiver Data Rate <=
17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for
Backplane Applications)
o
Example 4. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
o
Example 6. Power Supply Sharing Guidelines for Arria 10 GT with 11.3 Gbps < Transceiver Data Rate <=
15.0 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps < Transceiver Data Rate <= 14.2 Gbps(**) for
Backplane Applications)
o
Example 7. Power Supply Sharing Guidelines for Arria 10 GT with 15.0 Gbps < Transceiver Data Rate <=
17.4 Gbps(**)/28.3 Gbps for Chip-to-Chip Applications (14.2 Gbps < Transceiver Data Rate <= 17.4
Gbps(**) for Backplane Applications)
o
Example 8. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
o
Example 10. Power Supply Sharing Guidelines for Arria 10 SX with 11.3 Gbps < Transceiver Data Rate <=
17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for
Backplane Applications)
Added the following power sharing guidelines:
o
Example 2. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
o
Example 5. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
o
Example 9. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for
Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Page 81 of 82
®
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Preliminary PCG-01017-1.6
Revision
Description of Changes
•
•
•
•
•
•
•
•
1.6
•
Updated the connection guidelines of VCCP and VCC pins.
Updated the connection guidelines of RREF [T,B][L,R] pins.
Updated the connection guidelines of nPERST[L,R][0:1] pins.
Updated the connection guidelines of the VREFP_ADC pins.
Updated the connection guidelines of the VCCERAM pin.
Updated the connection guidelines of VREFB[[2][A,F,G,H,I,J,K,L],[3][A,B,C,D,E,F,G,H]]N0 pins.
Updated the on-chip reference source to +/-10% in the connection guidelines of the VREFP_ADC pin.
Updated the supported nominal voltage of VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] and
VCCT_GXB[L1,R4][C,D,E,F,G,H,I,J] from 1.0V and 1.1V to 1.03V and 1.11V, respectively.
o
Updated the connection guidelines for VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] and
VCCT_GXB[L1,R4][C,D,E,F,G,H,I,J].
o
Updated the following power sharing guidelines for the supported nominal voltage of 1.03V and 1.11V for
VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4][C,D,E,F,G,H,I,J]:

Example 3. Power Supply Sharing Guidelines for Arria 10 GX with 11.3 Gbps < Transceiver Data
Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Transceiver Data Rate <=
17.4 Gbps (**) for Backplane Applications)

Example 6. Power Supply Sharing Guidelines for Arria 10 GT with 11.3 Gbps < Transceiver Data
Rate <= 15.0 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps < Transceiver Data Rate <=
14.2 Gbps(**) for Backplane Applications)

Example 7. Power Supply Sharing Guidelines for Arria 10 GT with 15.0 Gbps < Transceiver Data
Rate <= 17.4 Gbps(**)/28.3 Gbps for Chip-to-Chip Applications (14.2 Gbps < Transceiver Data
Rate <= 17.4 Gbps(**) for Backplane Applications)

Example 10. Power Supply Sharing Guidelines for Arria 10 SX with 11.3 Gbps < Transceiver Data
Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Transceiver Data Rate <=
17.4 Gbps (**) for Backplane Applications)
o
Updated the supported nominal voltage of 1.03V and 1.11V for VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] and
VCCT_GXB[L1,R4][C,D,E,F,G,H,I,J] in the Notes to Power Supply Sharing Guidelines.
Added Shared 3V I/O Bank pins for Arria 10 HPS.
PCG-01017-1.6
Copyright © 2015 Altera Corp.
Date
5/4/2015
Page 82 of 82