V - Cypress

Module 5:
Advanced Analog
Design
Signals and Sensors
PSoC’s enhanced analog features allow users to interface with
the outside world, the analog world. This can take place
through a variety of signal processing and sensor interface
possibilities.
Examples:
Signal Processing
Amplitude detection
Frequency detection
Modulation/Demodulation
Filtering
Analog Multipliers
FSK
Sensor Interfacing
Thermistors
Passive Infrared Detectors
Ultrasonic Receivers
Thermocouples
Pressure sensors
Strain Gauges
This tele-training module will equip you with the tools to begin
utilizing PSoC’s powerful analog resources.
2
Fundamentals
Every electrical interaction is
governed by a simple set of
equations:
Maxwell's Equations
and, because we're a Silicon
company, particle movement is
governed by:
The Schrödinger Wave Equation
Don't Panic, it's not that hard.
3
∫ E ⋅dS =
Qenclosed
ε0
∫ B⋅dS = 0
∫ E ⋅dL =
dΦ B
dt
dΦ E
∫ B ⋅ d L = µ 0 I + µ 0ε 0 dt
2m
d 2ϕ
[E − U ( x)]ϕ ( x)
=
−
2
2
dx
⎛ h ⎞
⎜
⎟
2
π
⎝
⎠
Fundamental Fundamentals
Replace Maxwell and Schrödinger with simple laws:
Ohm's Law
4
E = I ⋅R
Kirchoff's Law
∑I =0
Simple Algebra
y = m⋅ x +b
Simple Physics
f −3dB = 1
Nyquist Criterion
f sample ≥ 2 ⋅ f signal
2πRC
Op-amp Algebra
Op-amp behavior follows
two simple rules
1. Inputs draw no current.
2. The output will do whatever
is necessary to make the
voltage difference between
the inputs equal to zero.
5
Op-amp Negative Gain
Simple op-amp algebra
VIN − VINV VINV − VOUT
=
Ri
Rf
VINV is 0 only when
VIN/Ri = -VOUT/Rf
VOUT/VIN = -Rf/Ri
6
Vin
Ri
VINV
Rf
Vout
Op-amp Positive Gain
Inputs draw no current, so
Vneg=Vout * Ri/(Ri+Rf)
Inputs can only be equal
when
Vin=Vout*(Ri/(Ri+Rf)
Vout/Vin = 1 + Rf/Ri
7
Ri
Vin
Rf
Vout
Sine Wave
Examine signal examples
Sine wave
Single frequency
Zero intentional harmonics
8
Square Wave
Square wave
Harmonics amplitude 1/n
9
Triangle Wave
Triangle wave
Harmonic amplitude 1/n2
Sampling data
Harmonics may add in
and distort the result
Aliases at sample rate add
image terms
10
Sampling
Whether its ADCs or
filters, when we think
of analog user
modules we think of
signals and sampling
1
0.5
V(t)
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
-0.5
-1
t
11
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
Sampling
Sampling the signal
Quantize the Signal
Amplitude
1
0.5
V(t)
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
40
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4 8
4
9
5
0
5
1
5
2
5
3
5
-0.5
-1
Definitions:
t
Range := The allowable input voltage.
Resolution := Range/ Number of Quantization Steps
For a “n” bit Converter:
Number of Quantization Steps := 2n
Resolution also known as “LSB” or “∆”
12
4
5
5
56
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6 4
6
5
Sampling
Sampling the signal
1
Quantize the Signal
Amplitude
0.5
V(n)
Quantize the Time Domain
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
-0.5
-1
n
Definitions:
Sample Rate “fs”
Expressed as samples per second “sps”. Not Hz!
13
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
Time Domain Quantization
Nyquist in a Nutshell
The Output Signal Frequencies
all map in the range of :
0 ≤ f out ≤
fs
2
This upper bound is know as the
Nyquist limit.
Any input frequencies meeting
this requirement are accurately
reproduced.
f out = f in ,
14
(0 ≤ f
in
≤
fs
2
)
3KHz Signal Sampled at 10ksps
Time Domain Quantization
Nyquist in a Nutshell
Input frequencies greater than
the Nyquist limit result in output
frequencies that map (alias)
into the 0 to Nyquist limit range.
f out
⎧αf − f in ,
=⎨ s
⎩ f in − αf s ,
(0 ≤ (αf
(0 ≤ ( f
s
− f in ) ≤
in
− αf ) ≤
fs
2
fs
2
7KHz Signal Sampled at 10ksps
Output mapped to 3kHz
)
)
Given a sample rate of 10ksps,
input signal with frequencies
of 1kHz, 9kHz,11kHz,19kHz.
& 21kHz are all going to map
to an output frequency of
1kHz.
With the whole spectrum mapped into a small bandwidth, a filter is
required to select the desired input frequency. It is referred to
as an “anti alias” filter.
15
Sampled Sine Wave I
Example shown using BPF, but results
are same for LPF or DAC generated
signal
Filtered waveform example is sampled
approx 7 times per cycle
PSoC filter adds 0.025% distortion (-72
dB) at 2nd harmonic
Sampling process adds first alias at fsamplefsignal = -16 dB
Sampling process adds other images
Sampling image
2nd Harmonic
16
Sampled Sine Wave II
Filtered waveform is sampled approx 17
times per cycle
Harmonic distortion same as waveform
with Over-Sample Ratio (OSR) = 7
First alias reduced by 9 dB
Subsequent aliases are smaller
Alias images occur as sin(x)/x
Increased OSR moves sin(x)/x
function closer to null and lowers
image level -- (simple algebra)
Sampling alias
2nd harmonic
17
Reconstruction
For output waveform, add R-C filter
(simple physics)
Set R-C corner at half of sample
frequency
Reduces first alias image by 10 dB
(factor of 3)
Reduces subsequent alias images
even more
Technique applies to either filter or DAC
Not necessary when signal is being
digitized for internal use
Sampling alias
2nd Harmonic
18
PSoC Design Fundamentals
What is THE essential element of PSoC analog design?
•
•
•
•
Power Consumption?
Accuracy?
Frequency Response?
Signal to Noise Ratio?
wrong
Topology
Hook it up first.
Then worry about how well it works
19
Analog Block Organization
4 Continuous Time (CT) Blocks
8 Switched-Cap (SC) Blocks
Programmable I/O
4 input mux per column
1 of 8 mux in two columns
Selectable clocks
Clock mux per column
Digital block or system clock source
Buffered out each column
Comparator bus each column
Selectable references
20
CBus0
CBus1
CBus2
CBus3
Analog
CT
Analog
CT
Analog
CT
Analog
CT
Analog
SC C
Analog
SC D
Analog
SC C
Analog
SC D
Analog
SC D
Analog
SC C
Analog
SC D
Analog
SC C
ABuf0
ABuf1
ABuf2
ABuf3
Building Blocks:
Analog User Modules
Programmable controls are SRAM register based
CT: 4 registers per block
SC: 4 registers per block
Functionality controlled by SRAM-based registers
Rapidly updated via software
Turn slow PGA into fast comparator in less than 1 microsecond
Allows for Dynamic Reconfiguration
Multiple configurations supported in design tool
Multiple blocks combine to form complex functions
Amplifiers
Multiple byte DACs
Filters
ADC (with timer and counter)
21
Continuous Time Analog
22
CBUS
VDD
ABUS
OUT
RESISTOR
MATRIX
CT Block configured from opamp, resistors and switch
array
DC open loop gain > 80 dB
Op-amp Unity GBW > 9 MHz
Op-amp slew rate to 8 V/us
Resistor matching < 0.5%
References
PGA Topology
Basic Gain Equation
VOUT
R
= 1+ B
VIN
RA
VIN
VOUT
but, Ground isn't necessarily Zero
RB
PGA ref selectable (Choose in globals – Ref Mux)
AGND
VSS (real Zero)
⎛ Rb ⎞
⎟⎟ + VGND
VO = (VIN − VGND ) ⋅ ⎜⎜1 +
⎝ Ra ⎠
23
RA
GNDRef
PGA Gain Range
VIN
VIN
VOUT
VOUT
RB
RB
Gain referenced to Vss
Used for
RA
Low-side current measurements
Ground referenced signals
AC signals
AGND (2.6V)
6
5
5
4
4
V(out)
V(out)
3
3
2
G=8
G=2
1
1
0
0
0
1
2
V(in)
3
4
RA
Vss (0.0V)
6
2
24
Gain referenced to AGND
Used for
5
G=8
G=2
0
1
2
V(in)
3
4
5
PGA Bandwidth
PGA bandwidth determined by
VIN
VOUT
Op-amp open loop gain
Shunt feedback cap (CF = 1 pF)
and feedback resistor
RB
CF
RA
AGND
35
PGA Freq Response, Pow er=High, Bias=High
G=48
G=24
G=16
G=8
G=4
G=2
30
25
Gain (dB)
20
15
10
5
0
-5
1 Freq (kHz) 10
25
100
1000
10000
INSAMP (2 op-amp)
Differential gain
+ IN
Out
VOUT
⎛ Rb ⎞
= (VIN + − VIN − )⎜⎜1 + ⎟⎟ + VREF
⎝ Ra ⎠
- IN
Abus
Out
Ra
Rb
AGND
A_Bus
Vss
High input impedance
Rb
SC Blk
Ra
Reference
Vin Range: Vcc=5V, AGND=2*Vbg
5
Common mode rejection >
59 dB
4
Max Vin
3
Agnd
Min Vin
2
1
26
16.00
8.00
Gain
5.33
4.00
3.20
2.67
2.29
2.00
0
INSAMP (3 op-amp)
+ IN
Input stage has
High differential gain
Unity common mode gain
⎛ R ⎞C
VOUT = (VIN + − VIN − )⎜⎜1 + b ⎟⎟ a + VAGND
⎝ Ra ⎠ C f
Slightly Improved CMRR
Wider input range
AnalogOut
AGnd
- IN
Vcm=
2.5
3.0
3.5
4.0
4.5
10
Vdiff in max
Improved performance
over INSAMP(2 opamp)
Switches
omitted for
clarity
ASIGN
1
0.1
27
48.00
24.00
16.00
Gain
8.00
4.00
3.20
2.00
0.01
1.00
Synchronize with ADC
Comparators
Vin
Programmable threshold
Vcc
Ref to Vss for P/S current sense
CompBus
Zero crossing
Vin
FSK and doppler processing
CompBus
AGND
Programmable hysteresis
Vin
Noise rejection
CompBus
AGND
Vref
28
Switched Cap Technology
Resistor is replaced
φ1
1
R=
fSC
29
φ2
Switched Cap Tutorial
The switched cap block
has two discrete phases of
operation:
φ1
φ2
Acquisition of signals
φ1
Cf
V os
Transfer of charge
φ1
V in
φ2
30
φ2
Ci
φ1
Vout
Switched Cap Tutorial
During Phi 1, switches are
closed to:
Place Vin on one side of Ci
Short the output to the
negative input and place Vos
on Ci and Cf
Cf
Vin
φ1
Short the output side of Cf to
ground
31
0
φ1
V in
φ2
φ2
V os
Ci
φ1
Vout
Switched Cap Tutorial
Between Phase 1 and Phase 2
All switches are open.
This stores
Vin - Vos on Ci
and
-Vos on Cf
Cf
Vin
φ1
V in
φ2
32
0
φ1
φ2
V os
Ci
φ1
V out
Switched Cap Tutorial
Phase 2 Transfer of Charge
With φ2 open, the input to
Ci was at Vin
When φ2 is shorted, charge
equal to Ci*Vin is pulled
out of Ci
The output must supply an
equal amount of charge
to Cf, so:
Vout = (1/Cf)* Ci * Vin
Vout/Vin = Ci/Cf
33
φ1
Cf
φ2
V os
φ1
V in
φ2
Ci
φ1
Vout
Switched Cap PSoC Block C
Programmable op-amp
Supports ∆−Σ and
Incremental ADC
Supports differential amp
Configurable as input half
of biquad filter
φ1*AZ
CC
0-31 C
CC
Inputs
A.IN
REF Inputs
φ1
CA
0-31 C
SN
φ 2+AZ
OS*φ2B
φ2
A.SIGN
A.REF
φ2
OBUS
φ1*!AZ
CS
CB
0-31 C
CBUS
PWR
CB Inputs
B.IN
(φ2+!AZ)*F.IN1
φ1*F.IN0
C.IN
CA Inputs
34
CF
16-32 C
φ1
Switched Cap PSoC Block D
Programmable op-amp
Supports ∆−Σ and
Incremental ADC
Configurable as output half
of biquad filter
CC
0-31 C
CARR
φ1*AZ
A.IN
CA Inputs
REF Inputs
φ1
CA
0-31 C
φ2+!B.SW
CF
16-32 C
CB
0-31 C
φ2+!B.SW
CB Inputs
B.IN
(φ2+!AZ)*F.IN1
φ1*F.IN0
φ1*!AZ
φ2
A.SIGN
A.REF
φ 2+AZ
OS*φ2B
φ1*B.SW
OBUS
φ 1*B.SW
CS
CBUS
PWR
35
Switched Cap DAC
φ1
VOUT = VAGND + / − VREF
CA
CF
Output is NOT rail to rail
DAC6 example
CF φ2
φ1
VREF
VAGND +/- VREF=VBG +/- VBG
VOUT(MAX)
= VBG + VBG*31/32
= 2.559V
VOUT(MIN)
= VBG - VBG*31/32
= 0.041V
CA
φ2
φ2
Analog column output buffer will further
limit output swing, see AN2089
36
VOUT
SCBlock as Comparator
Two Cap Comparator
With feedback capacitor CF
removed Vout goes to either
the high or low rail.
Vout goes high when
VinACA > VinBCB
Vout goes low when
VinACA < VinBCB
VinB is the inverting input input.
37
φ2
CB
φ1
φ1
CA
VinB
VinA
φ2
φ1
Vout
PSoC ADCs
The PSoC offers flexible resources allowing the
construction of several types of ADCs.
Each project’s unique System Requirements:
Resolution
Bandwidth
Hardware Utilization (digital blocks)
CPU loading
Interrupt loading
Determine which ADC (or ADCs) makes for the
best fit.
38
Choices, choices, choices
Trade-offs
Resolution
Sample Rate
% CPU Usage
Start Latency
Block Count
Power
Interrupt Latency
Gain Errors
Linearity (INL, DNL)
Noise
RAM Consumption
FLASH Consumption
39
Realistic ADC Types
Three types of PSoC ADCs
SAR (Successive Approximation Register)
Minimum block count
Subject to aliasing errors
Incremental
Integrates noise, slow
Enables multiple instances (Dual, Triple)
Delta Sigma
Integrates noise
Fast, continuous sampling
Uses decimator, "There can be only one . . ."
40
SAR (Successive Approximation Register)
Single Comparator & DAC
DAC resolution determines ADC
resolution
Logic determines how quickly DAC
zeros-in on input value
Binary search allows “n” bit DAC to
reach to best value in “n”
attempts
The “Successive Approximation
Register” (SAR) is a binary
search algorithm
41
Comparator
Vin
VDAC
DAC
logic
Incremental ADC
Constructed from:
SCBlock Analog Modulator
Timer to set the number of
integration cycles
Counter to accumulate the number
Vin
of comparator high cycles
A 12 bit ADC needs
12 bit counter
12 bit timer
÷4 Clock generator
SCBlock
Ref+
Ref-
42
φ1
CA
φ2
φ1*Reset
φ2
Enable
Int
To CPU
Counter8
÷4
φ1,φ2
generator
Uses decimator instead of counter,
only one at a time
Variable resolution
Dual and triple available
CF
Data
Bus
ADCINC
ADCINCVR
φ1
φ1
φ2
Int
Timer8
DataClock
To CPU
Incremental ADC
ADCINC (12 bit)
Not a 12 bit converter.
Average of 4096 single bit
conversions .
Nyquist limit determined by the
sampling frequency
(Remember fs =fdataclock/4).
Output Rate
fADCout= fdataclock /16640
-20
Sample Rate
-40
dB
-60
-80
409600
204800
102400
51200
25600
12800
6400
3200
1600
Frequency (Hz)
800
400
200
100
43
Nyquist
Limit
Output Rate
50
Aliasing not a problem until near
Nyquist rate
-3dB bandwidth = .44*Output Rate
-3 dB freq.
25
Nyquist Frequency
fNyquist= fdataclock /8
DataClock =4*409600sps (100sps SampleRate)
0
Delta Sigma ADC
Constructed from:
SCBlock analog modulator
Single digital block
On-chip decimator replaces
counter in Incremental
SCBlock
φ1
CF
Vin
Ref+
Ref-
φ1
CA
φ2
φ1*Reset
φ2
Data
Decimator Data
Bus
Pipelined ADC
Output rate reduced for
multiplexed inputs
One decimator = one Delta
Sigma ADC per system
44
Decimator Latch
÷4
φ1,φ2
generator
φ1
φ2
Out
Timer8
DataClock
Int
Delta Sigma 2nd Order Modulator
Equivalent to a 2 pole filter
Lower noise
Higher allowed clock rate
Faster conversion
Reset
φ2
φ1
Vin
φ2
Ref+ Ref-
45
φ1
Reset
φ2
φ1
φ2
Ref+ Ref-
φ1
Cmp
∼φ 2
ADC Summary 26xxx, 24/27/29xxx
Sample Rate vs Resolution, clock = 8.0 MHz
INC_2, DS_2 (double
modulator) not in
25/26xxx
INC_2 6,7,8 bit at
12 MHz clock (in
Max SPS
100000
10000
addition to 8MHz)
1000
INC_1
INC_2
DS_1
DS_2
SAR
29x only
100
5
46
6
7
8
9
10
11
Resolution
12
13
14
15
ADC Summary 26xxx, 24/27/29xxx
Max CPU Load (%) vs Resolution, FCPU=24 MHz
%
100
Logically, longer sample
times and fixed size
data handling code
mean lower % CPU
usage
SAR stalls CPU
10
INC_2 6,7,8 bit at 12
MHz clock
INC_1
INC_2
DS_1
DS_2
SA R
29x only
29xxx decimator saves
a lot of CPU overhead
1
5
47
6
7
8
9
10
11
Resolution
12
13
14
15
Start Latency
Delta Sigma converters are pipelined
Data is smeared from adjacent samples by
decimator
First two samples after start are in error
Cuts multiplex rate by factor of 3
ADCINC also uses Decimator, but
Reset at start of conversion eliminates
smearing and start latency
Decimator serves counter function, saves a
block
48
Block Count/Power
Analog and digital block usage listed in User Module
data sheets
ADCINC uses decimator
Saves digital block compared to ADCINCVR
Not available as dual or triple
ADCINCVR has adjustable rate, but more blocks
Most of power consumption in analog blocks
Double modulator ADCs consume double power,
reasonable price to pay for:
Higher speed
Lower noise
49
ADC Noise
Quantization noise = 0.288*Range/resolution
What's a half bit? . . . . A little higher noise
DelSig decimate by 64 listed as 7.5 bits
Output is 8 bits with higher noise on LSB
DelSig decimate by 256 listed as 10.5 bits
Output is 11 bits with higher noise on LSB
Double modulator ADCs
Lower noise than single modulator types
Higher non-linearity at ends of scale
50
Selection Process
1. Select chip (25/26xxx or 24,27,29xxx)
Prefer 24/27/29xxx for MUCH lower noise
2. Select resolution
3. Select sample rate
4. Choose: continuous data or triggered data
Continuous data: DelSig
Triggered data: ADCINC
Slow signal, low resolution: SAR6
5. Verify CPU load and interrupt structure
6. Verify block availability
51
ADC Performance
PSoC ADCs are well characterized
Non-linearities generally lower than quantization noise when
operated at specified clock rates
ADC Acquistion Rates
Consistent with signal processing bandwidth of PSoC
Exact rates (e.g., 1.000 ksps)
Achievable with ADCINCVRs by changing calculation time
ADCINC not adjustable with internal clock
DelSig ADCs with non-integer divider clock rates
Achievable by changing PWM
Causes slight gain error (seeAN2095 on u-Law example)
52
Clock Considerations
User Modules with both analog and digital
blocks (ADCs and DACs) require same
clock to all blocks.
Clock signal is divided by 4 in the mux to set
sample rate
User Module datasheets’ “Parameters”
section lists equations and explanations to
help guide clock settings
53
Clock Limitations
54
User Module
Column Clock
DAC8, DAC9, MDAC8
≤ 500 kHz
DAC6, MDAC6
≤ 1 MHz
Switch-Cap Comparators
≤ 2 MHz
Filters
≤ 6 MHz
Delta Sigma ADCs
≤ 8 MHz
Incremental ADCs
≤ 8 MHz
DAC Clock Considerations
DAC User Module Datasheets specify that the Column
Clock is 4 times the output update rate.
DAC8, DAC9, and MDAC8
Max output update rate = 125 ksps
DAC6 and MDAC6
Max output update rate = 250 ksps
55
Clock Considerations
Delta Sigma ADCs ≤ 8.0 MHz
Linearity is improved for ADC clock ≤ 2.0 MHz
DELSIG8 DataClock = SampleRate × 256
DELSIG11 DataClock = SampleRate × 1024
DELSIG8 Example
Max Sample Rate = 31.25 ksps
31,250 × 256 = 8 MHz
DELSIG11 Example
Max Sample Rate = 7.8 ksps
7,800 × 1024 ≈ 8 MHz
56
Clock Considerations
Incremental ADCs ≤ 8 MHz
Governing Equations:*
ADCINC12 DataClock = SampleRate × 65 × 256
ADCINC14 and ADCINCVR DataClock specified as ≤
8 MHz in User Module Data Sheets
ADCINC12 Example
Max Sample Rate = 480 sps
480 × 65 × 256 ≈ 8 MHz
* See User Module Data Sheets
57
Reference Structure
PSoC is Single Supply, so ...
Establish Artificial Ground
(called "Analog Ground") at mid-supply
Establish Reference used for ADC, DAC
VBandGap = 1.300 +/- 0.02 V
Selectable ground and reference
VBandGap for absolute voltage systems
Vdd/2 for supply ratiometric systems
External VREF for increased flexibility
58
Ground + Reference Values
Precision Base Reference
VBandGap Tolerance
1.5% worst case over temp
Excellent P/S rejection
Vcc =
5.00V
Reference Offsets
< 50 mV
Sets system accuracy
Vcc =
3.30V
References for "Real Signals"
Scale 0.0 to 4.0V
Agnd= 2.0V
Ref=+/-2.0V
Scale 0.0 to 2.6V
Agnd=VBG (1.3V)
Ref=+/-VBG (1.3V)
59
Vcc/2
+/VBG
Vcc/2
+/Vcc/2
Vcc/2
+/P2.6
VBG
+/VBG
P2.4
+/P2.6
2*VBG
+/VBG
Vcc/2
+/Vcc/2
1.6*VBG
+/1.6*VBG
Reference / Ground Structure
There is no massive ground plane as in a normal good board design
Distributed ground to eliminate crosstalk
Requires careful system and power design
Ground buffer offset adds to error budget
Vdd
Vdd/2
RefHI to
Analog
Blocks
X1
X1.6
X2
2*Vbandgap
P2[4]
AGND
P2[4] (External Cap)
Vbandgap
RefLO to
Analog
Blocks
X1
P2[6]
Vss
60
Analog Ground Bypass
External cap connection
Vcc
VBG
Bypass internal distributed
ground
Reduces noise to ground buffers
in analog blocks
RefHI
P2.6
RefLO
Vss
Distributed
Ground
Vcc/2
AGND
P2.4
40k
Analog block ground buffer noise
remains
Application
X12
Ground Buffer in
each Analog Block
2k
VNAGND
P2.4
i/o
dBV/rtHz
10000
Ext
1 uF
0
0.01
0.1
1.0
10
Audio to ultrasonic
signal processing
1000
100
0.001
61
0.01
0.1 Freq (kHz)
1
10
100
Filters: Application Examples
Transmit Generation
FSK Generation per AN2095
Coin Detector: 1-10 kHz swept BPF
Receive Processing
IR: 38 kHz BPF
Video Sync Detector: 15 kHz BPF
Fish Finder: 180 kHz BPF, 20 kHz LPF
Phone Modem: 1.8-2.2 kHz BPF4
Power Line Modem: 133 kHz BPF4, 12 kHz BPF2, 3 kHz LPF
U/S Motion Detector: 40 kHz BPF, 10 kHz LPF
Coin Detector: Synchronous with transmit
62
Filters: Design Possibilities
Currently available User Modules:
Low Pass 2 pole
Band Pass 1 pole-pair
Others in work include:
Low Pass 4 pole
Band Pass 2 pole-pair
Elliptical
Notch
High Pass
Select filter design to meet attenuation requirements
Balance design goals with side effects
In-band amplitude and phase performance
Out-of-band amplitude and phase performance
Pulse rise time and overshoot characteristic changes
Sampling alias/images
63
Continuous Time Filters
PSoC’s Analog System consists of both Switch Cap and Continuous
Time Blocks. There are filter options for both sets of blocks
Continuous Time Filters:
Implement standard Sallen + Key topology
Programmable gain stage simplifies design
Design methodology well known
Requires 4 external passive components
HPF and LPF design spreadsheets in app notes
Especially useful for anti-aliasing filters
64
Continuous Time
Low Pass Filters
Use PGA as fixed gain block with
passive R + C
Design equations VERY standard
Every analog IC company has
a filter design program
C4
R1
R2
Vin
Vout
+K
C3
C4
Primary use:
Anti-alias filters
Remember aliases in signal
description?
Aliases also occur in ADC,
adding to noise bandwidth -so it's important to suppress
out-of-band noise
65
Vin
R1
R2
Vout
C3
Continuous Time
High Pass Filters
Preferred over switched-cap high pass filter
Wider upper frequency limit
No errors due to low sampling
Consider switched-cap BPF
R4
C1
C2
Vin
Vout
+K
R3
R4
Filter shape is adjustable
Uses additional PGA UM
Additional Resources
AN2030 - Adjustable Sallen and Key High-Pass
Filters
AN2031 - Adjustable Sallen and Key Low-Pass
Filters
AN2099 - Single-Pole IIR Filters
66
C1
Vin
C2
Vout
R3
AGND
Switched Capacitor Filters
Standard Topologies
Low Pass, Band Pass, Notch, High Pass
RC Biquad maps to Switched Capacitor Blocks
R2
C2
C4
CA
Vin R
1
φ2
C4
1
1
φ1
CB
CA
R3
Vout
Vin
φ2
φ1
φ2
C1
φ1
CB
φ1
φ2
Scalable, Programmable, Connectable
67
C3
φ2
φ1
φ2
Vout
Filter Placement
LPF2
BPF2
Input on A Block
Output on B Block
C2
φ1
Input on A Block
Output on A Block
Comparator to Bus
C2
φ2
φ1
φ2
C4
CB
C4
CA
CA
Vin
φ2
φ1
φ2
C1
φ1
CB
φ1
φ2
C3
φ2
φ1
Vin
φ2
Vout
φ2
φ1
φ2
φ2
C1
φ2
φ1
C3
φ1
φ1
Vout
AnalogBus
CompBus
68
Filter Placement
Input on A-cap
Input on B-cap
ACA
01
ACA
02
ACA
03
ASA
10
ASB
11
ASA
12
ASB
13
ASB
20
ASA
21
ASB
22
ASA
23
No modulator
Inputs through Mux or direct on P2.x
ABUS(3)
P2.1
ACA
00
ABUS(1)
Allows use of modulator
Enables elliptical or notch filter (UM
delivered later)
P2.2
BPF placements similar
Eliptical and Notch horizontal only
69
ACA
01
ACA
02
ACA
03
ASA
10
ASB
11
ASA
12
ASB
13
ASB
20
ASA
21
ASB
22
ASA
23
ABUS(3)
P2.1
ACA
00
ABUS(1)
Output on same block as input
Chainable to BPF or LPF
P2.2
Low Pass Filter
Programmable -3 dB point
and d
300 Hz to 150 kHz
Scaled to clock
C2
φ1 φ 2
C4
CA
Vin
φ2
φ1
70
φ2
C1
φ1
CB
φ1
φ2
C3
φ2
φ1
φ2
Vout
Vout
=
Vin
⎛ ⎛ s ⎞2 ⎞ 2
⎜1 − ⎜
⎟ ⎟f
⎜ ⎜⎝ 2 f S ⎟⎠ ⎟ S
C1 ⎝
⎠
−
C 2 ⎛ C AC B 1 1 C 4
⎜⎜
− −
⎝ C 2 C3 4 2 C 2
s2 +
sf S
C4
C 2 ⎛ C AC B 1 1 C 4
⎜⎜
− −
⎝ C 2C3 4 2 C 2
⎞
⎟⎟
⎠
+
⎞
⎟⎟
⎠
fS
2
⎛ C AC B 1 1 C 4
⎜⎜
− −
⎝ C 2 C3 4 2 C 2
⎞
⎟⎟
⎠
Band Pass Filter
Programmable Q and fc
300 Hz to 150 kHz
Scaled to clock
Zero-crossing output for
energy detector
applications
C2
φ 1 φ2
Vout
=
Vin
C4
CB
CA
Vin
φ2
φ1
φ2
φ2
C1
φ2
φ1
C3
φ1
φ1
Vout
AnalogBus
CompBus
71
⎛
s ⎞
⎟⎟ f S
s⎜⎜1 +
2
f
C1 C B
S ⎠
⎝
−
C 2 C3 ⎛ C A C B 1 1 C 4 ⎞
⎟⎟
⎜⎜
− −
⎝ C 2 C3 4 2 C 2 ⎠
2
s2 +
C4
sf S
fS
+
C 2 ⎛ C AC B 1 1 C 4 ⎞ ⎛ C AC B 1 1 C 4 ⎞
⎟⎟
⎟⎟ ⎜⎜
⎜⎜
− −
− −
C
C
4
2
C
C
C
4
2
C
2 ⎠
2 ⎠
⎝ 2 3
⎝ 2 3
Elliptical Low Pass Filter
Notch can be tuned above or below
low pass corner
Vout
=
Vin
Ratio of fzero to f-3dB limits above
attenuation above fzero
Can be combined with additional
sections
C2
φ1 φ 2
C4
CA
Vin
φ2
φ1
φ1
CPP
72
φ2
C1
CB
φ1
φ2
C3
φ2
φ1
φ2
Vout
⎛ ⎛ s ⎞2 ⎛ C C
1 ⎞ ⎞⎟ 2
PP A
⎜1 + ⎜
⎟
⎜
⎟ fS
−
⎟ ⎜
⎜ ⎜
4 ⎟⎠ ⎟
C1 ⎝ ⎝ 2 f S ⎠ ⎝ C1C 3
⎠
−
C2
⎛ C AC B 1 1 C4 ⎞
⎜⎜
⎟⎟
− −
⎝ C 2 C3 4 2 C 2 ⎠
2
s2 +
sf S
fS
C4
+
C2 ⎛ C AC B 1 1 C4 ⎞ ⎛ C AC B 1 1 C4 ⎞
⎜⎜
⎟⎟ ⎜⎜
⎟⎟
− −
− −
⎝ C 2 C3 4 2 C 2 ⎠ ⎝ C 2 C3 4 2 C 2 ⎠
Notch Filter
Special case of elliptical
low pass where:
ωzero = ωpole
Band pass gain of Q in first
stage limits maximum
signal
C2
φ1 φ 2
C4
CA
Vin
φ2
φ1
φ1
CPP
73
φ2
C1
CB
φ1
φ2
C3
φ2
φ1
φ2
Vout
Vout
=
Vin
⎛ ⎛ s ⎞2 ⎛ C C
1 ⎞ ⎞⎟ 2
PP A
⎜1 + ⎜
⎟
⎜
⎟ fS
−
⎟ ⎜
⎜ ⎜
4 ⎟⎠ ⎟
C1 ⎝ ⎝ 2 f S ⎠ ⎝ C1C 3
⎠
−
C2
⎛ C AC B 1 1 C4 ⎞
⎜⎜
⎟⎟
− −
⎝ C 2 C3 4 2 C 2 ⎠
2
s2 +
sf S
fS
C4
+
C2 ⎛ C AC B 1 1 C4 ⎞ ⎛ C AC B 1 1 C4 ⎞
⎜⎜
⎟⎟ ⎜⎜
⎟⎟
− −
− −
⎝ C 2 C3 4 2 C 2 ⎠ ⎝ C 2 C3 4 2 C 2 ⎠
Multi-Section Filters
Two poles per block pair
Up to 8 poles using all switched-cap, but leaves
nothing left for ADC or DAC
Can be combined with CT-based Sallen + Key
74
Design Methods
Filter Wizards included in PSoC Designer
Right click on a filter (once placed) to access the filter wizard
Available as LPF, BPF 2 and 4 pole versions .xls in
Cypress MicroSystems/PSoC Designer/Documentation/Filter Design
75
Filter Sampling Effects - Warping
Sample rate causes a phase delay, lowers filter corner frequency
Corrected by biasing filter higher by 2*fS/fC*tan-1(πfC/fS)
Over-sample ratios >20 add very little error
Compensation built into design .xls and wizards
1.25
1.20
1.15
1.10
1.05
1.00
1
76
10
100
Filter Sampling Effects - Peaking
Complex zeros (in numerator of transfer function) peak the
response and limit the asymptotic attenuation
Compensation built into design .xls and wizards
s2 +
sf S
C4
C 2 ⎛ C AC B 1 1 C 4
⎜⎜
− −
⎝ C 2 C3 4 2 C 2
⎞
⎟⎟
⎠
+
20
Peak, OSR=10
⎞
⎟⎟
⎠
Peak,
OSR=35
Peak, OSR=70
Peak, OSR=140
0
fS
2
⎛ C AC B 1 1 C 4
⎜⎜
− −
⎝ C 2 C3 4 2 C 2
Net, OSR=10
-20
⎞
⎟⎟
⎠
dB
Vout
=
Vin
⎛ ⎛ s ⎞2 ⎞ 2
⎜1 − ⎜
⎟ ⎟f
⎜ ⎜⎝ 2 f S ⎟⎠ ⎟ S
C1 ⎝
⎠
−
C 2 ⎛ C AC B 1 1 C 4
⎜⎜
− −
⎝ C 2 C3 4 2 C 2
Net, OSR=35
-40
Net, OSR=70
-60
Net, OSR=140
Nom inal
-80
100
77
1000
10000
Freq (Hz)
100000
1000000
Switched Capacitor Block
Functions: Examples
Gain Invert Block
φ1
Equivalent to MDAC
CF φ2
Invert Signal Polarity
When CA=CF then gain is -1
Both samples and outputs on
φ2.
Can be strung together
Functions as a bus to route a
signal from one side of the
analog columns to the other.
System Gain Inversion
78
φ2
Vin
CA
φ1
φ1
Vout
SCBlock Amplifier Examples
Bi-Directional Current Source•
Vset
DAC6
DiffAmp configured with gain of one.
CF=CB=CA=16
Sign = Pos
External Resistor and DAC value sets
current.
Independent of load.
Vout = Vload − Vset
Vout − Vload
Vset
i=
=−
Rset
Rset
79
DiffAmp
Vload
-B
P2.1
x1
+A
Buf0
P0.3
Rset
i = -Vset / Rset
Rload
Vout
SCBlock as Integrator
SCBlock Integrator
Uses standard gain stage with the
exception that the switch to
discharge CF has been disabled.
So:
Vout = Voutold
CA
+ Vin
CF
Vout ⎛ C A ⎞ 1
⎟⎟ ⋅
= ⎜⎜ f s
Vin ⎝ C F ⎠ s
80
φ1
CF φ2
φ1
Vin
CA
φ2
s = 2πf − 1
Vout
SCBlock as Integrator
SC Integrator
φ1
(Doing an Op Amp’s Job)
Negative Gain Integrator closely
resembles a positive input grounded
φ2
open loop op amp.
Vin
φ1
CF φ2
CA
Vout
⎛ Vout ⎞
⎛ CA ⎞ 1
⎜⎜
⎟⎟
⎟⎟
= −⎜⎜ f s
⎝ CF ⎠ s
⎝ Vin ⎠ SCInt
⎛ Vout ⎞
1
⎜⎜
⎟⎟
≈ −(2πGBW )
s
⎝ Vin ⎠Opamp
81
Vin
Vout
SCBlock Integrator - Faux Op Amp
SC Integrator
Rf
Faux Opamp
This circuit is an inverting amplifier
and single pole low pass filter.
Its gain is determined with external
resistors.
The bandwidth is determined with
Switched Capacitor Values.
φ1
Rin
Vin
External Resisters
Sample Frequency
⎛ Vout ⎞
⎛ Rf ⎞
1
⎜⎜
⎟⎟
⎟⎟
= −⎜⎜
⎝ Vin ⎠ SCInt
⎝ Rin ⎠ 1 + s C A ⎛⎜1 + R f ⎞⎟
f s C F ⎜⎝ Rin ⎟⎠
82
CF φ 2
φ2
Vin
CA
φ1
buf
Vout
SCBlock - Opamp
Vin
Rin
100k
Rf
100k
Vout
CT Op Amp can be unstable in this mode
83
SCBlock - Peak Detector
Dual Input SC Integrator
Feedback through diode and
capacitor makes a Peak
Detector.
φ1
CF φ2
φ1
Vin
φ2
5
Vout
4
CA
Vpk
φ2
Volts
CB
3
Vin
φ1
2
1
0
84
Vpk
Cext
Reset
using
GPIO
buf
Vout
SCBlock - High Current Source
Dual Input SC Integrator
•
Or a Single Block
Programmable High Power
Current Source.
φ1
CF φ2
V
φ1
CA
RefHi
I load
85
C
Asign Ref High A + AGND
31
=
Rset
iload
buf
φ2
Vout
φ2
CB
φ1
Rset
SC Modulator
Modulator multiplies by a series +1…-1…+1…-1…
Toggles Sign bit in A-cap input under logic control
sin( n 2πf mod t )
v(t ) = ∑
n
n = odd
Generates sum and difference frequencies
PLUS
Sum and difference from multiples of modulator frequency
86
SCBlock Analog Modulator
φ1
Analog Modulator
CF
ASC10, 12, 21, 23
Vin
Digital Connections
Low (no modulation)
GOE[1]
GOE[0]
Row 0 Broadcast Row
Analog Column Comparator 0,1,2,3
Enables connection from BPF zerocrossing out to BPF or LPF modulator
input for frequency shift or energy
detector
CA
φ1
φ2
φ1
Vout
φ2
ASign
AMod
low (no modulation)
GOE[1]
GOE[2]
Row 0 Broadcast Bus
Analog Column Comparator 0
Analog Column Comparator 1
Analog Column Comparator 2
Analog Column Comparator 3
CBus0
ACB00
P2.3
B
CBus1
ACB01
CBus2
ACB02
ASC10
ASC12
ASD11
CBus3
ACB03
A
ASD13
A
A
P2.2
P2.1
A
ASD20
A
ASD22
ASC21
A
B
ASC23
P2.0
ABuf0
87
ABuf1
ABuf2
ABuf3
SCBlock Analog Modulator
Heterodyne
Heterodyne
Mixing of two or more signals to
produce a different frequency.
Vin
Analog modulator heterodyne is built
around the property that multiplying two
sinusoids produces:
Output sinusoid with a frequency equal to
the difference of the two input
frequencies.
Output sinusoid with a frequency equal to
the sum of the two input frequencies.
Low pass filter removes sum frequency
Low
Pass
Filter
Vout
(Modulator)
PWM
Ref
GlobalOut0
10kHz
sin( f a ) ⋅ sin( f b )
=
cos( f a − f b ) cos( f a + f b )
−
2
2
Removed with
low pass filter
88
SCBlock Analog Modulator
Heterodyne
Heterodyne Example
10kHz reference frequency is input
to the modulator bit of the low
pass filter.
PSoC
Cin
Vin
Buffer1
P0.7
0.1µF
FColumnClock ≤ 6 MHz
89
Buf1
P0.5
(Modulator)
Rin
PWM
Ref
10K
11 kHz Input Signal is converted to
a 1kHz Output Signal.
Low
Pass
Filter
P0.3
Buf0
AGND
GlobalOut0
10kHz
Vout
SCBlock Analog Modulator
Full Wave Detector
PreAmp
Comparator
Gain Stage (Full Wave Detector)
Signal Flow
Signal comes into Preamp
Goes to Gain Stage and
Comparator
Comparator Output used to
control Gain Stage
modulator bit
Example:
4 cycle 20 kHz burst
90
SCBlock Analog Modulator
Amplitude Demodulator
Comparator
PreAmp
Low Pass Filter (AM Demodulator)
Signal Flow
Signal comes into Preamp
Goes to Low Pass Filter and
Comparator
Column Comparator 1 is used to
control Low Pass Filter
modulator bit
Example:
10 cycle 50 kHz burst
91
Modulator: Analog or Digital
Analog modulator
Implements function in SC block
Digital modulator
XOR is equivalent
Examine typical system design with modulator
for non-amplitude based signals
92
Digital Modulator
FSK Detector
FSK Examples
HART Modem, Bell202 (Caller ID)
0 = 1200 Hz, 1 = 2200 Hz
Power Line Modem
0 = 131.850 kHz, 1 = 133.050 kHz
v(t ) = VP sin(2π ( f L + data( f H − f L ))t )
Correlator
-cos(2πfd)
sin(2πft)
Multiplies signal by delayed replica
Integer cycle delay = positive output Delay Clock
Integer + 1/2 cycle delay = negative
Implemented in Modulator in LPF or in
XOR (in row LUT) followed by LPF
TIME DELAY, d
sin(2πf(t+d))
sinfl
sinfl delay
fl corr
filt fl corr
sinfh
sinfh delay
fh corr
filt fh corr
0
93
500
1000
1500
2000
SC Analog Modulator
FSK Detector
FSK In
BPF
Delay
Clock
FSK Out
LPF
24 bit
S/R
Hysteresis
Comparator
Input Dig Data
(1200 Baud
1 bit Lo, 2 bits Hi)
Filter / Comparator
Convert to zero-crossing
Delay Line
FSK Modulated
Implemented with Shift Register from
PRS block
Comparator Out
Modulator Out
Out of Phase
S/R Out
S/R In
`
In Phase
Shift Reg. Out
Delayed Comp.
XOR Output
(Correlator Out)
PRS
Delay
Clock
Low Pass Filter
Bandwidth near baud rate
Comparator finds the data
94
5
Filtered Correlator
6
7
Digital Data Out
Detection Delay = 620 usec
Measuring FSK Performance
An "eye pattern" shows transmission
of repetively sampled random data
1:
2:
3:
4:
Input data
FSK modulated data
Correlator output
Detected digital data
(Horizontal synced to input data)
"Openess" of the eye indicates quality
of received data
Risetime determined by sum of
correlator delay and filter
bandwidth.
Width of line determined by resolution
of correlator delay clock and
sharpness of filter
Finer resolution takes more blocks
Better filter takes more blocks.
95
FSK: Customer Example
PSoC in phone application
Update from Call Waiting/Caller ID app note
98% Customer Design
PSoC (CY8C27443) Replaced
TL494 PWM P/S controller
MT8870 DTMF decoder
80C52 processor
93C46 EEPROM
2 LM324 opamps
Analog filters
TLC555 timer + discretes
Line voltage detect circuit
Enabled Zero Cost Additions
DTMF Dialer
Caller ID
True Sinusoidal Ring Tone
Improved line voltage monitor
Improved audible ringback
Programmable ring voltage
96
Limited Slew Amplifier
Slow Slew (Volts/sec) is Bad for fast
signals!
...but, there are applications for
slow slew amplifiers
A comparator with and external R C
simulates an opamp with
programmable slew.
i=C
V 2
∆Vout
i ≈ cc
R
∆t
∆Vout Vcc 2
≈
∆t
R ⋅C
R & C determine Slew Rate.
97
R
Vout
C
Limited Slew Amplifier Example
Universal AC Motor
Voltage across the Commutator is:
Mains power less the voltage drop across the
field coils.
Inductive switching pulses for brush switching.
Amplitude of pulses is:
Proportional to the voltage across the
commutator.
Frequency of pulse is:
Dependent on rate of switch changes.
Proportional to shaft speed. (RPM)
determined by commutator switching
If Mains power component can be
suppressed, the pulses can easily be
Digitized.
98
Com+
Mains
Com-
Limited Slew Amplifier Example
Slew Rate Limited Pulse Separator
Amplifier allows low frequency
signals (Mains Power) to pass.
Fast Slewing signals
(Commutator Noise) are
blocked, leaving only the
pulses at the output of the Diff
Amp.
Forms an effective phase neutral
high pass filter.
No distortion of Pulses
No Delay
99
Vin
Diff Amp
Vout
Slew Limited
OpAmp
Limited Slew Amplifier Example
PSoC Implementation of Slew
Rate Limited Pulse
Separator
1M
1M
1k
SENSE+
1k
SENSE-
Presently implemented with:
PulseDetect
Compare
6 Analog Blocks
2 Digital Blocks
For Production Implemented with:
27k
5 Analog Blocks
1 Digital Block
.1uF
Remaining Resources:
58% of Analog Blocks
87% of Digital Blocks
100% of CPU
100
AGND
InAmpOutVout
Vout
Limited Slew Amplifier Example
PSoC Implementation of Slew
Rate Limited Pulse
Separator
Scope Traces show that the 60Hz
signal is removed with no visible
distortion of pulses.
Pulses can easily be digitized
(and counted)
Demo’ed to customer!
101
1/f Noise
Noise example
ADCINCVR direct input from quiet source with
long term average subtracted
Scale is in ADC counts (300 µV per bit)
Note slow wander . . . . 1/f
THE dominant type of noise in most measurement systems
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61
60
59
58
102
RAW(SIG-AVG(REF)}
Start with a "nice, clean" signal
Start with a clean signal:
3.0 mV DC
Example: output of pitot tube
Differential pressure
indicator of air speed
0.015
0.010
0.005
0.000
-0.005
Signal
-0.010
Add noise:
10.0 mV 3.0 Hz sine wave
Representative (but much
larger) of the low
frequency noises in the
PSoC
Representative of
environmental noise
0
0.1
0.2
0.3
0.4
0.5
0.6
0.8
0.015
0.010
0.005
0.000
-0.005
Signal
-0.010
0
103
0.7
0.1
0.2
0.3
0.4
0.5
0.6
Signal+Noise
0.7
0.8
Get Rid of Noise by Averaging
Sample at 100 Hz
Take average of some
number of ADC
measurements, but ...
4 sample average does
nearly nothing
0.015
0.010
0.005
0.000
Signal
-0.005
Signal+Noise
Average(4)
-0.010
16 sample average doesn't
help much either
Logically, we must average
much longer than the noise.
Filter for 3 Hz noise will take 1012 seconds -- not useful
0
0.1
0.2
0.3
0.5
0.6
0.7
0.8
0.6
0.7
0.8
0.015
0.010
0.005
0.000
Signal
-0.005
Signal+Noise
Average(16)
-0.010
0
104
0.4
0.1
0.2
0.3
0.4
0.5
Correlated Double Sample
Sample low frequency noise
Short the inputs
Measure INSAMP out Store
VSIGNAL
INSAMP
13 bit ADC
INSAMP
13 bit ADC
Sample noise + signal
Switch inputs to source
Measure INSAMP out
Compute difference
VSIGNAL
Subtract stored noise from noise
+ signal
Compute running average with easily implemented IIR filter
105
Voila
Correlated Double Sampling
Removes common mode low
frequency noise
0.015
IIR filter over 4 samples
80% reduction in noise
0.000
0.010
0.005
Signal
-0.005
Signal+Noise
CDS:IIR(4)
-0.010
0
IIR over 16 samples
95% reduction in noise
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.015
0.010
0.005
0.000
Signal
-0.005
Signal+Noise
CDS:IIR(16)
-0.010
0
106
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
CDS Antidote to 1/f Noise
Apply lessons of Correlated Double Sample (CDS)
Short inputs, measure offset, subtract instantaneous offset from direct
input
Blue trace shows CDS signal
Average more constant, Std Dev (σ) remains the same
RA W(SIG-AVG(REF)}
62
RA W(SIG-REF)
61
60
59
58
Now, add filtering
107
CDS + IIR
Correlated Double Sample (CDS) removed most of 1/f
Infinite Impulse Response (IIR) filter provides running
average
Raw Std Dev
σ = .816 counts
IIR (25%) on Non CDS
σ = .518 counts
IIR (25%) on CDS σ = .224 counts
62
N(avg)=4(SIG-AVG(REF))
N(avg)=4(SIG-REF)
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60
59
58
108
CDS + more IIR
Longer IIR filter provides longer running average
Raw Std Dev
σ = .816 counts
IIR (5%) on Non CDS σ = .465 counts
IIR (5%) on CDS
σ = .085 counts
IIR filters require simple computation, near zero RAM
IIR (like any other filter) reduces data bandwidth
Technique proven in customer applications
App Notes in process
62
N(avg)=20(SIG-AVG(REF))
N(avg)=20(SIG-REF)
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109
System Design Example:
X-10 Receiver
Power line communications for consumer applications
Signal
120 kHz 1 msec pulse at zero crossing
Rides on top of AC line (110 V)
Level = 50 mV to 4 V p-p -- requires AGC
Data encoded in presence/absence of pulse
110
X-10 Receiver Block Diagram
3 kHz LPF takes 120 kHz carrier out of zero x-ing sync
3 kHz HPF takes 50/60 Hz line out of carrier path
Demo shows 120 kHz detection only
Line connections left as exercise for student
Zero x-ing detector and AGC to follow later
3 kHz LPF
Zero X-ing
Detector
COMP
3 kHz HPF
PGA
DATA
120 kHz
Band Pass
Filter
AGC (digital)
Full
Wave
Detector
10 kHz
Low Pass
Filter
Gated
ADC
Zero X-ing Detector and AGC
left as exercise fo the student
111
COMP
PSoC Topology
User modules dropped in
Parameters set from spreadsheet calculations
DigBuf used to route comparator output to port
112
Switched Cap Filter Design
Band Pass Filter
Low Pass Filter
Common Clock with BPF
High OSR is important to reject 2x
carrier in full wave detector
Mod bit built into ASC A-cap
Enter parameters
Adjust C2 to align peak
Tighter bandwidth is possible
4 pole filters are possible, but
consume blocks
Center Frequency (Hz)
Bandwidth (Hz)
Gain (dB)
Sample Frequency
Derived Filter Section Requirements
Q
osr
f0 (with pre-warp)
Gain (V/V)
User Module Design Parameters
Enter:
C2 ( to UM)
CA (default to UM)
CB (default to UM)
C3 (calculated)
C3 ( to UM)
C4 (calculated)
C4 ( to UM)
C1 (calculated)
C1 ( to UM)
Calculated Q
Required fs
Divide by n (Calculated for 24 MHz clock)
Adjusted divide by n
Sample Clock (Hz)
Calculated Gain (V/V)
120000.0
10000.0
0.00
1500000.0
12.000
12.500
122592.1318
1.000
14
32
32
17.74
18
2.254
2
1.125
1
13.541
1500000.000
4.00
4
1500000.000
0.889
Cypress MicroSystems 1 Pole Pair Low Pass Filter Design, Rev 2.1
Design Requirements
Enter:
Corner Frequency (Hz)
11000.0
Enter:
Gain (dB)
0.00
sample freq
1500000.00
Enter 0 or 1:
Type
Butterworth
1
Enter 0 or 1:
.1 dB Cheb.
0
Enter 0 or 1:
1 dB Cheb.
0
Enter 0 or 1:
Bessel
0
Enter 0 or 1:
Custom Complex Poles
0
Enter 0 or 1:
Custom Real Poles
0
Design Procedure
Enter Data fields in yellow
Verify calculated Cx parameters in range of 1:31
Verify calculated "d" matches designed "d"
Verify calculated corner frequency matches designed value
Adjust plot scales as necessary
Transfer values for C1,C2,C3,C4,CA,CB User Module Parameter Table
Select clock source and dividers (24V1,2 or dig block), set for div by n
1.0
Derived Filter Section Requirements
OSR
d (damping ratio)
Custom Complex Poles
Enter Real Part of Pole Location
Enter Imaginary Part of Pole Location
0.0
With pre-warp allowance
Design Procedure
Enter Filter Specification (data fields in yellow)
Enter C2 value ( range 1:31)
Verify C1-4 values in range 1:31
Select Plot Resolution, adjust scales as necessary
Verify expected filter performance, adjust C2 and Sample Frequency
Transfer values for C1,C2,C3,C4,CA,CB to User Module Parameter Table
Select clock source and dividers (24V1,2 or dig block), set for div by n
Enter resolution
0 for Narrow Band, 1 for Wide Band
0.000
Band Pass Frequency Response
-1.0
User Module Design Parameters
If C2<1 reduce sample freq
-2.0
-3.0
-4.0
If C4>>31, reduce sample freq
-5.0
-6.0
-7.0
100000
110000
Nominal
120000
Expected
130000
140000
Freq (Hz)
150000
d compensated
scaled f0
Gain (V/V)
C2 (calculated)
C2 ( to UM)
CA (default to UM)
CB (default to UM)
C4 (calculated)
C4 ( to UM)
C3 (calculated)
C3 ( to UM)
C1 (calculated)
C1 ( to UM)
Caculated d
Required fs
Divide by n (Calculated for 24 MHz clock)
Adjusted Divide by n
Sample Clock (Hz)
Corner Frequency
Gain Calculated (V/V)
113
136.364
1.414
1.445
11001.95
1.000
1.020
1
32
32
31.368
31
2.061
2
1.000
1
1.392
1500000.000
4.000
4
1500000.000
10633.987
1.00
Custom Real Poles
Enter Plow scaled to corner freq.
Enter Phigh scaled to corner freq
0
-10
-20
-30
0.4
0.7
0.037
1
Low Pass Frequency Response
10
Gain (dB)
1 Pole Pair Band Pass Filter Design, Rev 2.1
Gain (dB)
Cypress MicroSystems
Design Requirements
Enter:
Enter:
Enter:
Enter:
Bu
.1Ch
1 Ch
Bess
Custom
re
im
0.707107 0.707107
0.6104
0.7106
0.4508
0.7351
1.103
0.6368
0.4
0.7
-40
-50
-60
real
selected
Nominal
0.037
1
0.707107
0.707107
Expected
-70
-80
1000
10000
100000
Freq (Hz)
1000000
Parameters and Resources
Set User Module Parameters
Control LPF polarity in software
Set Global Parameters
Easily limited to ref and clock selections
Set Pin-outs
Use modulator bit to generate full wave detector
Placement limited to ASC10 blocks
Comparator output routed through DigBuf
Modulator built into LPF2 User Module
114
Software
Start analog user modules
Enable modulator
AMD_CR1 is in Bank 1
;------------------------------------------------
; X-10 Receiver Assembly main line
;-----------------------------------------------include "m8c.inc"
; part specific constants
; and macros
include "memory.inc" ; Constants & macros for
; SMM/LMM and Compiler
include "PSoCAPI.inc" ; PSoC API definitions for
; all User Modules
export _main
_main:
;
Compile
Build
Switch to Debugger
Connect to ICE
Download program
RUN
;
Set UM power and start
mov A, PGA_1_HIGHPOWER
call PGA_1_Start
mov A, BPF2_1_HIGHPOWER
call BPF2_1_Start
mov A, LPF2_1_HIGHPOWER
call LPF2_1_Start
mov A, CMPPRG_1_HIGHPOWER
call CMPPRG_1_Start
Enable Modulator in LPF2_1
M8C_SetBank1
mov reg[AMD_CR1], 04h
M8C_SetBank0
.terminate:
jmp .terminate
115
System Test
Signal source: waveform generator in burst mode
120 kHz, 1 msec at 120 Hz rate
120 kHz carrier burst
Band Pass Filter output
Full Wave Detector/LPF output
Detected carrier output
Total design, program, build and test: 2.0 Hours ( + documentation)
116
Advanced Analog Design Summary
PSoC offers flexible resources to accomplish sensor
interfaces, signal processing, and system controls.
PSoC Designer quickly and easily unlocks the Analog
functionality of PSoC
Filters
References
Amplifiers
Clocking Options
Power Concerns
ADCs
…and more
117