MAXIM MAX8810AETM

19-3886; Rev 1; 8/06
KIT
ATION
EVALU
E
L
B
A
AVAIL
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Features
The MAX8809A/MAX8810A synchronous, 2-/3-/4phase, step-down, current-mode controllers with integrated dual-phase MOSFET drivers provide flexible
solutions that fully comply with Intel® VRD11/VRD10
and AMD K8 Rev F CPU core supplies. The flexible
design supplies load currents up to 150A for low-voltage CPU core power requirements.
A tri-state SEL input is available to configure the VID
logic for either the Intel VRD11/VRD10 or AMD K8 Rev F
applications. An enable input (EN) is available to disable the IC. True-differential remote output-voltage
sensing enables precise regulation at the load by eliminating the effects of trace impedance in the output and
return paths. A high-accuracy DAC combined with precision current-sense amplifiers and droop control
enable the MAX8809A/MAX8810A to meet the most
stringent tolerance requirements of new-generation
high-current CPUs. These ICs use either integral or voltage-positioning feedback control to achieve high output-voltage accuracy.
The COMP input allows for either positive or negative
voltage offsets from the VID code voltage. A powergood signal (VRREADY) is provided for startup
sequencing and fault annunciation. The SS/OVP pin
enables the programming of the soft-start period, and
provides an indication of an overvoltage condition. A
soft-stop feature prevents negative voltage spikes on
the output at turn-off, eliminating the need for an external Schottky clamp diode.
The MAX8809A/MAX8810A incorporate a proprietary
“rapid active average” current-mode control scheme for
fast and accurate transient-response performance, as
well as precise load current sharing. Either the inductor
DCR or a resistive current-sensing element is used for
current sensing. When used with DCR sensing, rapid
active current averaging (RA2) eliminates the tolerance
effects of the inductance and associated current-sensing components, providing superior phase current
matching, accurate current limit, and precise load-line.
The MAX8809A operates as a single-chip, 2-phase
solution with integrated drivers. It also provides a 3rdphase PWM output and easily supports 3-phase design
by adding the MAX8552 high-performance driver. The
MAX8810A enables up to 4-phase designs by adding
the MAX8523 high-performance dual driver for a compact 2-chip solution.
♦ VRD11/VRD10 and K8 Rev F Compliant
♦ ±0.35% Initial Output Voltage Accuracy
♦ Dual Integrated Drivers with Integrated Bootstrap
Diodes
♦ Up to 26V Input Voltage
♦ Adaptive Shoot-Through Protection
♦ Soft-Start, Soft-Stop, VRREADY Output
♦ Fast Load Transient Response
♦ Individual Phase, Fully TemperatureCompensated Cycle-by-Cycle Average Current
Limit
♦ Current Foldback at Short Circuit
♦ Voltage Positioning or Integral Feedback
♦ Differential Remote Voltage Sensing
♦ Programmable Positive and Negative Offset
Voltages
♦ 150kHz to 1.2MHz Switching Frequency per Phase
♦ NTC-Based, Temperature-Independent Load Line
♦ Precise Phase Current Sharing
♦ Programmable Thermal-Monitoring Output
(VRHOT)
♦ 6A Peak MOSFET Drivers
♦ 0.3Ω/0.85Ω Low-Side, 0.8Ω/1.1Ω High-Side
Drivers (typ)
Intel is a registered trademark of Intel Corp.
♦ 40-Pin and 48-Pin Thin QFN Packages
Applications
Desktop PCs
Servers, Workstations
Desknote and LCD PCs
Voltage-Regulator Modules
Ordering Information
PART
PINPACKAGE
PKG
CODE
FUNCTION
MAX8809AETL+
40 Thin QFN
5mm x 5mm
T4055-1
2-/3-phase
MAX8810AETM+
48 Thin QFN
6mm x 6mm
T4866-1
2-/3-/4-phase
+Denotes lead-free package.
Note: All parts are specified in the -40°C to +85°C extended
temperature range.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8809A/MAX8810A
General Description
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
REF, COMP, SS/OVP, OSC, NTC, VRTSET,
RS+, RS-, PWM_ to GND.......................-0.3V to (VCC + 0.3V)
CS_+, CS_-, VID_, BUF, EN, ILIM, SEL, VRREADY,
VRHOT, VCC to GND ............................................-0.3V to +6V
BST_ to PGND_ ......................................................-0.3V to +35V
LX_ to PGND_............................................................-1V to +28V
BST_ to VL_ ...............................................................-1V to +30V
DH_ to PGND_ .........................................-0.3V to (VBST_ + 0.3V)
DH_, BST_ to LX_ .....................................................-0.3V to +7V
VL_ to PGND_ ..........................................................-0.3V to +7V
DL_ to PGND_ ..........................................-0.3V to (VVL_ + 0.3V)
PGND_ to GND......................................................-0.3V to +0.3V
CS_+ to CS_-.........................................................-0.3V to +0.3V
DH_, DL_ Current ....................................................±200mARMS
VL_ to BST_ Diode Current...........................................50mARMS
Continuous Power Dissipation (TA = +70°C)
40-Pin Thin QFN 5mm x 5mm
(derate 35.7mW/°C above +70°C) ..........................2857.1mW
48-Pin Thin QFN 6mm x 6mm
(derate 37mW/°C above +70°C) ................................2963mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩ pullup to 5V, RSS/OVP = 12kΩ to GND, RNTC = 10kΩ to GND, fSW = 300kHz, RVRTSET = 118kΩ to GND, VCS_+ = VCS_- = 1V,
PWM_ = unconnected, RVRHOT = 249Ω pullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA = 0°C
to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
VCC Operating Range
VCC UVLO Trip Level
VCC Shutdown Supply Current
MIN
TYP
4.5
MAX
UNITS
5.5
V
Rising
4.0
4.25
4.5
Falling
3.7
4.0
4.3
V
VCC < 3.75V
0.35
mA
VCC Standby Supply Current
VEN = 0V
0.5
mA
VCC Operating Supply Current
VRS+ - VRS- = 1.0V, no switching, VDAC = 1.0V (Note 1)
13
mA
Thermal Shutdown
Temperature rising, hysteresis = 25°C (typ)
+160
°C
INTERNAL REFERENCE (REF)
Output Voltage
IREF = -100µA
1.992
Output Regulation (Sourcing)
VCC = 4.5V at IREF = -500µA to VCC = 5.5V at
IREF = -100µA
Output Regulation (Sinking)
VCC = 4.5V at IREF = +100µA to VCC = 5.5V at
IREF = +500µA
Reference UVLO Trip Level
Rising (100mV typ hysteresis)
2.000
2.008
V
-0.05
+0.05
%
-0.2
+0.2
%
1.84
V
BUF REFERENCE
BUF Regulation Voltage
IBUF = 0A
0.99
BUF Output Regulation
VCC = 4.5V at IBUF = +100µA to VCC = 5.5V at
IBUF = +500µA
-0.25
1.0
1.01
V
+0.25
%
SOFT-START
EN Startup Delay (TD1)
From EN rising to VOUT rising
1.6
Soft-Start Period Range (TD2)
12kΩ < RSS/OVP < 90.9kΩ
0.5
Soft-Start Tolerance
RSS/OVP = 56kΩ
2.25
Intel Boot-Level Duration (TD3)
SEL = GND or SEL = VCC
175
2
2.2
2.8
ms
6.5
ms
3.00
3.75
ms
250
350
µs
_______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩ pullup to 5V, RSS/OVP = 12kΩ to GND, RNTC = 10kΩ to GND, fSW = 300kHz, RVRTSET = 118kΩ to GND, VCS_+ = VCS_- = 1V,
PWM_ = unconnected, RVRHOT = 249Ω pullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA = 0°C
to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE REGULATION
RS+ Input Bias Current
VRS+ = 1V
0.1
1
µA
RS- Input Bias Current
VRS- = 0.2V
0.1
1
µA
Output Voltage Initial Accuracy
VDAC = 1V (Note 1)
-0.35
+0.35
%
Droop Accuracy
VDAC = 1V (Note 1),
RNTC = 10kΩ
TA = +25°C to +85°C
-3.5
+3.5
TA = -5°C to +85°C
-5.5
+5.5
gMV Amplifier Transconductance
1.94
gMV Gain Bandwidth Product
Comp Output Current
VDAC - VRS+ = 200mV (Note 1)
2.00
2.06
%
mS
5
MHz
385
µA
CURRENT LIMIT
Average Current-Limit Trip Level
Accuracy
VILIM = 1.5V
-6
ILIM Input Bias Current
ILIM Default Program Level
VILIM > VCC - 0.2V
+6
%
0.01
1
µA
1.197
1.330
1.463
V
0.8
0.85
0.9
V
ENABLE INPUT (EN)
Turn-On Threshold (Rising)
VCC = 4.5V to 5.5V, 100mV typ hysteresis
LOGIC INPUTS (VID0–VID7)
INTEL (SEL = HIGH OR LOW)
Input Low Level
VCC = 4.5V to 5.5V
Input High Level
VCC = 4.5V to 5.5V
Input Pulldown Resistance
0.4
0.8
V
V
100
270
kΩ
0.6
V
270
kΩ
200
kΩ
AMD (SEL = UNCONNECTED)
Input Low Level
VCC = 4.5V to 5.5V
Input High Level
VCC = 4.5V to 5.5V
Input Pulldown Resistance
1.4
V
100
LOGIC INPUT (SEL)
Internal Bias Resistance
50
Internal Bias Voltage
VCC = 4.5V to 5.5V
Input Low Level
VCC = 4.5V to 5.5V
Input High Level
VCC = 4.5V to 5.5V
100
VCC / 2
V
0.5
VCC 0.5
V
V
VRREADY OUTPUT
Output Low Level
IVRREADY = +4mA
0.4
V
Output High Leakage
VVRREADY = 5.5V
1
µA
VRREADY Blanking Time
From EN rising to VRREADY rising, RSS/OVP = 12kΩ
5.5
ms
3.0
_______________________________________________________________________________________
3
MAX8809A/MAX8810A
ELECTRICAL CHARACTERISTICS (continued)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩ pullup to 5V, RSS/OVP = 12kΩ to GND, RNTC = 10kΩ to GND, fSW = 300kHz, RVRTSET = 118kΩ to GND, VCS_+ = VCS_- = 1V,
PWM_ = unconnected, RVRHOT = 249Ω pullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA = 0°C
to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
(VRS+ - VRS-) rising
VDAC +
0.150
VDAC +
0.200
(VRS+ - VRS-) falling
VDAC +
0.075
VDAC +
0.125
(VRS+ - VRS-) falling
VDAC 0.250
VDAC 0.200
(VRS+ - VRS-) rising
VDAC 0.175
VDAC 0.125
Intel (SEL = High or Low)
(VRS+ - VRS-) rising (Note 1)
VDAC +
0.150
AMD (SEL = Unconnected)
(VRS+ - VRS-) rising
1.750
SS/OVP High Level
ISS/OVP = -10mA
VCC 0.450
VRREADY Upper Threshold
(Note 1)
VRREADY Lower Threshold
(Note 1)
UNITS
V
V
OVERVOLTAGE PROTECTION
VDAC + VDAC +
0.175
0.200
1.775
1.800
V
V
V
OSCILLATOR
Oscillator Frequency Accuracy
(per Phase)
Frequency per phase = 300kHz
Switching Frequency Range
(per Phase)
-10
+10
%
150
1200
kHz
30.0
31.2
V/V
CURRENT-SENSE AMPLIFIERS
Current-Sense Amplifier Gain (GCA)
RNTC = 10kΩ, TA = +25°C to +85°C
28.8
CS_+ Input Bias Current
VCS_+ = VCS_- = 2V
0.3
3.0
µA
CS_- Input Bias Current
VCS_+ = VCS_- = 2V
0.6
5.5
µA
CS to PWM_ Delay
VCOMP falling
20
ns
GAIN TEMPERATURE COMPENSATION (NTC)
Compensation Accuracy
RNTC temperature = 0°C to +125°C
(10k NTC Panasonic ERTJ1VR103)
-6
+6
%
VRHOT TEMPERATURE MONITORING
VRHOT Output Low Voltage
IVRHOT = +4mA
0.4
V
VRHOT Output High Leakage Current
VVRHOT = 5.5V
5
µA
+60
+125
°C
-5
+5
°C
VRTSET Temperature Range
VRTSET Accuracy
4
RNTC temperature = +60°C to +125°C, 15°C
hysteresis (typ) (10k NTC Panasonic ERTJ1VR103)
_______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩ pullup to 5V, RSS/OVP = 12kΩ to GND, RNTC = 10kΩ to GND, fSW = 300kHz, RVRTSET = 118kΩ to GND, VCS_+ = VCS_- = 1V,
PWM_ = unconnected, RVRHOT = 249Ω pullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA = 0°C
to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.1
0.4
4.5
4.9
V
PWM DRIVER
Output Low Level
IPWM_ = +5mA
Output High Level
IPWM_ = -5mA
Source Current
VPWM_ = VCC - 2V
52
mA
Sink Current
VPWM_ = 2V
65
mA
10
ns
VCC 0.7
V
Rise/Fall Times
PWM Disable Program Threshold
4V < VCC < 5.5V
3.0
V
GATE-DRIVER SPECIFICATIONS
VL_, BST_ to LX_ Input Voltage Range
4.5
6.5
V
26
V
3.55
3.80
V
1
1.6
DH_ = LX_
1.1
1.8
DH_ = BST_
0.6
1
LX Operating Range
VL_ UVLO Threshold (VL12,
MAX8809A; VL1, MAX8810A)
Driver Static Supply Current, IVL_
(per Channel)
Boost Static Supply Current, IBST_
(per Channel)
DH Driver Resistance
VVL_ rising, 250mV hysteresis (typ)
DH_ = BST_
3.25
Sourcing current, VVL _ = 6.5V
1.1
2.0
Sinking current, VVL _ = 6.5V
0.8
1.2
mA
mA
Ω
Sourcing current, VVL _ = 6.5V
0.85
1.7
Sinking current, VVL _ = 6.5V
0.3
0.6
DH_ Rise Time (trDH)
CDH_ = 3000pF
14
ns
DH_ Fall Time (tfDH)
CDH_ = 3000pF
9
ns
DL_ Rise Time (trDL)
CDL_ = 3000pF
10
ns
DL Driver Resistance
Ω
DL_ Fall Time (tfDL)
CDL_ = 3000pF
7
ns
DH_ Propagation Delay (tpDHf)
CS+ rising to DH falling
32
ns
Dead Time (tpDLr)
LX_ falling to DL_ rising
18
ns
Dead Time (tDEAD)
DL_ falling to DH_ rising
35
ns
6
Ω
INTERNAL BOOST-DIODE SPECIFICATIONS
On-Resistance
IBST_ = 2mA
_______________________________________________________________________________________
5
MAX8809A/MAX8810A
ELECTRICAL CHARACTERISTICS (continued)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩ pullup to 5V, RSS/OVP = 12kΩ = RNTC = 10kΩ to GND, fSW = 300kHz, RVRTSET = 50kΩ to GND, VCS_+ = VCS_- = 1V, PWM_ =
unconnected, RVRHOT = 249Ω pullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA = -40°C to
+85°C.) (Note 2)
PARAMETER
CONDITIONS
VCC Operating Range
MIN
TYP
MAX
UNITS
V
4.5
5.5
Rising
4.0
4.5
Falling
3.7
4.3
Output Voltage
IREF = -100µA
1.99
2.01
V
Output Regulation (Sourcing)
VCC = 4.5V at IREF = -500µA to VCC = 5.5V at
IREF = -100µA
-0.065
+0.065
%
Output Regulation (Sinking)
VCC = 4.5V at IREF = +100µA to VCC = 5.5V at
IREF = +500µA
-0.2
+0.2
%
BUF Regulation Voltage
IBUF = 0A
0.99
1.01
V
BUF Output Regulation
VCC = 4.5V at IBUF = +100µA to VCC = 5.5V at
IREF = +500µA
-0.4
+0.4
%
EN Startup Delay (TD1)
From EN rising to VOUT rising
1.6
2.8
ms
Soft-Start Period Range (TD2)
12kΩ < RSS/OVP < 90.9kΩ
0.5
6.5
ms
Soft-Start Tolerance
RSS/OVP = 56kΩ
2.25
3.75
ms
Intel Boot Level Duration (TD3)
SEL = GND or SEL = VCC
175
350
µs
1
µA
1
µA
VCC UVLO Trip Level
V
INTERNAL REFERENCE (REF)
BUF REFERENCE
SOFT-START
VOLTAGE REGULATION
RS+ Input Bias Current
VRS+ = 1.0V
RS- Input Bias Current
VRS- = 0.2V
Output-Voltage Initial Accuracy
VDAC_ = 1V (Note 1)
gMV Amplifier Transconductance
-0.35
+0.35
%
1.91
2.06
mS
-11
+11
%
1
µA
1.197
1.463
V
0.8
0.9
V
0.4
V
270
kΩ
CURRENT LIMIT
Average Current-Limit Trip-Level
Accuracy
VILIM = 1.5V
ILIM Input Bias Current
ILIM Default Program Level
VILIM > VCC - 0.2V
ENABLE INPUT (EN)
Turn-On Threshold (Rising)
VCC = 4.5V to 5.5V, 100mV typ hysteresis
LOGIC INPUTS (VID0–VID7)
INTEL (SEL = HIGH OR LOW)
Input Low Level
VCC = 4.5V to 5.5V
Input High Level
VCC = 4.5V to 5.5V
Input Pulldown Resistance
6
0.8
100
_______________________________________________________________________________________
V
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩ pullup to 5V, RSS/OVP = 12kΩ = RNTC = 10kΩ to GND, fSW = 300kHz, RVRTSET = 50kΩ to GND, VCS_+ = VCS_- = 1V, PWM_ =
unconnected, RVRHOT = 249Ω pullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA = -40°C to
+85°C.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.6
V
AMD (SEL = UNCONNECTED)
Input Low Level
VCC = 4.5V to 5.5V
Input High Level
VCC = 4.5V to 5.5V
Input Pulldown Resistance
1.4
V
100
270
kΩ
50
200
kΩ
0.5
V
LOGIC INPUT (SEL)
Internal Bias Resistance
Input Low Level
VCC = 4.5V to 5.5V
Input High Level
VCC = 4.5V to 5.5V
VCC 0.5
V
VRREADY OUTPUT
Output Low Level
IVRREADY = +4mA
0.4
V
Output High Leakage
VVRREADY = 5.5V
1
µA
VRREADY Blanking Time
From EN rising to VRREADY rising, RSS/OVP = 12kΩ
ms
3.0
5.5
(VRS+ - VRS-) rising
VDAC +
0.150
VDAC +
0.200
(VRS+ - VRS-) falling
VDAC +
0.075
VDAC +
0.125
(VRS+ - VRS-) falling
VDAC 0.250
VDAC 0.200
(VRS+ - VRS-) rising
VDAC 0.175
VDAC 0.125
Intel (SEL = High or Low)
(VRS+ - VRS-) rising (Note 1)
VDAC +
0.150
VDAC +
0.200
V
AMD (SEL = Unconnected)
(VRS+ - VRS-) rising
1.75
1.80
V
SS/OVP High Level
ISS/OVP = 10mA
VCC 0.450
VRREADY Upper Threshold
(Note 1)
VRREADY Lower Threshold
(Note 1)
V
V
OVERVOLTAGE PROTECTION
V
OSCILLATOR
Oscillator Frequency Accuracy
(per Phase)
Switching Frequency Range
(per Phase)
Frequency per phase = 300kHz
-20
+20
%
150
1200
kHz
_______________________________________________________________________________________
7
MAX8809A/MAX8810A
ELECTRICAL CHARACTERISTICS (continued)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩ pullup to 5V, RSS/OVP = 12kΩ = RNTC = 10kΩ to GND, fSW = 300kHz, RVRTSET = 50kΩ to GND, VCS_+ = VCS_- = 1V, PWM_ =
unconnected, RVRHOT = 249Ω pullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA = -40°C to
+85°C.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
33
V/V
CURRENT-SENSE AMPLIFIERS
Current-Sense Amplifier Gain (GCA)
RNTC = 10kΩ
CS_+ Input Bias Current
VCS_+ = VCS_- = 2V
27
4.5
µA
CS_- Input Bias Current
VCS_+ = VCS_- = 2V
7
µA
+7.5
%
GAIN TEMPERATURE COMPENSATION (NTC)
Temperature Compensation Accuracy
RNTC temperature = 0°C to +125°C
(10k NTC Panasonic ERTJ1VR103)
-7.5
VRHOT TEMPERATURE MONITORING
VRHOT Output Low Voltage
4mA sink current
VRHOT Output High Leakage Current
VVRHOT = 5.5V
VRTSET Temperature Range
VRTSET Accuracy
RNTC temperature = +60°C to +125°C (10k NTC
Panasonic ERTJ1VR103)
0.4
V
5
µA
+60
+125
°C
-5
+5
°C
0.4
V
PWM DRIVER
Output Low Level
IPWM_ = +5mA
Output High Level
IPWM_ = -5mA
PWM Disable Program Threshold
4V < VCC < 5.5V
4.5
V
3
V
GATE-DRIVER SPECIFICATIONS
VL_, BST_ to LX_ Input Voltage Range
4.5
LX_ Operating Range
VL_ UVLO Threshold (MAX8809A,
VL12; MAX8810A, VL1)
Driver Static Supply Current,
IVL_ (per Channel)
Boost Static Supply Current,
IBST_ (per Channel)
DH_ Driver Resistance
DL_ Driver Resistance
VVL_ rising, 250mV hysteresis (typ)
3.25
V
26
V
3.80
V
DH_ = BST_
1.6
DH_ = LX_
1.8
DH_ = BST_
1
Sourcing current, VVL _ = 6.5V
2.0
Sinking current, VVL _ = 6.5V
1.2
Sourcing current, VVL _ = 6.5V
1.7
Sinking current, VVL _ = 6.5V
0.6
Note 1: VDAC refers to the internal voltage set by the VID code.
Note 2: Specifications to -40°C are guaranteed by design and characterization.
8
6.5
_______________________________________________________________________________________
mA
mA
Ω
Ω
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
1.32
OUTPUT VOLTAGE (V)
60
VIN = 12V
40
30
VIN = 20V
20
1.30
1.28
1.26
1.24
1.22
ILOAD = 0A
1.35
ILOAD = 50A
1.30
1.25
1.20
1.20
0
1.18
1
10
100
LOAD CURRENT (A)
1000
1.15
0
20
40
60
80
LOAD CURRENT (A)
100
120
25
0
50
75
100
125
INDUCTOR TEMPERATURE (°C)
ACTIVE CURRENT SHARING
vs. LOAD CURRENT
OUTPUT LOAD TRANSIENT
MAX8809A toc04
25
MEASURED ACROSS
C19, C20, C26, C27
20
50mV/div
VDC (mV)
VOUT
MAX8809A toc05
10
15
10
60A/div
IOUT
5
AVERAGE DCR IS 0.86mΩ (+25°C)
0
20μs/div
0
DYNAMIC VID RESPONSE
100
VRREADY
1V/div
MAX8809A toc07
VRREADY
50
LOAD CURRENT (A)
SOFT-START WAVEFORMS (INTEL)
MAX8809A toc06
EFFICIENCY (%)
70
1.34
OUTPUT VOLTAGE (V)
80
1.40
MAX8809A toc02
VIN = 7V
50
1.36
MAX8809A toc01
100
90
OUTPUT VOLTAGE
vs. INDUCTOR TEMPERATURE
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8809A toc03
EFFICIENCY vs. LOAD CURRENT
ROSC = 130kΩ
EN
1V/div
1V/div
500mV/div
VOUT
VRREADY
1V/div
VOUT
60A/div
IOUT
500mA/div
IIN
200μs/div
1ms/div
_______________________________________________________________________________________
9
MAX8809A/MAX8810A
Typical Operating Characteristics
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO = 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA = +25°C,
unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO = 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA = +25°C,
unless otherwise noted.)
MAX8809A toc08
IIN
MAX8809A toc09
SHUTDOWN WAVEFORMS AT NO LOAD
SOFT-START WAVEFORMS (AMD)
EN
500mA/div
1V/div
VRREADY
VRREADY
1V/div
1V/div
VOUT
VOUT
1V/div
1V/div
VEN
IIN
500mA/div
1V/div
400μs/div
1ms/div
SHORT-CIRCUIT AND
RECOVERY WAVEFORMS
EN
VRREADY
MAX8809A toc11
MAX8809A toc10
SHUTDOWN WAVEFORMS AT FULL LOAD
2V/div
VRREADY
VOUT
2V/div
500mV/div
1V/div
VOUT
IIN
IIN
5A/div
500mV/div
50A/div
5A/div
IOUT
500μs/div
40μs/div
REFERENCE VOLTAGE
vs. AMBIENT TEMPERATURE
CURRENT THRESHOLD
vs. INDUCTOR CASE TEMPERATURE
120
ILIM = 100A
100
80
60
40
MAX8809A toc13
140
2.10
REFERENCE VOLTAGE (V)
160
ILIM = 155A
MAX8809A toc12
180
RMS CURRENT LIMIT (A)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
2.05
2.00
1.95
20
1.90
0
-10 0 10 20 30 40 50 60 70 80 90 100
INDUCTOR TEMPERATURE (°C)
10
-40
-20
0
20
40
60
AMBIENT TEMPERATURE (°C)
______________________________________________________________________________________
80
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
BUF VOLTAGE
vs. AMBIENT TEMPERATURE
1.00
0.95
1100
900
2/4 PHASE
700
3 PHASE
500
MAX8809A toc16
MAX8809A toc15
1000
950
900
FREQUENCY (kHz)
1.05
1300
PER-PHASE FREQUENCY (kHz)
MAX8809A toc14
1.10
BUF VOLTAGE (V)
CLOCK FREQUENCY
vs. TEMPERATURE
PER-PHASE FREQUENCY vs. ROSC
850
800
750
700
650
600
300
550
100
-20
0
20
40
60
AMBIENT TEMPERATURE (°C)
80
500
0
100
ROSC (kΩ)
15
10
5
4
3
2
100
30
40
50
60
50
0
20
40
60
RSS/OVP (kΩ)
80
100
50
100
150
200
RVRTSET (kΩ)
CDL_ = CDH_ = 3300pF
1400
500mV/div
5V/div
VL_ POWER DISSIPATION (mW)
MAX8809A toc20
1600
1V/div
SS/OVP
0
250
300
VL_ POWER DISSIPATION
vs. PER-PHASE SWITCHING FREQUENCY
OUTPUT OVERVOLTAGE
PROTECTION WAVEFORM
VRREADY
80
60
ROS (kΩ)
VOUT
90
70
0
0
85
110
1
5
60
120
VRHOT SETPOINT (°C)
20
10
35
TEMPERATURE (°C)
130
MAX8809A toc18
MAX8809A toc17
25
20
-15
VRHOT SETPOINT
vs. RVRTSET
6
SOFT-START DURATION (ms)
OUTPUT VOLTAGE (mV)
30
-40
SOFT-START DURATION
vs. RSS/OVP
OUTPUT VOLTAGE OFFSET
vs. ROS
35
200
MAX8809A toc19
-40
MAX8809A toc21
0.90
1200
1000
800
600
400
200
0
2μs/div
0
200
400
600
fS (kHz)
800
1000
______________________________________________________________________________________
11
MAX8809A/MAX8810A
Typical Operating Characteristics (continued)
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO = 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA = +25°C,
unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO = 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA = +25°C,
unless otherwise noted.)
DL_ RISE/FALL TIME
vs. LOAD CAPACITANCE
VL_ POWER DISSIPATION
vs. LOAD CAPACITANCE
MAX8809A toc23
350
25
300
RISE/FALL TIME (ns)
250
200
150
20
DL_ RISE
15
10
100
DL_ FALL
5
50
0
0
2000 3000 4000 5000 6000
DH_/DL_ LOAD CAPACITANCE (pF)
1000
7000
25
MAX8809A toc24
30
25
DH_ RISE
CDH_ = CDL_ = 3300pF
20
RISE/FALL TIME (ns)
RISE/FALL TIME (ns)
7000
DH_/DL_ RISE/FALL TIME
vs. AMBIENT TEMPERATURE
DH_ RISE/FALL TIME
vs. LOAD CAPACITANCE
20
15
10
3000
5000
LOAD CAPACITANCE (pF)
DH_ FALL
DH_ RISE
15
DL_ RISE
10
DH_ FALL
5
5
MAX8809A toc25
1000
DL_ FALL
0
0
0
2000
4000
6000
LOAD CAPACITANCE (pF)
-40
8000
VL_ SUPPLY CURRENT
vs. PER-PHASE SWITCHING FREQENCY
CDH_ = CDL_ = 3300pF
200
0
20
40
60
AMBIENT TEMPERATURE (°C)
DL_
10V/div
150
LX_
10V/div
DH_
20V/div
100
50
0
0
12
80
SWITCHING WAVEFORMS
MAX8809A toc26
250
-20
MAX8809A t0c27
VL_ POWER DISSIPATION (mW)
30
MAX8809A toc22
400
VL_ SUPPLY CURRENT (mA)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
200
400
600
fS (kHz)
800
1000
200ns/div
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
BST_ AND VL_ WAVEFORMS
VIN = 8V
200mV/div
(AC-COUPLED)
BST_
LX_
5V/div
MAX8809A toc29
VL_
50
500mV/div
(AC-COUPLED)
45
PROPAGATION DELAY (ns)
MAX8809A toc28
DH_ FALLING PROPAGATION DELAY
vs. TEMPERATURE
40
35
30
25
20
-40
500ns/div
-20
0
20
40
60
AMBIENT TEMPERATURE (°C)
80
Pin Description
PIN
NAME
FUNCTION
MAX8809A
MAX8810A
1
48
VRREADY
2
1
ILIM
Current-Limit Set Input. Connect to the center tap of an external resistor-divider from REF
to GND to set the cycle-by-cycle average current-limit threshold. Connect ILIM to VCC to
select the default current-limit threshold.
3
2
REF
Internal Reference Output. REF regulates to 2V. Bypass REF to GND with a 0.1µF to 1µF
ceramic capacitor. Do not use a capacitor greater than 1µF. REF sources up to 500µA for
external loads. REF is enabled when VCC is above UVLO regardless of the state of EN.
Open-Drain, Power-Okay Indicator. VRREADY is an open-drain output that goes high
impedance when the output is in regulation. VRREADY pulls low when the output is out of
regulation, the IC is in shutdown, or VCC is below the UVLO threshold.
Error-Amplifier Output. Connect COMP to the compensation network to implement either
voltage positioning or integral feedback-control. Connect a resistor from COMP to GND
to set the offset voltage. See the Loop-Compensation Design section for details on
determining the compensation network.
4
3
COMP
5
5
GND
Analog Ground. Connect GND to the analog ground plane.
6
6
VCC
IC Supply Input. Connect VCC to a 4.5V to 5.5V power supply. Bypass VCC to GND with
a 1µF or larger ceramic capacitor.
7
8
RS-
Output-Voltage Remote-Sense Negative Input. Connect RS- to the VSS_SEN remotesense point at the load when using the remote sense. Otherwise, connect RS- to GND at
the load.
8
9
RS+
Output-Voltage Remote-Sense Positive Input. Connect RS+ to the VCC_SEN remotesense point at the load when using remote sense. Otherwise, connect RS+ to the output
at the load.
______________________________________________________________________________________
13
MAX8809A/MAX8810A
Typical Operating Characteristics (continued)
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO = 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA = +25°C,
unless otherwise noted.)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Pin Description (continued)
PIN
NAME
FUNCTION
11
OSC
Internal Clock Oscillator Frequency Set Input. Connect a resistor from OSC to GND to set
the internal oscillator frequency. See the Setting the Switching Frequency section for
determining the resistor value.
12
SS/OVP
Soft-Start Program Input and Overvoltage-Protection Fault Flag. Connect a resistor from
SS/OVP to GND to set the soft-start period. SS/OVP pulls to VCC during an OVP event to
signal the fault condition. See the Soft-Start section for determining the resistor value.
VRTSET
Temperature Comparator Program Input. Connect a resistor from VRTSET to GND to set
the VRHOT temperature threshold. Connect VRTSET to VCC to disable the VRHOT
monitoring feature. See the Temperature Monitoring (VRTSET, VRHOT) section for
resistor selection.
MAX8809A
MAX8810A
9
10
11
14
13
12
14
NTC
Temperature-Sensing Input. Connect a 10kΩ NTC thermistor between NTC and GND for
load-line independent temperature compensation. Connect NTC to VCC to disable the
temperature compensation and VRHOT monitoring features. See the Temperature
Monitoring (VRTSET, VRHOT) section for more details on selection of the NTC device.
13
—
CS3-
Phase 3 Current-Sense Negative Input. Connect to the load side of the output currentsensing element.
14
17
CS3+
Phase 3 Current-Sense Positive Input. Connect CS3+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.
15
18
CS2+
Phase 2 Current-Sense Positive Input. Connect CS2+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.
16
19
CS12-
Phases 1 and 2 Current-Sense Common Negative Input. Connect to the load side of the
output current-sensing elements.
17
20
CS1+
Phase 1 Current-Sense Positive Input. Connect CS1+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.
18
21
EN
Enable Input. Drive EN high to enable the IC. Drive EN low to place the IC in shutdown
mode. If VCC is greater than the UVLO threshold, EN is internally pulled to VCC with a
100kΩ resistor. If VCC is less than the UVLO threshold, EN is internally pulled to GND
with a 2kΩ resistor.
19
23
PWM3
PWM Signal Output for phase 3. PWM3 is low during shutdown, UVLO, and OVP faults.
Connect PWM3 to VCC to enable 2-phase operation.
20
24
VRHOT
Temperature Fault Flag. VRHOT is an active-high, open-drain output that goes high
impedance when the temperature sensed by the thermistor at NTC exceeds the
temperature threshold programmed at VRTSET.
21
25
DH1
Phase 1 High-Side MOSFET Gate-Drive Output. Connect to the gate of the high-side
MOSFET for phase 1. DH1 is pulled low during shutdown, UVLO, and OVP faults.
22
26
LX1
Phase 1 Inductor Sense Point. Connect LX1 to the switched side of the inductor for
phase 1.
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
PIN
NAME
FUNCTION
MAX8809A
MAX8810A
23
27
BST1
Phase 1 High-Side MOSFET Gate-Drive Supply. Connect a 0.22µF or larger ceramic
capacitor from BST1 to LX1 to supply gate drive for the high-side MOSFET. See the Boost
Capacitor Selection section for details on calculating the BST1 capacitor value.
24
28
DL1
Phase 1 Low-Side MOSFET Gate-Drive Output. Connect to the gate of the low-side MOSFET
for phase 1. DL1 is pulled low during undervoltage lockout and pulled high during an OVP
fault. DL1 is high in shutdown if VCC is greater than the UVLO threshold.
25
29
PGND1
Power Ground for the Phase 1 Driver. Connect PGND1 to the source of the phase 1
low-side MOSFET. PGND1 must be connected to PGND2 and GND externally. See the
PC Board Layout Guidelines section for more details.
26
—
VL12
Phase 1 and 2 Low-Side MOSFET Gate-Drive Supply. Connect VL12 to a 4.5V to 6.5V
supply. Bypass VL12 with a 2.2µF or larger ceramic capacitor to the power ground
plane.
27
32
PGND2
Power Ground for the Phase 2 Driver. Connect PGND2 to the source of the phase 2
low-side MOSFET. PGND2 must be connected to PGND1 and GND externally. See the
PC Board Layout Guidelines section for more details.
28
33
DL2
Phase 2 Low-Side MOSFET Gate-Drive Output. Connect to the gate of the low-side MOSFET
for phase 2. DL2 is pulled low during undervoltage lockout and pulled high during an OVP
fault. DL2 is high in shutdown if VCC is greater than the UVLO threshold.
29
34
BST2
Phase 2 High-Side MOSFET Gate-Drive Supply. Connect a 0.22µF or larger ceramic
capacitor from BST2 to LX2 to supply gate drive for the high-side MOSFET. See the Boost
Capacitor Selection section for details on calculating the BST2 capacitor value.
30
35
LX2
Phase 2 Inductor Sense Point. Connect LX2 to the switched side of the inductor for
phase 2.
31
36
DH2
Phase 2 High-Side MOSFET Gate-Drive Output. Connect to the gate of the high-side
MOSFET for Phase 2. DH2 is pulled low during shutdown, UVLO, and OVP faults.
32
38
SEL
VID Table Selection Input. Connect SEL to GND to select the VRD10 VID code
(Table 5). Connect SEL to VCC to select the VRD11 8-bit VID code (Table 6). Leave SEL
unconnected to select the K8 Rev F VID code (Table 4).
33–40
39–46
VID7–VID0
Voltage Identification Code Inputs. Use VID_ to set the output voltage. SEL selects the
VRD10, VRD11, or K8 Rev F VID logic codes. Connect VID_ to the system VTT with a
680Ω resistor for logic-high for Intel VR solutions. Connect VID_ to the system VDDQ
with a 1kΩ resistor for logic-high for AMD VR solutions.
______________________________________________________________________________________
15
MAX8809A/MAX8810A
Pin Description (continued)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Pin Description (continued)
PIN
NAME
FUNCTION
4
BUF
1V Reference Output. Bypass BUF to GND with a 1µF or larger ceramic capacitor.
Connect a resistor from COMP to BUF to set the load-line. See the Loop-Compensation
Design section for more details.
—
7, 10, 37, 47
N.C.
No Internal Connection
—
15
CS4+
Phase 4 Current-Sense Positive Input. Connect CS4+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.
—
16
CS34-
Phases 3 and 4 Current-Sense Common Negative Input. Connect to the load side of
the output current-sensing elements.
—
22
PWM4
PWM Signal Output for Phase 4. PWM4 is low during shutdown, UVLO, and OVP faults.
Connect PWM4 to VCC to enable 3-phase operation. Connect PWM3 and PWM4 to VCC
to enable 2-phase operation.
—
30
VL1
Phase 1 Low-Side MOSFET Gate-Drive Supply. Connect VL1 to a 4.5V to 6.5V supply.
VL1 must be connected to VL2 externally. Bypass the VL1/VL2 connection with a 2.2µF
or larger ceramic capacitor to the power ground plane.
—
31
VL2
Phase 2 Low-Side MOSFET Gate-Drive Supply. Connect VL2 to a 4.5V to 6.5V supply.
VL2 must be connected to VL1 externally. Bypass the VL1/VL2 connection with a 2.2µF
or larger ceramic capacitor to the power ground plane.
—
—
EP
Exposed Paddle. Connect to the analog GND plane for enhanced thermal power
dissipation.
MAX8809A
MAX8810A
—
16
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A/MAX8810A
OSC
2-/3-/4PHASE
CONTROL
OSCILLATOR
MAX8809A
MAX8810A
OPERATION
MODE DETECT
CS1+
S/R
CS12CS2+
S/R
CS3(MAX8809A)
CS3+
S/R
PWM3
S/R
PWM4
(MAX8810A)
CS34(MAX8810A)
CS4+
(MAX8810A)
MAX8810A ONLY
1V
REF
BUF
(MAX8810A)
+
BST1
TEMPERATURE
COMPENSATION
VRREADY
DHOUT
LX
SENSE
POWER-GOOD
CIRCUITRY
CURRENT
FOLDBACK
OVP
THRESHOLD
SOFT-START
SOFT-STOP
LX1
VL1
(MAX8810A)
PWM1
OVP
COMPARATOR
SS/OVP
DH1
DLOUT
DL1
DL
SENSE
PGND1
(MAX8809A)
gMB
-
COMP
DRIVER
CONTROL
LOGIC
2V
REFERENCE
REF
PWM2
VL12
(MAX8809A)
BST2
DHOUT
DH2
LX
SENSE
LX2
VL2
(MAX8810A)
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID
DECODE
LOGIC
DL2
DLOUT
VDAC
DL
SENSE
gMV
PGND2
TEMPERATURE
COMPENSATION
SEL
NTC
THERMISTOR
LINEARIZATION
CIRCUIT
RS+
RSDA
UVLO
VL1
VCC
+
RS-
BIAS
EN
CLAMP
ILIM
REF / 2
VRHOT
VRTSET
NTC
Figure 1. Block Diagram
______________________________________________________________________________________
17
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
tfDL
DL
tpDLr
trDL
tDEAD
LX
trDH
tfDH
DH
Figure 2. Driver Timing Diagram
Detailed Description
The MAX8809A/MAX8810A synchronous, 2-/3-/4phase, step-down, current-mode controllers with integrated dual-phase MOSFET drivers provide flexible
solutions that fully comply with Intel VRD11/VRD10 and
AMD K8 Rev F CPU core supplies. The flexible design
supplies load currents of up to 150A for low-voltage
CPU core power supplies.
The MAX8809A is suitable for 2- or 3-phase core supply applications. With an integrated dual-MOSFET driver, the MAX8809A offers a single-chip IC solution for
dual-phase core supplies. Together with the MAX8552,
a high-performance single-phase MOSFET driver, the
MAX8809A also supports 3-phase core supplies.
Similarly, the MAX8810A features a single IC solution
for dual-phase core supplies. It also features two-IC
solutions for 3- or 4-phase core supplies by adding a
single MOSFET driver (MAX8552) or a dual-MOSFET
driver (MAX8523).
18
Both the MAX8809A and MAX8810A fully comply with
Intel VRD11, Extended VRD10, and the AMD K8 Rev F
VID codes. The SEL input allows the user to select the
architecture specifications.
Clock Frequency (OSC)
An external resistor, ROSC, from OSC to GND sets the
internal clock frequency of the MAX8809A/MAX8810A.
A 1% resistor is recommended to maintain good frequency accuracy. The internal clock frequency sets the
per-phase switching frequency. The selection of switching frequency per phase is influenced by factors such
as the switching speed of the MOSFETs, the inductor’s
core material, different types of input and output capacitors, and the available board space. Once the perphase switching frequency is selected, the internal
clock frequency is determined using the procedure in
the Setting the Switching Frequency section.
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Output Current Sensing (CS_+, CS_-)
The output current of each phase is sensed differentially.
A low-offset-voltage, differential-current amplifier
(30V/V) at each phase allows low-resistance currentsense resistors to be used to minimize power dissipation. Sensing the current at the output of each phase
offers advantages including less noise sensitivity, more
accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC
resistance of the output inductor.
Using the DC resistance, RDC, of the output inductor
(Figure 3) allows higher efficiency. In this configuration,
the initial tolerance and temperature coefficient of RDC
must be accounted for in the output-voltage droop-error
budget. The temperature coefficient can be compensated; see the Load-Line Independent Inductor DC
Resistance Temperature Compensation section for more
details. An RC-filtering network is needed to extract the
current information from the output inductor. The time
constant of the RC network is calculated as follows:
R1 × C1 =
L
RDC
where L is the inductance of the output inductor. For
20A or higher current-per-phase applications, the DC
resistance of commercially available inductors is
approximately 1mΩ. To minimize current-sense error
due to the bias current at the current-sense inputs,
choose R1 less than 2kΩ. Determine the value for C1 as:
RDC
L
R1
VRDC = RDC x IOUT
IOUT
C1 =
L
R
( DC × R1)
Select a 1% resistor for R1. For mainstream PCs 20%
tolerance is recommended for C1, and for performance
PCs 10% tolerance should be considered. If using an
inductor with RDC greater than 1mΩ, a resistor (R2)
may be necessary to divide down the voltage across
CS_+ and CS_-. The maximum average signal present
at the input of the current-sense amplifier should not
exceed 85mV.
When a current-sense resistor is used for more accurate current sharing and load-line, a similar RC-filtering
circuit is recommended to cancel the equivalent series
inductance of the current-sense resistor, as shown in
Figure 4. Again, select R2 less than 2kΩ, and C2 is
determined by the following equation:
ESL
C2 =
(RS × R2)
where ESL is the equivalent series inductance of the
current-sense resistor and RS is the value of the current-sense resistor. For example, a 1mΩ, 2025 package sense resistor has an ESL of 1.6nH. If using an RS
greater than 1mΩ, a resistor (R2) may be necessary to
divide down the voltage across CS_+ and CS_-. The
maximum average signal present at the input of the
current-sense amplifier should not exceed 85mV.
Output Current Limit and Short-Circuit
Protection (ILIM)
The MAX8809A/MAX8810A feature a precise average
output current limit on a cycle-by-cycle basis using
Maxim’s proprietary RA2 technology. The current-limit
scheme is insensitive to input-voltage variation, the
inductor tolerance, and the tolerance of the currentsense capacitor, permitting the use of low-cost components to reduce total BOM cost. Furthermore, the
current limit is fully temperature compensated resulting
L
ESL
R2
C1
RS
VS = RS x IOUT
RDC IS THE INDUCTOR DC RESISTANCE
Figure 3. Inductor RDC Current Sense
C2
R2
OPTIONAL
R2
OPTIONAL
CS_+
IOUT
CS_-
CS_+
CS_-
ESL IS THE PARASITIC INDUCTANCE OF THE CURRENT-SENSE RESISTOR
Figure 4. Resistor Current Sense
______________________________________________________________________________________
19
MAX8809A/MAX8810A
Voltage Reference (REF)
A precision 2V reference is provided by the MAX8809A/
MAX8810A at the REF output. REF is capable of sinking
and sourcing up to 500µA for external loads. Connect a
0.1µF to 1µF ceramic capacitor from REF to GND.
Internal REFOK circuitry monitors the reference voltage.
The reference voltage must be above the REFOK threshold of 1.84V to activate the controller. The controller is
disabled if the reference voltage falls below 1.74V.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
in a constant output current limit over the entire operational temperature range. This eliminates the need to
oversize MOSFETs and inductors to compensate for
thermal effects. Connecting ILIM to VCC programs the
default current-limit threshold. To select a different current-limit threshold, connect a resistor-divider from REF
to GND with ILIM connected to the center tap. The voltage at ILIM is proportional to the current-limit threshold.
See the Setting the Current-Limit section for more details.
The current-limit circuitry terminates the DH_ on-time
immediately when the current-sense voltage (VCS_+ VCS_-) exceeds the current-limit threshold, allowing the
output inductor current to ramp down. At the next
switching cycle, the PWM pulse is skipped if the output
inductor current is still above the current-limit threshold.
Otherwise, the new cycle initiates as normal.
The MAX8809A/MAX8810A offer foldback-current protection under soft-start and overload conditions. This
feature allows the VRM to safely operate under shortcircuit conditions and to automatically recover once the
short-circuit condition is removed. If the output voltage
falls below the VRREADY threshold during an overcurrent event, the foldback current-limit circuitry sets the
current-limit threshold to half the user-selected value.
Output Differential Sensing (RS+, RS-)
The MAX8809A/MAX8810A feature differential outputvoltage sensing to achieve the highest possible output
accuracy. This allows the controllers to sense the actual voltage at the load, so the controller can compensate
for losses in the power output and ground lines. Traces
from the load point back to RS+ and RS- should be
routed close to each other and as far away as possible
from noise sources (such as inductors and high di/dt
traces). Use a ground plane to shield the remote-sense
traces from noise sources. To filter out common-mode
noise, RC filtering is recommended for these inputs as
shown in Figure 5. For VRD applications, a 100Ω resistor with a 1nF capacitor should be used. For VRM
applications, additional 50Ω resistors should be connected from these inputs to the local outputs of the
converter before the VRM connector. This avoids
excessive voltage at the CPU in case the remote-sense
connections get disconnected.
Programming the Output-Voltage Droop
Both the MAX8809A and MAX8810A employ peak-current-mode control with finite gain to actively set the output-voltage droop. Figure 6 shows the simplified control
block diagram. The relationship between the output
inductor current in an N-phase DC-DC converter and
the output voltage of the voltage-error amplifier is:
I
VC = OUT × RSENSE × GCA
N
where GCA (30V/V typ) is the gain of the differential current amplifier and N is the number of phases. IOUT is the
total output current. Therefore, when the output current
increases, VC increases. On the other hand, VC is related to the output voltage of the converter by the following
equation:
VC = gMV × RCOMP × ( VDAC − VOUT )
where gMV is the transconductance of the voltage-error
amplifier (2mS typ) and VDAC is the VID-generated voltage.
TO POSITIVE OUTPUT
OF VRM
R1
50Ω
RSENSE
IL_PEAK
GCA
R3
100Ω
RS+
TO REMOTE SENSE
LOCATION
R4
100Ω
RS-
R2
50Ω
C1
1nF
MAX8809A/
MAX8810A
TO POWER GROUND
OF VRM
Figure 5. Recommended Filtering for Output-Voltage Remote
Sensing
20
VOUT
C2
1nF
Vi
gMV
VOLTAGEERROR AMPLIFIER
VC
PWM
COMPARATOR
RCOMP
VDAC
Figure 6. Simplified Peak Current-Mode Control IC with Active
Output-Voltage Positioning
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
RDROOP =
(VDAC
RA2 ALGORITHM
RSENSE x (IOUT / N)
− VOUT )
gMA
RSENSE x (IOUT / N)
gMB
VC
GCA
IOUT
then RDROOP can be expressed as:
RDROOP =
RSENSE × GCA
N × gMV × RCOMP
Since GCA and gMV are constants, RDROOP is solely
determined by RCOMP when RSENSE and N are chosen.
Peak current-mode control with finite gain is the simplest way to achieve the output-voltage droop without
introducing a separate current loop, which is the case
for voltage-mode control. Therefore, the response time
of the output-voltage droop is the same as the voltagefeedback loop, resulting in fast output-voltage-droop
transient response and less output capacitance than
solutions using voltage-mode control.
Other features offered by peak-current-mode control
are excellent line regulation and inherent current sharing between phases. Standard peak-current-mode control does have one disadvantage in that current
matching between phases is impacted by the inductor
mismatch (tolerance) between phases. Because only
the current peak is controlled, any mismatch in the
inductor value between two phases creates an inductor
ripple current mismatch, which, in turn, creates a DC
current mismatch between those two phases.
Tolerance mismatch between the current-sense capacitors used in DCR current sensing creates the exact
same DC current mismatch as an inductor mismatch.
Maxim’s proprietary RA 2 technology addresses this
issue by averaging out the inductor ripple current individually at each phase, as shown in Figure 7. The rapid
active average circuitry learns the peak-to-peak ripple
current of each phase in 5 to 10 switching cycles and
then biases the peak current signal down by half of the
peak-to-peak ripple current, consequently eliminating
the impact of both output inductance and DCR currentsense capacitance variations. Since the rapid active
1/S
VOUT
VC
PWM
COMPARATOR
gMV
VOLTAGEERROR AMPLIFIER
RCOMP
VDAC
Figure 7. Implementation of the Rapid Active Averaging (RA2)
Algorithm
average circuitry is not part of the current-loop path, it
does not slow down the transient response.
Programming the Output Offset Voltage
According to the Intel VRD specifications, the output
voltage at no load cannot exceed the voltage specified
by the VID code, including the initial set tolerance, ripple voltage, and other errors. Therefore, the actual output voltage should be biased lower to compensate for
these errors. For the MAX8809A, the output-voltage offset is created through a resistor-divider that is connected between REF and GND, with the center tap
connected to COMP as shown in Figure 8. This resistordivider also sets the output load-line. The MAX8810A
contains a BUF output that makes the output-voltage
offset setting independent of the output load-line. To
program the output-voltage offset, connect a resistor
between COMP and GND. A resistor between BUF and
COMP sets the output load-line. See the Loop
Compensation Design section for details on setting the
output-voltage offset.
______________________________________________________________________________________
21
MAX8809A/MAX8810A
The DC gain of the voltage-error amplifier is equal to
gMV x RCOMP. From the previous equations it is clear
that the output-voltage droop can be accurately programmed if the DC gain of the voltage-error amplifier is
set to be a finite value. As the output current increases,
V C increases and, consequently, V OUT decreases.
Define the output-droop resistance, RDROOP, as:
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A
MAX8810A
REF
RLL
BUF
RLL
COMP
ROS
COMP
ROS
Figure 8. Programming the Output Offset Voltage
Load-Line Independent Inductor DC
Resistance Temperature Compensation
Changes in inductor resistance due to temperature
cause a change in the output-droop characteristic. This
is compensated by changing the gain of the currentsense amplifier as a function of temperature. In doing
so, the voltage at COMP is independent of temperature,
resulting in a temperature-independent load-line setting.
Additionally, the output short-circuit protection is also
temperature independent because current limit is implemented by clamping the voltage at COMP. This technology uses an NTC thermistor solely for temperature
compensation, freeing it from being one of the components that determines the output load-line. Therefore,
only one NTC thermistor is needed to enable any output
load-line. The same NTC thermistor is used for temperature sense for the VRHOT output. The MAX8809A/
MAX8810A temperature-compensation scheme is optimized for use with a Panasonic ERTJ1VR103 10kΩ NTC
thermistor. Other thermistors may be used. Contact your
local Maxim representative for more details.
Loop Compensation
During a load transient, the output voltage instantly
changes due to the ESR of the output capacitors by an
amount equal to their ESR times the change in load current (ΔVOUT = RESR x ΔILOAD). The output voltage then
deviates further based on the speed at which the loop
compensates for the load transient. The voltage-positioning method allows better utilization of the output regulation window, resulting in less required output
capacitors. The RA2 architecture adjusts the output current based on the instantaneous output voltage, resulting in fast voltage positioning. The voltage-error
amplifier consists of a high-bandwidth, high-accuracy
transconductance amplifier (gMV in Figure 7). The nega22
tive input of the transconductance amplifier is connected
to the output of the remote-voltage differential amplifier,
and the positive input is connected to the output of an
internal DAC controlled by the VID inputs. The DC gain
of the transconductance amplifier is set to a finite value
to achieve fast output-voltage positioning by connecting
an RC circuit (RCOMP and CCOMP) from COMP to GND.
See the Loop-Compensation Design section for details
on selecting the required components.
VR Ready Output (VRREADY)
VRREADY is an open-drain output that turns high
impedance when the output voltage reaches regulation. VRREADY goes low if VOUT is less than (VDAC 225mV) or greater than (VDAC + 175mV), signaling an
out-of-regulation fault. VRREADY is held low in shutdown, if VCC is less than the UVLO threshold, or during
soft-start. For logic-level output voltages, connect an
external pullup resistor between VRREADY and the
logic power supply. A 100kΩ resistor works well in most
applications.
Dynamic VID Change
The MAX8809A/MAX8810A provide the ability for the
CPU to dynamically change the VID inputs while the
controller is operating (on-the-fly or OTF). The output
voltage changes in 6.25mV steps (Intel) or
12.5mV/25mV steps (AMD) when a VID change is
detected.
The controller provides a 400ns logic-skew window to
prevent false code changes. The controller accepts
both step-by-step changes of VID inputs or all-at-once
VID input changes. For all-at-once VID input changes,
the output-voltage slew rate is the same, 1 LSB per
step and 2µs duration. VRREADY is blanked during
dynamic VID changes.
Multiphase Operation Selection
The MAX8809A operates in either a 2- or 3-phase configuration. Connect PWM3 to VCC for 2-phase operation.
The MAX8810A operates in 2-, 3- or 4-phase configuration. Connect PWM4 to V CC for 3-phase operation.
Connect PWM4 and PWM3 to VCC for 2-phase operation.
All active PWM outputs are held low during shutdown.
UVLO and Output Enable
When the IC supply voltage (V CC ) is less than the
UVLO threshold (4.25V typ), all active PWM outputs are
internally pulled low and most internal circuitry is shut
down to reduce the quiescent current. When EN is
released and VCC > UVLO, the internal 100kΩ resistor
pulls EN to VCC and soft-start is initiated (after a typical
2.2ms delay).
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
start time of 500µs to 6.5ms. For Intel designs, the
resistor value is calculated as:
Soft-Start
where tSS is the desired soft-start time (in ms) to the
1.1V V BOOT level. Figure 9 shows the Intel startup
sequence, and Table 1 shows the values of the time
delays.
For AMD applications, the controllers soft-start up to the
voltage set by the VID inputs. The soft-start time is set
by the following equation:
RSS / OVP (kΩ) =
The MAX8809A/MAX8810A soft-start with 6.25mV
steps, regardless of processor architecture. Connect a
resistor between SS/OVP and GND to program the softstart time. When the device is enabled, SS/OVP is driven to 2V and the current drawn by the set resistor is
measured. This current sets the internal delay time
between the DAC voltage steps. Select a resistor
between 12kΩ and 90.9kΩ for a corresponding soft-
RSS / OVP (kΩ) =
Table 1. Intel Startup Sequence
Specifications
PARAMETER
MIN
TD1
1ms
5ms
TD2
50µs
5ms
TD3
50µs
3ms
TD4
—
2.5ms
TD5
50µs
3ms
Soft-Stop
When EN goes low, the output of the converter ramps
down to 0V in 6.25mV DAC steps in the time set by the
SS/OVP input. Once the output reaches 0V, DL is held
high and DH is held low to maintain the 0V output. This
NORMAL
OPERATION
6.25mV/2μs
SOFT-START RATE
SET BY RSS/OVP
VBOOT
OUT
SOFT-STOP
RATE SET BY RSS/OVP
VID CODE
CHANGE
STEP TO
VID CODE
6.25mV/2μs
6.25mV/STEP
t ss − 0.0183
1.1V
×
0.0532
VDAC
where VDAC is the output voltage set by the VID inputs.
Figure 10 shows the AMD startup sequence, and Table 2
shows the values of the time delays.
MAX
VID
INPUT
READ
tss − 0.0183
0.0532
6.25mV/STEP
VRREADY
TD1
TD2
TD5
TD3
TD4
EN
(SS TIME)
NO. OF STEPS x 2μs
Figure 9. Intel VRD11/VRD10 Startup Sequence
______________________________________________________________________________________
23
MAX8809A/MAX8810A
When the driver supply voltage (VVL_) is less than its
UVLO threshold (3.55V typ), DH_ and DL_ are held low.
If VVL_ is above the UVLO threshold and while EN is low,
DL_ is driven high and DH_ is held low. This prevents
the output of the converter from rising before a valid EN
high signal is present.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
SOFT-START RATE
SET BY RSS/OVP
SOFT-STOP
RATE SET BY RSS/OVP
ABOVE 0.775V
25mV/4μs
VID INPUT
CHANGE
VID CODE
LEVEL
BELOW 0.775V
12.5mV/2μs
6.25mV/STEP
OUT
6.25mV/STEP
VRREADY
EN
2ms
TD1
TD2
TD3
1.1ms
TD4
SS TIME
Figure 10. K8 Rev F Startup Sequencing and Timing
Table 2. AMD Startup Sequence
Specifications
PARAMETER
MINIMUM TIME
(µs)
Integrated Dual-MOSFET Driver
MAXIMUM TIME
(ms)
TD1
1
—
TD2*
500
6.5
TD3
—
20
TD4
—
500
*User programmable.
approach prevents large negative voltages on the output during shutdown and therefore eliminates the need
for a Schottky clamp diode on the output.
Output Overvoltage Protection (OVP)
When the output voltage exceeds the regulation voltage
by 200mV (Intel) or exceeds 1.8V (AMD), all active PWM
outputs are pulled low and the controller is latched off.
SS/OVP is internally pulled to VCC to signal an overvoltage fault. All DH_ outputs are held low and all DL_ outputs are held high to discharge the output. The latch
condition can only be cleared by cycling the input voltage (VCC).
24
The MAX8809A/MAX8810A contain a dual-phase gate
driver capable of driving 3000pF capacitive loads with
only 32ns propagation delay and 11ns typical rise and fall
times, allowing operation up to 1.2MHz per phase.
Adaptive dead time controls low-side MOSFET turn-on
and high-side MOSFET turn-on. This maximizes converter
efficiency, while allowing operation with a variety of
MOSFETs. A UVLO circuit ensures proper power-on
sequencing.
Adaptive Shoot-Through Protection
Adaptive shoot-through protection is incorporated for
the switching transition after the high-side MOSFET is
turned off and before the low-side MOSFET is turned
on. The low-side driver is turned on only when the LX_
voltage falls below 2.5V typical. In addition, a fixed
35ns delay time between the low-side MOSFET turn-off
and high-side MOSFET turn-on adds further protection
from “shoot-through.” The 35ns time begins after DL_
has fallen through 1.5V typical.
MOSFET Driver UVLO
When VVL12 (MAX8809A) or VVL1 (MAX8810A) is below
the UVLO threshold (3.55 typ), DH_ and DL_ are held
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
monitor an active-high, open-drain VRHOT output.
Connect a resistor from VRTSET to GND to set the temperature-monitoring threshold. The resistor is calculated as follows:
Boost Circuit for High-Side MOSFET Driver
RVRTSET =
800
in kΩ
0.6K T
The gate-drive voltage for the high-side MOSFET drivers is generated by a flying-capacitor boost circuit.
The capacitor between BST_ and LX_ is charged from
the VL_ supply through an internal switch while the lowside MOSFET is on. When the low-side MOSFET is
switched off, the stored voltage on the capacitor is
stacked above LX_ to provide the necessary turn-on
voltage for the high-side MOSFET(s). No external boost
diode is needed. See the Boost Capacitor Selection
section for details on selecting the correct capacitor.
where KT is a temperature scale factor specifically for
the Panasonic ERTJ1VR103 NTC thermistor. Table 3
provides values of K T and the closest standard 1%
RVRTSET values needed to program the VRHOT threshold over a +60°C to +125°C range. RVRTSET must be
greater than 20kΩ. Contact your local Maxim representative for information on using other thermistors.
Thermal Protection
Architecture Selection and Timing
The MAX8809A/MAX8810A feature a thermal-fault-protection circuit. When the junction temperature rises
above +160°C typical, an internal thermal sensor activates the shutdown circuit to hold all MOSFET drivers
and active PWM outputs low to disable switching. The
thermal sensor reactivates the controller after the junction temperature cools by 25°C typical.
AMD K8 Rev F
The AMD K8 Rev F processor uses a 6-bit VID code
that specifies a 0.375V to 1.55V output voltage range
(see Table 4). Leave SEL unconnected to select the
AMD K8 Rev F architecture. The startup sequencing
and timing specifications are shown in Figure 10. Note
that the VID input defines the AMD processor boot
level, and there is no internal default. The boot level is
not latched; therefore, if the codes change during softstart, the boot level also changes.
Temperature Monitoring (VRTSET, VRHOT)
The MAX8809A/MAX8810A contain temperature-monitoring circuitry that allows the user to program a temperature trip point between +60°C and +125°C, and
Table 3. Temperature Scale Factor
TEMPERATURE (°C)
KT
RVRTSET (kΩ)
+60
4.497
294
+65
5.453
243
+70
6.580
200
+75
7.903
169
+80
9.447
140
+85
11.244
118
+90
13.325
100
+95
15.725
84.5
+100
18.484
71.5
+105
21.643
61.9
+110
25.247
52.3
+115
29.345
45.3
+120
33.988
39.2
+125
39.231
34
Extended Intel VRD10
The Intel VRD10 processor uses a 7-bit VID code that
specifies a 0.83125V to 1.6V output voltage range (see
Table 5). Connect SEL to GND to select the VRD10
architecture. The startup sequencing and timing specifications are shown in Figure 9. The Intel boot level is
internally set to 1.1V; therefore, the VID inputs are
ignored during soft-start. In compliance with the Intel
VRD specifications, there is a typical 2.2ms delay after
EN is asserted before soft-start begins. This delay is
not included in the soft-start time set by SS/OVP.
Intel VRD11
The Intel VRD11 processor uses an 8-bit VID code that
specifies a 0.3125V to 1.6V output voltage range (see
Table 6). Connect SEL to VCC to select the VRD11
architecture. The startup sequencing and timing specifications are shown in Figure 9. The Intel boot level is
internally set to 1.1V; therefore, the VID inputs are
ignored during soft-start. In compliance with the Intel
VRD specifications, there is a typical 2.2ms delay after
EN is asserted before soft-start begins. This delay is
not included in the soft-start time set by SS/OVP.
______________________________________________________________________________________
25
MAX8809A/MAX8810A
low. Once VVL_ is above the UVLO threshold and EN is
low, DL_ is kept high and DH_ is kept low. This prevents the output from rising before a valid EN signal
is given.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 4. AMD K8 Rev F VID Code, SEL = UNCONNECTED
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
1
1
1
1
1
1
0.3750
0
1
1
1
1
1
0.7750
1
1
1
1
1
0
0.3875
0
1
1
1
1
0
0.8000
1
1
1
1
0
1
0.4000
0
1
1
1
0
1
0.8250
1
1
1
1
0
0
0.4125
0
1
1
1
0
0
0.8500
1
1
1
0
1
1
0.4250
0
1
1
0
1
1
0.8750
1
1
1
0
1
0
0.4375
0
1
1
0
1
0
0.9000
1
1
1
0
0
1
0.4500
0
1
1
0
0
1
0.9250
1
1
1
0
0
0
0.4625
0
1
1
0
0
0
0.9500
1
1
0
1
1
1
0.4750
0
1
0
1
1
1
0.9750
1
1
0
1
1
0
0.4875
0
1
0
1
1
0
1.0000
1
1
0
1
0
1
0.5000
0
1
0
1
0
1
1.0250
1
1
0
1
0
0
0.5125
0
1
0
1
0
0
1.0500
1
1
0
0
1
1
0.5250
0
1
0
0
1
1
1.0750
1
1
0
0
1
0
0.5375
0
1
0
0
1
0
1.1000
1
1
0
0
0
1
0.5500
0
1
0
0
0
1
1.1250
1
1
0
0
0
0
0.5625
0
1
0
0
0
0
1.1500
1
0
1
1
1
1
0.5750
0
0
1
1
1
1
1.1750
1
0
1
1
1
0
0.5875
0
0
1
1
1
0
1.2000
1
0
1
1
0
1
0.6000
0
0
1
1
0
1
1.2250
1
0
1
1
0
0
0.6125
0
0
1
1
0
0
1.2500
1
0
1
0
1
1
0.6250
0
0
1
0
1
1
1.2750
1
0
1
0
1
0
0.6375
0
0
1
0
1
0
1.3000
1
0
1
0
0
1
0.6500
0
0
1
0
0
1
1.3250
1
0
1
0
0
0
0.6625
0
0
1
0
0
0
1.3500
1
0
0
1
1
1
0.6750
0
0
0
1
1
1
1.3750
1
0
0
1
1
0
0.6875
0
0
0
1
1
0
1.4000
1
0
0
1
0
1
0.7000
0
0
0
1
0
1
1.4250
1
0
0
1
0
0
0.7125
0
0
0
1
0
0
1.4500
1
0
0
0
1
1
0.7250
0
0
0
0
1
1
1.4750
1
0
0
0
1
0
0.7375
0
0
0
0
1
0
1.5000
1
0
0
0
0
1
0.7500
0
0
0
0
0
1
1.5250
1
0
0
0
0
0
0.7625
0
0
0
0
0
0
1.5500
Note: VID voltage increment is 12.5mV from 0.3875 to 0.775 and 25mV from 0.775 to 1.550.
26
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
1
1
0
1
0
1
0
1.60000
1
1
1
0
0
1
0
1.40000
0
1
0
1
0
1
0
1.59375
0
1
1
0
0
1
0
1.39375
1
0
0
1
0
1
1
1.58750
1
0
1
0
0
1
1
1.38750
0
0
0
1
0
1
1
1.58125
0
0
1
0
0
1
1
1.38125
1
1
0
1
0
1
1
1.57500
1
1
1
0
0
1
1
1.37500
0
1
0
1
0
1
1
1.56875
0
1
1
0
0
1
1
1.36875
1
0
0
1
1
0
0
1.56250
1
0
1
0
1
0
0
1.36250
0
0
0
1
1
0
0
1.55625
0
0
1
0
1
0
0
1.35625
1
1
0
1
1
0
0
1.55000
1
1
1
0
1
0
0
1.35000
0
1
0
1
1
0
0
1.54375
0
1
1
0
1
0
0
1.34375
1
0
0
1
1
0
1
1.53750
1
0
1
0
1
0
1
1.33750
0
0
0
1
1
0
1
1.53125
0
0
1
0
1
0
1
1.33125
1
1
0
1
1
0
1
1.52500
1
1
1
0
1
0
1
1.32500
0
1
0
1
1
0
1
1.51875
0
1
1
0
1
0
1
1.31875
0
1
0
1
1
0
1.31250
1
0
0
1
1
1
0
1.51250
1
0
0
0
1
1
1
0
1.50625
0
0
1
0
1
1
0
1.30625
1
1
0
1
1
1
0
1.50000
1
1
1
0
1
1
0
1.30000
1
1
0
1
1
0
1.29375
0
1
0
1
1
1
0
1.49375
0
1
0
0
1
1
1
1
1.48750
1
0
1
0
1
1
1
1.28750
0
0
0
1
1
1
1
1.48125
0
0
1
0
1
1
1
1.28125
1
1
0
1
1
1
1.27500
1
1
0
1
1
1
1
1.47500
1
0
1
0
1
1
1
1
1.46875
0
1
1
0
1
1
1
1.26875
1
0
1
0
0
0
0
1.46250
1
0
1
1
0
0
0
1.26250
0
1
1
0
0
0
1.25625
0
0
1
0
0
0
0
1.45625
0
1
1
1
0
0
0
0
1.45000
1
1
1
1
0
0
0
1.25000
0
1
1
0
0
0
0
1.44375
0
1
1
1
0
0
0
1.24375
1
0
1
0
0
0
1
1.43750
1
0
1
1
0
0
1
1.23750
0
0
1
0
0
0
1
1.43125
0
0
1
1
0
0
1
1.23125
1
1
1
0
0
0
1
1.42500
1
1
1
1
0
0
1
1.22500
0
1
1
0
0
0
1
1.41875
0
1
1
1
0
0
1
1.21875
1
0
1
0
0
1
0
1.41250
1
0
1
1
0
1
0
1.21250
0
0
1
0
0
1
0
1.40625
0
0
1
1
0
1
0
1.20625
______________________________________________________________________________________
27
MAX8809A/MAX8810A
Table 5. Extended Intel VRD10 VID Code, SEL = GND
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 5. Extended Intel VRD10 VID Code, SEL = GND (continued)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
1
1
1
1
0
1
0
1.20000
1
1
0
0
0
1
0
1.02500
0
1
1
1
0
1
0
1.19375
0
1
0
0
0
1
0
1.01875
1
0
1
1
0
1
1
1.18750
1
0
0
0
0
1
1
1.01250
0
0
1
1
0
1
1
1.18125
0
0
0
0
0
1
1
1.00625
1
1
1
1
0
1
1
1.17500
1
1
0
0
0
1
1
1.00000
0
1
1
1
0
1
1
1.16875
0
1
0
0
0
1
1
0.99375
1
0
1
1
1
0
0
1.16250
1
0
0
0
1
0
0
0.98750
0
0
1
1
1
0
0
1.15625
0
0
0
0
1
0
0
0.98125
1
1
1
1
1
0
0
1.15000
1
1
0
0
1
0
0
0.97500
0
1
1
1
1
0
0
1.14375
0
1
0
0
1
0
0
0.96875
1
0
1
1
1
0
1
1.13750
1
0
0
0
1
0
1
0.96250
0
0
1
1
1
0
1
1.13125
0
0
0
0
1
0
1
0.95625
1
1
1
1
1
0
1
1.12500
1
1
0
0
1
0
1
0.95000
0
1
1
1
1
0
1
1.11875
0
1
0
0
1
0
1
0.94375
1
0
1
1
1
1
0
1.11250
1
0
0
0
1
1
0
0.93750
0
0
1
1
1
1
0
1.10625
0
0
0
0
1
1
0
0.93125
1
1
1
1
1
1
0
1.10000
1
1
0
0
1
1
0
0.92500
0
1
1
1
1
1
0
1.09375
0
1
0
0
1
1
0
0.91875
1
0
1
1
1
1
1
OFF
1
0
0
0
1
1
1
0.91250
0
0
1
1
1
1
1
OFF
0
0
0
0
1
1
1
0.90625
1
1
1
1
1
1
1
OFF
1
1
0
0
1
1
1
0.90000
0
1
1
1
1
1
1
OFF
0
1
0
0
1
1
1
0.89375
1
0
0
0
0
0
0
1.08750
1
0
0
1
0
0
0
0.88750
0
0
0
0
0
0
0
1.08125
0
0
0
1
0
0
0
0.88125
1
1
0
0
0
0
0
1.07500
1
1
0
1
0
0
0
0.87500
0
1
0
0
0
0
0
1.06875
0
1
0
1
0
0
0
0.86875
1
0
0
0
0
0
1
1.06250
1
0
0
1
0
0
1
0.86250
0
0
0
0
0
0
1
1.05625
0
0
0
1
0
0
1
0.85625
1
1
0
0
0
0
1
1.05000
1
1
0
1
0
0
1
0.85000
0
1
0
0
0
0
1
1.04375
0
1
0
1
0
0
1
0.84375
1
0
0
0
0
1
0
1.03750
1
0
0
1
0
1
0
0.83750
0
0
0
0
0
1
0
1.03125
0
0
0
1
0
1
0
0.83125
28
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0
1.60000
0
0
0
0
0
0
1
1
1.59375
0
0
0
0
0
1
0
0
1.58750
0
0
0
0
0
1
0
1
1.58125
0
0
0
0
0
1
1
0
1.57500
0
0
0
0
0
1
1
1
1.56875
0
0
0
0
1
0
0
0
1.56250
0
0
0
0
1
0
0
1
1.55625
0
0
0
0
1
0
1
0
1.55000
0
0
0
0
1
0
1
1
1.54375
0
0
0
0
1
1
0
0
1.53750
0
0
0
0
1
1
0
1
1.53125
0
0
0
0
1
1
1
0
1.52500
0
0
0
0
1
1
1
1
1.51875
0
0
0
1
0
0
0
0
1.51250
0
0
0
1
0
0
0
1
1.50625
0
0
0
1
0
0
1
0
1.50000
0
0
0
1
0
0
1
1
1.49375
0
0
0
1
0
1
0
0
1.48750
0
0
0
1
0
1
0
1
1.48125
0
0
0
1
0
1
1
0
1.47500
0
0
0
1
0
1
1
1
1.46875
0
0
0
1
1
0
0
0
1.46250
0
0
0
1
1
0
0
1
1.45625
0
0
0
1
1
0
1
0
1.45000
0
0
0
1
1
0
1
1
1.44375
0
0
0
1
1
1
0
0
1.43750
0
0
0
1
1
1
0
1
1.43125
0
0
0
1
1
1
1
0
1.42500
0
0
0
1
1
1
1
1
1.41875
0
0
1
0
0
0
0
0
1.41250
0
0
1
0
0
0
0
1
1.40625
0
0
1
0
0
0
1
0
1.40000
0
0
1
0
0
0
1
1
1.39375
0
0
1
0
0
1
0
0
1.38750
0
0
1
0
0
1
0
1
1.38125
0
0
1
0
0
1
1
0
1.37500
0
0
1
0
0
1
1
1
1.36875
______________________________________________________________________________________
29
MAX8809A/MAX8810A
Table 6. Intel VRD11 VID Code, SEL = VCC
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 6. Intel VRD11 VID Code, SEL = VCC (continued)
30
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
0
0
1
0
1
0
0
0
1.36250
0
0
1
0
1
0
0
1
1.35625
0
0
1
0
1
0
1
0
1.35000
0
0
1
0
1
0
1
1
1.34375
0
0
1
0
1
1
0
0
1.33750
0
0
1
0
1
1
0
1
1.33125
0
0
1
0
1
1
1
0
1.32500
0
0
1
0
1
1
1
1
1.31875
0
0
1
1
0
0
0
0
1.31250
0
0
1
1
0
0
0
1
1.30625
0
0
1
1
0
0
1
0
1.30000
0
0
1
1
0
0
1
1
1.29375
0
0
1
1
0
1
0
0
1.28750
0
0
1
1
0
1
0
1
1.28125
0
0
1
1
0
1
1
0
1.27500
0
0
1
1
0
1
1
1
1.26875
0
0
1
1
1
0
0
0
1.26250
0
0
1
1
1
0
0
1
1.25625
0
0
1
1
1
0
1
0
1.25000
0
0
1
1
1
0
1
1
1.24375
0
0
1
1
1
1
0
0
1.23750
0
0
1
1
1
1
0
1
1.23125
0
0
1
1
1
1
1
0
1.22500
0
0
1
1
1
1
1
1
1.21875
0
1
0
0
0
0
0
0
1.21250
0
1
0
0
0
0
0
1
1.20625
0
1
0
0
0
0
1
0
1.20000
0
1
0
0
0
0
1
1
1.19375
0
1
0
0
0
1
0
0
1.18750
0
1
0
0
0
1
0
1
1.18125
0
1
0
0
0
1
1
0
1.17500
0
1
0
0
0
1
1
1
1.16875
0
1
0
0
1
0
0
0
1.16250
0
1
0
0
1
0
0
1
1.15625
0
1
0
0
1
0
1
0
1.15000
0
1
0
0
1
0
1
1
1.14375
0
1
0
0
1
1
0
0
1.13750
0
1
0
0
1
1
0
1
1.13125
0
1
0
0
1
1
1
0
1.12500
0
1
0
0
1
1
1
1
1.11875
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
0
1
0
1
0
0
0
0
1.11250
0
1
0
1
0
0
0
1
1.10625
0
1
0
1
0
0
1
0
1.10000
0
1
0
1
0
0
1
1
1.09375
0
1
0
1
0
1
0
0
1.08750
0
1
0
1
0
1
0
1
1.08125
0
1
0
1
0
1
1
0
1.07500
0
1
0
1
0
1
1
1
1.06875
0
1
0
1
1
0
0
0
1.06250
0
1
0
1
1
0
0
1
1.05625
0
1
0
1
1
0
1
0
1.05000
0
1
0
1
1
0
1
1
1.04375
0
1
0
1
1
1
0
0
1.03750
0
1
0
1
1
1
0
1
1.03125
0
1
0
1
1
1
1
0
1.02500
0
1
0
1
1
1
1
1
1.01875
0
1
1
0
0
0
0
0
1.01250
0
1
1
0
0
0
0
1
1.00625
0
1
1
0
0
0
1
0
1.00000
0
1
1
0
0
0
1
1
0.99375
0
1
1
0
0
1
0
0
0.98750
0
1
1
0
0
1
0
1
0.98125
0
1
1
0
0
1
1
0
0.97500
0
1
1
0
0
1
1
1
0.96875
0
1
1
0
1
0
0
0
0.96250
0
1
1
0
1
0
0
1
0.95625
0
1
1
0
1
0
1
0
0.95000
0
1
1
0
1
0
1
1
0.94375
0
1
1
0
1
1
0
0
0.93750
0
1
1
0
1
1
0
1
0.93125
0
1
1
0
1
1
1
0
0.92500
0
1
1
0
1
1
1
1
0.91875
0
1
1
1
0
0
0
0
0.91250
0
1
1
1
0
0
0
1
0.90625
0
1
1
1
0
0
1
0
0.90000
0
1
1
1
0
0
1
1
0.89375
0
1
1
1
0
1
0
0
0.88750
0
1
1
1
0
1
0
1
0.88125
0
1
1
1
0
1
1
0
0.87500
0
1
1
1
0
1
1
1
0.86875
______________________________________________________________________________________
31
MAX8809A/MAX8810A
Table 6. Intel VRD11 VID Code, SEL = VCC (continued)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 6. Intel VRD11 VID Code, SEL = VCC (continued)
32
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
0
1
1
1
1
0
0
0
0.86250
0
1
1
1
1
0
0
1
0.85625
0
1
1
1
1
0
1
0
0.85000
0
1
1
1
1
0
1
1
0.84375
0
1
1
1
1
1
0
0
0.83750
0
1
1
1
1
1
0
1
0.83125
0
1
1
1
1
1
1
0
0.82500
0
1
1
1
1
1
1
1
0.81875
1
0
0
0
0
0
0
0
0.81250
1
0
0
0
0
0
0
1
0.80625
1
0
0
0
0
0
1
0
0.80000
1
0
0
0
0
0
1
1
0.79375
1
0
0
0
0
1
0
0
0.78750
1
0
0
0
0
1
0
1
0.78125
1
0
0
0
0
1
1
0
0.77500
1
0
0
0
0
1
1
1
0.76875
1
0
0
0
1
0
0
0
0.76250
1
0
0
0
1
0
0
1
0.75625
1
0
0
0
1
0
1
0
0.75000
1
0
0
0
1
0
1
1
0.74375
1
0
0
0
1
1
0
0
0.73750
1
0
0
0
1
1
0
1
0.73125
1
0
0
0
1
1
1
0
0.72500
1
0
0
0
1
1
1
1
0.71875
1
0
0
1
0
0
0
0
0.71250
1
0
0
1
0
0
0
1
0.70625
1
0
0
1
0
0
1
0
0.70000
1
0
0
1
0
0
1
1
0.69375
1
0
0
1
0
1
0
0
0.68750
1
0
0
1
0
1
0
1
0.68125
1
0
0
1
0
1
1
0
0.67500
1
0
0
1
0
1
1
1
0.66875
1
0
0
1
1
0
0
0
0.66250
1
0
0
1
1
0
0
1
0.65625
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
1
1
0
0
0.63750
1
0
0
1
1
1
0
1
0.63125
1
0
0
1
1
1
1
0
0.62500
1
0
0
1
1
1
1
1
0.61875
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
1
0
1
0
0
0
0
0
0.61250
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
1
0
1
0
0
0
1
1
0.59375
1
0
1
0
0
1
0
0
0.58750
1
0
1
0
0
1
0
1
0.58125
1
0
1
0
0
1
1
0
0.57500
1
0
1
0
0
1
1
1
0.56875
1
0
1
0
1
0
0
0
0.56250
1
0
1
0
1
0
0
1
0.55625
1
0
1
0
1
0
1
0
0.55000
1
0
1
0
1
0
1
1
0.54375
1
0
1
0
1
1
0
0
0.53750
1
0
1
0
1
1
0
1
0.53125
1
0
1
0
1
1
1
0
0.52500
1
0
1
0
1
1
1
1
0.51875
1
0
1
1
0
0
0
0
0.51250
1
0
1
1
0
0
0
1
0.50625
1
0
1
1
0
0
1
0
0.50000
1
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
1
OFF
Design Procedure
The following sections detail the selection process for
the external components used with the MAX8809A/
MAX8810A. Contact your local Maxim representative to
obtain a spreadsheet-based tool to facilitate your
design.
Setting the Switching Frequency
The switching frequency influences the switching loss,
the size of the power MOSFETs, and the size of power
components such as output inductors and capacitors.
Higher switching frequencies result in smaller external
components and more compact designs. However,
power-MOSFET switching losses and magnetic core
losses in the output inductor increase with switching
frequency, reducing efficiency. Select a switching frequency as a tradeoff between size and efficiency.
Once the per-phase switching frequency is selected,
the internal oscillator frequency (fOSC) must be set.
Determine the required oscillator frequency based on
the desired per-phase switching frequency (fSW) from
Table 7.
Table 7. Required Clock Frequency for
Per-Phase Switching Frequency
NO. OF
PHASES
CONFIGURATION
fOSC
2
PWM3 = VCC (MAX8809A);
PWM3 = PWM4 = VCC (MAX8810A)
4 x fSW
3
PWM4 = VCC (MAX8810A)
3 x fSW
4
MAX8810A only
4 x fSW
For 2- or 4-phase designs, the internal clock frequency
should be set at four times the desired per-phase
switching frequency. In 3-phase designs, the internal
clock frequency should be set at three times the
desired per-phase switching frequency. Set the internal
clock frequency with a resistor from OSC to GND
(ROSC). The value of ROSC for a given internal clock
frequency is approximated from the following equation:
ROSC = 161.88 × fOSC −1.2074
______________________________________________________________________________________
33
MAX8809A/MAX8810A
Table 6. Intel VRD11 VID Code, SEL = VCC (continued)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
where fOSC is given in MHz and ROSC is in kΩ. Also
see the Per-Phase Frequency vs. ROSC graph in the
Typical Operating Characteristics for the relationship
between the clock frequency and the value of the frequency-setting resistor.
Output Inductor Selection
The output inductor is selected based on the desired
amount of inductor ripple current. A larger inductance
value minimizes output ripple current and increases
efficiency but slows down the output-inductor-current
slew rate during a load transient. LIR is the ratio of ripple current to the total current per phase. For the best
tradeoff of size, cost, and efficiency, an LIR of 30% to
60% is recommended (LIR = 0.3 to 0.6). Choose a
higher LIR when more phases are used to take advantage of ripple-current cancellation. The inductor value
is determined from:
VOUT × (1 − D) × N
L≥
LIR × fSW × IOUT _ MAX
where f SW is the per-phase switching frequency,
IOUT_MAX is the maximum-rated output current, D is the
duty ratio, N is the number of phases, and VOUT is the
output voltage at a given VID code. The output-inductor
ripple current produces a ripple voltage across the output-capacitor ESR that usually is the dominant component of the output voltage ripple. For an N-phase buck
converter with a D x N factor of less than 1, the output
ripple voltage, VRIPPLE, can be calculated using:
VRIPPLE =
VOUT × RESR _ CO × (1 − (D × N))
fSW × L
This equation takes into account the voltage ripple cancellation from multiphase designs. Optimum voltage
positioning (droop) requires the effective output-capacitor ESR to match the load resistance, RO. For initial ripple-voltage estimates, replace RESR_CO with RO. If the
output-ripple-voltage specification is not satisfied, a
larger value of output inductance should be chosen.
The selected inductor should have the lowest possible
DC resistance, and the saturation current should be
greater than the peak inductor current, IPEAK. IPEAK is
found from:
IOUT _ MAX
LIR ⎞
⎛
IPEAK =
× ⎜1 +
⎟
⎝
N
2 ⎠
When the DC resistance (RDC) of the output inductor is
used for current sensing, the DC resistance should be
a minimum of 0.5mΩ.
It is also important that the peak-to-peak ripple voltage at
the input of the current-sense amplifier not exceed 23mV:
34
(VCS+ - VCS-) = IRIPPLE x RSENSE
where R SENSE is the sense resistance value at the
highest operating temperature. If this condition is not
met, then the LIR must be adjusted or the input signal
to the current-sense amplifier must be scaled down
with a resistor-divider.
Output Capacitor Selection
In most cases, selection of the output capacitor is dictated by the target ESR requirement, RESR_CO = RO
(load resistance), to meet the core-supply transient
response. However, the minimum output capacitance,
CO(MIN) , required to meet load-dump requirements, is
estimated based on energy balance from:
L × ⎛⎝ IINIT 2 − IFIN2 ⎞⎠
1
CO(MIN) ≥
×
2
N × (VFIN − VINIT + VOV ) × VINIT
where IINIT and IFIN are the initial and final values of the
inductor current during a load dump, VINIT is the voltage prior to the load dump, VFIN is the voltage after,
and V OV is the allowed overshoot above V FIN . The
above equation is an approximation, and the outputcapacitance value obtained serves as a good starting
point. The final value should be obtained from actual
measurements.
There is also an upper limit on the amount of output
capacitance to meet the OTF VID change requirement.
Too much output capacitance can prevent the output
voltage from reaching the new VID output voltage within the OTF time window:
CO(MAX) ≤
(ILIM
)
− IOUT _ MAX × t OTF
ΔVOTF
where t OTF is the time window to achieve ΔV OTF
(change in output voltage). If C O(MAX) is less than
CO(MIN), the system does not meet the VID OTF specification. ILIM is usually set at 110% to 120% of IOUT_MAX.
RMS ripple current rating is an additional requirement
for the output capacitors. For a multiphase buck converter, the RMS ripple current in the output capacitors
is given by:
V
× (1 − N × D)
ICO _ RMS = OUT
2 3 × L × fSW
for (N x D) ≤ 1, where D is the duty cycle and is computed from the following equation:
D=
N × VOUT + IOUT _ MAX × (RDSON _ LS + RDC )
N × VIN − IOUT _ MAX × (RDSON _ HS − RDS _ LO )
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
when the low-side MOSFET is turned on. Therefore, the
decoupling capacitor for VL_ should be large enough
to minimize the ripple voltage during switching transitions. Choose CVL_ according to the following equation:
CVL _ = 10 × CBST _
Input Capacitor Selection
The input capacitor reduces the peak current drawn
from the power source and reduces the noise and voltage ripple on the input DC voltage bus caused by the
circuit’s switching. The input capacitors must meet the
ripple-current requirement (I RMS ) imposed by the
switching currents as defined by the following equation:
IRMS = D × IOUT _ MAX ×
1
− 1
N × D
for (D x N) ≤ 1
Use the minimum input voltage for calculating the duty
cycle to obtain the worst-case input-capacitor RMS ripple current. Low-ESR aluminum electrolytic, polymer, or
ceramic capacitors should be used to avoid large voltage transients at the input during a large step load
change at the output. The ripple-current specifications
provided by the manufacturer should be carefully
reviewed for temperature derating. Additional smallvalue, low-ESL ceramic capacitors (1µF to 10µF with
proper voltage rating) can be used in parallel to reduce
any high-frequency ringing.
Boost Capacitor Selection
The MAX8809A/MAX8810A use a bootstrap circuit to
generate the floating supply voltages for the high-side
drivers. The selected high-side MOSFET determines
the appropriate boost capacitance values according to
the following equation:
CBST =
QGATE _ HS × MHS
ΔVBST
where MHS is the total number of high-side MOSFETs
handled by each BST_ capacitor, QGATE_HS is the total
gate charge of each high-side MOSFET, and ΔVBST is
the voltage variation allowed on the high-side MOSFET
drive. Choose ΔVBST = 0.1V to 0.2V when determining
the CBST_ value. Use low-ESR ceramic capacitors for
CBST_. Note that QGATE_HS is a function of gate-drive
voltage VVL_ and should be obtained from the MOSFET
data sheet VGS vs. QGATE curve.
VL_ Bypass Capacitor Selection
VL_ provides the supply voltages for the low-side drivers. The decoupling capacitor at VL_ also charges the
high-side driver’s BST capacitor during the time period
Power-MOSFET Selection
MOSFET power dissipation depends on the gate-drive
voltage (VD), the on-resistance (RDSON), the total gate
charge (QGATE), and the gate threshold voltage (VTH).
The supply voltage (VL_) range for the MOSFET drivers
is from 4.5V to 7V. With V GATE < 10V, logic-level
threshold MOSFETs are recommended.
Power dissipation in the high-side MOSFET consists of
two parts: the conduction loss and the switching loss.
The per phase conduction loss for the high side can be
calculated from:
I2OUT _ MAX
RDSON _ HS
LIR2
PCOND _ HS = D ×
× (1 +
)×
2
12
MHS
N
where N is the number of phases and MHS is the number of MOSFETs in parallel for each phase. Total highside conduction loss equals the number of phases
times PCOND_HS.
Switching loss is the major contributor to the high-side
MOSFET power dissipation due to the hard switching
transition every time it turns on. The switching loss is
found from the following:
PSW _ HS =
2 × VIN × IOUT _ MAX
N
R
× QMILLER
× GATE
× fSW × MHS
VD − VTH
where VD is the gate-drive voltage and RGATE is the total
gate resistance including the driver’s on-resistance (see
the Electrical Characteristics table) and the MOSFET gate
resistance. For a logic-level power MOSFET, the gate
resistance is approximately 2Ω. QMILLER is the MOSFET
Miller charge found in the MOSFET data sheet.
Note that adding more MOSFETs in parallel on the high
side increases the switching loss. Smaller Miller gate
charge and lower gate resistance usually result in lower
switching loss.
The low-side MOSFET power dissipation is mostly
attributed to the conduction loss. Switching loss is negligible due to the zero-voltage switching at turn-on and
body-diode clamp at turn-off. Power dissipation in the
low-side MOSFETs of each phase can be calculated
from the following equation:
PCOND _ LS = (1 − D) ×
I2 OUT _ MAX
2
N
⎛
RDSON _ LS
LIR2 ⎞
× ⎜1 +
⎟×
12 ⎠
MLS
⎝
______________________________________________________________________________________
35
MAX8809A/MAX8810A
Use the maximum input voltage for calculating the duty
cycle to obtain the worst-case RMS ripple current.
RDSON_LS and RDSON_HS are the on-state resistances
of the low-side and high-side MOSFETs, respectively,
and RDC is the DC resistance of the output inductor.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
where MLS is the number of MOSFETs in parallel per
phase on the low side. Total power dissipation for the
low side equals the number of phases times the lowside conduction loss of each phase.
Even though the switching loss is insignificant in the
low-side MOSFETs, RDSON is not the only parameter
that should be considered in selecting the low-side
MOSFETs. Large Miller capacitance (CRSS) could turn
on the low-side MOSFETs momentarily when the drainto-source voltage goes high at fast slew rates, if the driver cannot hold the gate low. The ratio of CRSS/CISS
should be less than 1/10th for the low-side MOSFETs to
avoid shoot-through current due to momentary turn-on
of the low-side switch. Adding a resistor between BST_
and CBST_ can slow the high-side MOSFET turn-on.
Similarly, adding a capacitor from the gate to the
source of the high-side MOSFET has the same effect.
However, both methods are at the expense of increasing the high-side switching losses.
Loop-Compensation Design
Loop Compensation with Voltage Positioning
Processor power-supply specifications often require
the output voltage to “droop” from its no-load value at a
fixed slope with increasing load current. This slope is
termed the load-line resistance (RO). Once the currentsense resistance (RSENSE), the required load-line resistance, and the output offset voltage (V OS ) are
determined, the values of RLL and ROS (see Figure 8)
are calculated from the following equations:
For the MAX8809A:
RLL =
ROS =
⎞
gMV ⎛
N × RO
×⎜
− VOS ⎟
2
⎝ RSENSE × GCA
⎠
1
⎞
gMV ⎛
N × RO
1
×⎜
+ VOS ⎟ −
2
⎝ RSENSE × GCA
⎠ 20 × 106
ROS =
1
gMV × VOS
ROS × RCOMP
RLL =
ROS − RCOMP
R
× GCA
RCOMP = SENSE
N × gMV × RO
The pole due to the load (ROUT) and output capacitance produces a -20dB/decade slope up to the output36
CCOMP =
RESR _ CO × CO
RCOMP
where RESR_CO is the total equivalent series resistance
and CO is the total capacitance of the output capacitors.
Loop Compensation with Integral Feedback
For applications that do not implement droop, it is necessary to compensate the loop using integral feedback.
Looking at the transfer function from inductor current
iL(t) to output:
ω
1+
ϖ ZERO
GVI (ω ) = ROUT ×
ω
1+
ϖ POLE
The DC gain is the output impedance ROUT:
ROUT = VOUT / IOUT_MAX
A pole and zero are present due to the output capacitance (CO), output-capacitor ESR (RESR_CO), and the
load impedance (ROUT), as follows:
1
For the MAX8810A:
The 1V BUF output simplifies the ROS calculation considerably. ROS and RLL are calculated as:
where:
capacitor ESR zero frequency. To continue to roll off the
gain out to high frequencies at -20dB/decade, the compensation places a pole at the ESR zero frequency. An
RC circuit, RCOMP and CCOMP, must be connected
from COMP to ground. Calculate RCOMP as the parallel
combination of RLL and ROS. The capacitor value can
be found from the following equation once the output
capacitor ESR is known:
1
+ RESR _ CO ) × CO
Ω POLE =
(ROUT
Ω ZERO =
1
×
R
R
( OUT ESR _ CO )
and :
(ROUT
+ RESR _ CO )
× CO
The transfer function from control voltage vC(t) to inductor current iL(t) is:
gPWM =
iL ( t)
vC ( t )
=
1
RSENSE × GCA
where RSENSE is the resistance of the current-sense
element, and GCA is the current-sense amplifier gain.
The simplified control-to-output transfer function is then:
GCONTR _ OUTPUT (ω ) = gPWM × GVI (ω ) × N
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
where φMARGIN is the desired phase margin at crossover, and φCONTR_OUTPUT is the phase shift from controlto-output (at crossover).
MAX8809A/
MAX8810A
RCOMP
COMP
CCOMP1
The next step is to determine the constant K value in the
equation below, which provides the desired error-amplifier phase shift determined above. The value of K determines the locations of the error-amplifier zero and
high-frequency pole relative to the crossover frequency:
⎛
180
⎛ 1 ⎞⎞
φERROR _ AMPLIFIER = ⎜ arctan(K ) − arctan⎜ ⎟ ⎟ ×
+ 90
⎝ K ⎠⎠
π
⎝
2π × fCROSSOVER
K
ωPOLE _ ERROR _ AMPLIFIER = 2π × fCROSSOVER × K
ω ZERO _ ERROR _ AMPLIFIER =
The simplified compensator transfer function can be
modeled at low frequencies as:
⎛
⎞
1
gMV × ⎜ RCOMP +
ω × CCOMP1 ⎟⎠
⎝
where gMV is the transconductance of the error amplifier. At crossover, CCOMP1 is essentially a short and can
be ignored. The compensator must provide gain boost
to bring the loop gain to zero at crossover. Applying
these criteria and solving for RCOMP:
RCOMP =
1
gMV × | GCONTR _ OUTPUT (fCROSSOVER ) |
Solving for C COMP1 and C COMP2 is now relatively
straightforward:
CCOMP1 =
CCOMP2 =
•
1
ω ZERO _ ERROR _ AMPLIFIER × RCOMP
1
ωPOLE _ ERROR _ AMPLIFIER × RCOMP
Case 2: ωZERO < 2π x fCROSSOVER < ωPOLE-CM
where ωPOLE-CM is the frequency of the double pole
created by the sampling effect. This case is likely to
exist in situations where high-capacitance, high-ESR
output capacitors (e.g., low-cost aluminum electrolytic
such as 2800µF/12mΩ) are used.
Analysis of the control-to-output transfer function for this
case shows that 1) the slope is zero at crossover so the
compensation must roll off with a -1 slope, and 2) the
compensation must provide gain boost at the
crossover frequency to bring the loop gain to zero at
crossover. Both of these conditions are satisfied with
the following relationship:
CCOMP2
gMV ×
1
1
=
2π × fCROSSOVER × CCOMP
| GCONTR _ OUTPUT (fCROSSOVER ) |
Figure 11. Type II Compensation Scheme
______________________________________________________________________________________
37
MAX8809A/MAX8810A
This simplified transfer function ignores a double pole
due to the current-mode sampling effect, which can be
approximately placed at 1/2 the per-phase switching
frequency.
As a rule-of-thumb, the loop should be designed to
close between 1/5th and 1/10th of the per-phase
switching frequency. At this point, a determination
should be made as to which of the following cases
applies to the desired crossover frequency:
• Case 1: ωPOLE < 2π x fCROSSOVER < ωZERO
This case is likely to exist in situations where the zero
frequency (ωZERO) is relatively high due to use of lowvalue output capacitors with low ESR (e.g., 560µF/7mΩ
or all-ceramic designs).
Analysis of the control-to-output transfer function for
this case shows that 1) the slope is -1 at the crossover
frequency due to the low-frequency pole (ωPOLE), and
2) the compensation must provide gain boost at the
crossover frequency to bring the loop gain to zero at
crossover. Because of item 1), the compensator gain
must be flat at crossover so that the closed-loop gain
rolls off with -1 slope at crossover.
For this case, it is recommended to design the compensator with type II compensation. The zero is placed
to ensure flat gain at crossover, and the 2nd pole provides phase shift above crossover. The compensator
consists of a series resistor (RCOMP) and capacitor
(CCOMP1) from COMP to GND, and a second capacitor
(CCOMP2) placed from COMP to GND, in parallel to
RCOMP and CCOMP1 (see Figure 11).
The first step in the compensator design is to choose
the desired phase margin at crossover and solve for
the error-amplifier phase shift:
φERROR_AMPLIFIER = φMARGIN - φCONTR_OUTPUT
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
where gMV is the transconductance of the error amplifier and CCOMP is a capacitor placed from the output of
the error amplifier (COMP) to GND. Solving for CCOMP:
CCOMP = gMV x
BUF
| GCONTR _ OUTPUT (fCROSSOVER ) |
MAX8810A
2π × fCROSSOVER
RLL3
RLL2
RLL1
Multiload-Line Programming (MAX8810A)
In some applications, it may be desired to implement
multiple load-lines. This is easily accomplished by
switching resistors in parallel with RLL (Figure 12).
Paralleling resistors with RLL causes the load-line resistance to increase. With this scheme implemented for
the MAX8810A, the offset voltage is not affected by the
new load-line setting. It is also not necessary to change
the temperature compensation based on the new loadline setting. Switches S1 and S2 can be implemented
with small-signal n-channel MOSFETs.
RLL1 and ROS are designed using methods described
in the Loop-Compensation Design section. RO1, RO2,
and RO3 are the required load-line resistances. RLL2
and RLL3 are calculated as follows:
where:
and:
where:
RCOMP1 = RLL
R
×
RLL2 = COMP1
RCOMP1 −
R
RCOMP2 = O1 ×
RO2
R
RCOMP1 = LL1
RLL1
R
×
RLL3 = COMP2
RCOMP2 −
R
RCOMP3 = O2 ×
RO3
|| ROS
RCOMP2
RCOMP2
RCOMP1
× ROS
+ ROS
RCOMP3
RCOMP3
RCOMP2
COMP
ROS
Figure 12. Load-Line Switching Circuit
Setting the Current Limit
The current-limit threshold sets the maximum available
output DC current. The output current limit should be
selected to meet the OTF requirement as described in
the Output Capacitor Selection section. The voltage at
ILIM and the value of the current-sense resistor or the
DC resistance of the output inductor sets the currentlimit threshold:
I
VILIM = GCA × RSENSE × LIM
N
where RSENSE is the resistance of the current-sensing
element. The value of R SENSE at room temperature
must be used because the MAX8809A and MAX8810A
provide temperature-compensated current limit. VILIM
is set by connecting ILIM to the center tap of a resistordivider from REF to GND. Select R1 and R3 (Figure 13)
so the current through the divider is at least 10µA:
R1 + R3 < 200kΩ
A typical value for R1 is 10kΩ; then solve for R3 using:
R3 = R1 ×
38
VLIM
2 − VLIM
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
PC Board Layout Guidelines
A properly designed PC board layout is important in
any switching DC-DC converter circuit. Mount the
MOSFETs, inductors, input/output capacitors, and current-sense resistor on the top side of the PC board. A
single large ground plane is preferred; however it is
very important to partition the ‘analog’ portion of this
ground plane from the ‘power’ portion of the ground
plane. Ensure that all analog ground connections are
made to the ground plane away from any areas of
power ground switching currents. Do not connect the
analog returns at a single point to the ground plane;
use as many direct connections as possible. Connect
the GND of the IC to the thermal pad of the IC on the
top layer. Connect the thermal pad to the ground plane
through at least nine 10-mil drill size VIAs.
To help dissipate heat, place high-power components
(MOSFETs and inductors) on a large copper area, or
use a heat sink. Keep high-current traces short, wide,
and tightly coupled to reduce trace inductances and
resistances. Gate-drive traces should be at least 20
mils wide, kept as short as possible, and tightly coupled to reduce EMI and ringing induced by high-frequency gate currents. Adjacent DH_ and LX_ traces
should be tightly coupled. Connect the PGND_ pins to
the ground plane near the controller through two VIAs
(each).
A clean current-sense signal is critical to a successful
layout. Always place the current-sense traces on the
bottom layer. Make sure all adjacent traces (for example CS1+, CS2+, and CS12-) are tightly coupled. Kelvin
connections to the current-sense element are essential.
For inductor DCR current-sensing, place all currentsense components near the inductor, except for the fil-
tering capacitors, which should be placed next to the
controller IC. This ensures that noise generated by
large di/dt on the LX node is kept away from both current-sense signals and the controller IC. To ensure the
integrity of the current-sense signal, the inner layer
above the bottom layer must be a solid ground plane.
Place the VL_ decoupling capacitor on the top layer
and near the VL_ pins. The negative terminal of the VL_
decoupling capacitor should be connected to PGND_
on the top layer. Also place the BST capacitors on the
top layer near the controller. When needed always use
double VIAs on the driver traces to reduce inductance.
Do not connect the PGND_ pins to the thermal pad on
the top layer.
The NTC thermistor should be placed near the “hottest”
inductor. Use two traces, tightly coupled, to return to
the controller. To ensure temperature compensation
accuracy, make sure that the GND trace of the NTC is
not “accidentally” connected to any other GND trace or
ground plane on the way back to the controller.
Place the BUF capacitor, REF capacitor, VCC capacitor, the current-sense decoupling capacitors, and the
remote-sense decoupling capacitors as close to the
MAX8809A/MAX8810A as possible. All decoupling
capacitors must make a direct connection to the corresponding pin. Making the connection using VIAs to
transition between layers creates parasitic inductance,
which negates the benefit of the decoupling capacitor.
If this cannot be avoided, use double VIAs to minimize
the parasitic inductance.
A sample layout is available in the evaluation kit to
speed designs.
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________
39
MAX8809A/MAX8810A
Applications Information
40
VSS_SEN
VCC_SEN
C14
VRREADY
VRHOT
VTT
R7
C12
R24
R23
SYSTEM 5V
R12
REF
OUTEN
R15
R6
C25
C21
VL
C26
R17
R16
R13
C8
VCC
R2
SYSTEM 5V
7
8
26
5
11
12
4
10
3
18
1
20
32
6
RS-
RS+
VL12
EP
GND
VRTSET
NTC
COMP
SS/OVP
REF
EN
VRREADY
VRHOT
SEL
VCC
U1
ILIM
2
ILIM
R25
9
OSC
MAX8809A
R1
REF
R3
29
31
34
PWM3
CS12-
19
16
C22
14
CS3+
15
CS2+
17
CS1+
VID5
35
36
VID4
37
VID3
38
VID2
39
VID1
40
VID0
13
CS3-
VID6
VID7
33
30
LX2
28
DL2
27
PGND2
BST2
DH2
22
LX1
24
DL1
25
PGND1
DH1
23
BST1
21
C18
C24
R22
VID0
VID3
VID2
VID1
VID4
VID5
VID6
VID7
C11
C9
VOUT
CS12-
C23
CS3+
CS2+
CS1+
C19
CS3-
C15
C27
VL
C28
R18
C16
DLY
C29
VL
U2
3
C30
DL
LX
DH
BST
C31
PGND
MAX8552
GND
VCC
6
PWM
7
EN
5
4
1
1
D1
10
3
2
8
9
C32
C33
C17
R14
1
1
1
1
1
1
3
2
3
2
3
2
3
2
3
2
3
2
N11
N9
N7
N5
N3
N1
1
1
1
1
1
1
3
2
3
2
3
2
3
2
3
2
3
2
N12
N10
N8
N6
N4
N2
C5
VIN+
VIN+
C6
CS3+
C20
R19
CS2+
C13
R10
CS1+
C10
R4
C7
C1
L3
L2
CS3-
R20
R11
R5
L1
C2
R9
CS12-
R21
C3
C4
VOUT
VIN+
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Figure 13. Intel VRD11 Desktop Application Circuit Using the MAX8809A—3-Phase, 85A
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A/MAX8810A
Table 8. Bill of Materials for Intel VRD11 3-Phase Desktop Application Circuit
(Figure 13)
COMPONENTS
C1–C4
DESCRIPTION
PART NUMBER
1500µF, 16V aluminum electrolytic capacitors
Rubycom 16VMBZ1500
C5, C6, C7
10µF, 16V X5R ceramic capacitors (1206)
Taiyo Yuden EMK316BJ106ML
C8, C15, C21
2.2µF, 10V X5R ceramic capacitors (0603)
Taiyo Yuden LMK107BJ225MA
C9, C11, C12, C16, C17
0.22µF, 16V X5R ceramic capacitors (0603)
Taiyo Yuden EMK107BJ224KA
C10, C13, C20
2200pF, 50V X7R ceramic capacitors (0603)
TDK C1608X7R1H222K
68pF, 50V C0G ceramic capacitor (0603)
Kemet C0603C101J5GACTU
C18, C22, C23
0.22µF, 10V X5R ceramic capacitors (0603)
TDK C1608X5R1A224K
C19, C24, C25, C26
1000pF, 50V X7R ceramic capacitors (0603)
Kemet C0603C102J5RACTU
560µF, 4V, 7mΩ ESR OS-CON capacitors
Sanyo 4R5SEP560M
C14
C27–C33
D1
L1, L2, L3
N1, N2, N5, N6, N9, N10
N3, N4, N7, N8, N11, N12
30V, 200mA Schottky diode (SOT23)
Central Semiconductor CMPSH-3
0.20µH, 30A toroid cores
Falco T50069
30V, 12mΩ n-channel logic MOSFETs (DPAK)
International Rectifier IRLR7821
30V, 4.5mΩ n-channel logic MOSFETs (DPAK)
International Rectifier IRLR7843
R1
10kΩ ±1% resistor (0603)
—
R2
10Ω ±5% resistor (0603)
—
R15
5.62kΩ ±1% resistor (0603)
—
R4, R9, R10, R19, R21
2.2Ω ±5% resistors (0603)
—
1.62kΩ ±1% resistors (0603)
—
R5, R11, R20
R6, R7
680Ω ±1% resistors (0603)
—
R3, R12
8.06kΩ ±1% resistors (0603)
—
R13
22kΩ ±5% resistor (0603)
—
R14
0Ω ±5% resistor (0603)
—
R16
10kΩ NTC thermistor
Panasonic ERTJ1VR103
R17
61.9kΩ ±1% resistor (0603)
—
R18
7.1kΩ ±1% resistor (0603)
—
R22
Not installed
R23, R24
100Ω ±1% resistors (0603)
R25
220kΩ ±1% resistor (0603)
—
U1
VRD11, VRD10, and K8 Rev F 3-phase controller
Maxim MAX8809A
U2
High-speed, single-phase MOSFET driver
Maxim MAX8552
—
______________________________________________________________________________________
41
42
VRREADY
VRHOT
VTT
VSS_SEN
VCC_SEN
R7
R13
C13
REF
R23
R22
SYSTEM 5V
OUTEN
C14
NTC
R6
8
9
31
5
13
14
30
C30
COMP
SS/OVP
REF
EN
VRREADY
VRHOT
SEL
VCC
RS-
RS+
VL2
EP
VL1
GND
VRTSET
NTC
4 BUF
3
12
C25
C31
C17
R27
R12
2
21
48
24
38
6
VL
R16
C9
VCC
R2
SYSTEM 5V
U1
ILIM
1
R26
11
OSC
MAX8810A
R1
REF
R3
34
36
40
39
16
19
VOUT
23
PWM3
22
PWM4
CS12-
15
CS4+
17
CS3+
18
CS2+
20
CS1+
CS34-
VID5
41
42
VID4
43
VID3
44
VID2
45
VID1
46
VID0
VID6
VID7
35
LX2
33
DL2
32
PGND2
BST2
DH2
26
LX1
28
DL1
29
PGND1
25
DH1
27
BST1
C33
C19
C34
C26
VID0
VID3
VID2
VID1
VID4
VID5
N.C.
N.C.
C12
C10
C35
C28
C20
CS12-
C36
C27
CS4+
CS3+
CS2+
CS1+
C21
CS34-
C37
C23
R15
C38
C18
C39
R20
4
DLY
VCC
C40
3
U2
LX1
DH1
BST1
D1
1
2
1
5
3
2
DL2
LX2
12
14
16
BST2
15
DH2
6
PGND1
11
PGND2
DL1
MAX8523
PV2
PV1
9
PWM1
10
PWM2
8
7
13
VL
C29
R21
C22
R14
1
1
1
1
1
1
1
1
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
N15
N13
N11
N9
N7
N5
N3
N1
1
1
1
1
1
1
1
1
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
N16
N14
N12
N10
N8
N6
N4
N2
C5
VIN+
VIN+
VIN+
C6
R30
C44
CS4+
C32
R24
R29
C43
CS3+
C24
R17
R28
C42
CS2+
C15
R10
R27
C41
CS1+
C11
R4
C7
C8
R25
R18
R11
R5
L4
L3
L2
L1
C1
C2
CS34-
R19
CS12-
R9
C3
VOUT
C4
VIN+
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Figure 14. Intel VRD11 Desktop Application Circuit Using the MAX8810A—4-Phase, 115A
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A/MAX8810A
Table 9. Bill of Materials for Intel VRD11 4-Phase Desktop Application Circuit
(Figure 14)
COMPONENTS
C1–C4
DESCRIPTION
1500µF, 16V aluminum electrolytic capacitors
PART NUMBER
Rubycom 16VMBZ1500
C5–C8
10µF, 16V X5R ceramic capacitors (1206)
Taiyo Yuden EMK316BJ106ML
C9, C17, C18, C25
2.2µF, 10V X5R ceramic capacitors (0603)
Taiyo Yuden LMK107BJ225MA
C10, C12, C13, C22, C29
0.22µF, 16V X5R ceramic capacitors (0603)
Taiyo Yuden EMK107BJ224KA
C11, C15, C24, C32
2200pF, 50V X7R ceramic capacitors (0603)
TDK C1608X7R1H222K
C14
68pF, 50V C0G ceramic capacitor (0603)
Kemet C0603C101J5GACTU
C19, C20, C26, C27
0.22µF, 10V X5R ceramic capacitors (0603)
TDK C1608X5R1A224K
C21, C28, C30, C31
1000pF, 50V X7R ceramic capacitors (0603)
Murata C0603C102J5RACTU
560µF, 4V, 7mΩ ESR OS-CON capacitors
Sanyo 4R5SEP560M
30V, 200mA Schottky diode (SOT23)
Central Semiconductor CMPSH-3A
0.20µH, 30A toroid cores
Falco T50069
30V, 12mΩ n-channel logic MOSFETs (DPAK)
International Rectifier IRLR7821
C33–C40
D1
L1–L4
N1, N2, N5, N6, N9, N10, N13, N14
N3, N4, N7, N8, N11, N12, N15, N16
30V, 4.5mΩ n-channel logic MOSFETs (DPAK)
International Rectifier IRLR7843
R1
10kΩ ±1% resistor (0603)
—
R2, R15
10Ω ±5% resistors (0603)
—
R3
7.15Ω ±1% resistor (0603)
—
R4, R9, R10, R17, R19, R24
2.2Ω ±5% resistors (0603)
—
1.62kΩ ±1% resistors (0603)
—
R5, R11, R18, R25
R6, R7
680Ω ±1% resistors (0603)
—
R12
22.0kΩ ±1% resistor (0603)
—
R13
26.1kΩ ±1% resistor (0603)
—
0Ω ±5% resistors (0603)
—
R16
61.9kΩ, ±1% resistor (0603)
—
R20
7.17Ω ±1% resistor (0603)
—
R22, R23
100Ω ±1% resistors (0603)
—
R26
160kΩ ±1% resistor (0603)
—
R27
2.87kΩ ±1% resistor (0603)
—
10kΩ NTC thermistor
Panasonic ERTJ1VR103
R14, R21
NTC
U1
VRD11, VRD10, and K8 Rev F 4-phase controller Maxim MAX8810A
U2
High-speed, dual-phase MOSFET driver
Maxim MAX8523
______________________________________________________________________________________
43
44
VSS_SEN
R7
C13
REF
R23
R22
SYSTEM 5V
R13
OUTEN
C14
NTC
C16
R6
VCC_SEN
VRREADY
VRHOT
VTT
8
9
31
5
13
14
C25
C30
SS/OVP
REF
EN
VRREADY
VRHOT
SEL
VCC
RS-
RS+
VL2
EP
VL1
GND
VRTSET
NTC
COMP
4 BUF
3
12
30
C31
C17
R12
2
21
48
24
38
6
VL
R16
C9
VCC
R2
SYSTEM 5V
1
U1
ILIM
R26
11
OSC
MAX8810A
R1
REF
R3
DH2
34
40
39
16
19
VOUT
23
PWM3
22
PWM4
CS12-
15
CS4+
17
CS3+
18
CS2+
20
CS1+
CS34-
41
VID5
42
VID4
43
VID3
44
VID2
45
VID1
46
VID0
VID6
VID7
35
LX2
33
DL2
32
PGND2
BST2
36
26
LX1
28
DL1
29
PGND1
25
DH1
27
BST1
C33
C19
C34
C26
VID0
VID3
VID2
VID1
VID4
VID5
N.C.
N.C.
C12
C10
C35
C28
C20
CS12-
C36
C27
CS4+
CS3+
CS2+
CS1+
C21
CS34-
C37
C23
R15
C38
C18
C39
R20
4
DLY
VCC
C40
3
U2
LX1
DH1
BST1
D1
2
1
5
3
2
1
DL2
LX2
12
14
16
BST2
15
DH2
6
PGND1
11
PGND2
DL1
MAX8523
PV2
PV1
9
PWM1
10
PWM2
8
7
13
VL
C29
R21
C22
R14
1
1
1
1
1
1
1
1
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
N15
N13
N11
N9
N7
N5
N3
N1
1
1
1
1
1
1
1
1
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
N16
N14
N12
N10
N8
N6
N4
N2
C5
C11
R4
R30
C44
CS4+
C32
R24
R29
C43
VIN+ CS3+
C24
R17
R28
C42
VIN+ CS2+
C15
R10
R27
C7
C41
VIN+ CS1+
C6
C8
R25
R18
R11
R5
L4
L3
L2
L1
C1
C2
CS34-
R19
CS12-
R9
C3
VOUT
C4
VIN+
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Figure 15. AMD K8 Rev F Desktop Application Circuit Using the MAX8810A—4-Phase, 115A
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A/MAX8810A
Table 10. Bill of Materials for AMD K8 Rev F Desktop Application Circuit (Figure 15)
COMPONENTS
DESCRIPTION
PART NUMBER
C1–C4
1500µF, 16V aluminum electrolytic capacitors
C5–C8
10µF, 16V X5R ceramic capacitors (1206)
Taiyo Yuden EMK316BJ106ML
C9, C17, C18, C25
2.2µF, 10V X5R ceramic capacitors (0603)
Taiyo Yuden LMK225BJ225ML
C10, C12, C13, C22, C29
0.22µF, 10V X5R ceramic capacitors (0603)
Taiyo Yuden EMK107BJ224KA
C11, C15, C24, C32
2200pF, 50V X7R ceramic capacitors (0603)
TDK C1608X7R1H222K
Not installed (0603)
—
C14
Rubycom 16VMBZ1500
C16
0.015µF, 50V C0G ceramic capacitor (0603)
Murata GRM39X7R153K50
C19, C20, C23, C26, C27
0.22µF, 10V X5R ceramic capacitors (0603)
TDK C1608X5R1A224K
1000pF, 50V X7R ceramic capacitors (0603)
Kemet C0603C102J5RACTU
2200µF, 6.3V, 12mΩ ESR aluminum electrolytic
capacitors
Rubycon 6.3VMBZ2200
C21, C28, C30, C31
C33–C40
C41–C44
D1
L1–L4
Not installed (0603)
—
30V, 200mA Schottky diode (SOT23)
Central Semiconductor CMPSH-3A
0.28µH, 30A toroid cores
Falco T50183
N1, N2, N5, N6, N9, N10, N13, N14
30V, 12mΩ n-channel logic MOSFETs (DPAK)
International Rectifier IRLR7821
N3, N4, N7, N8, N11, N12, N15, N16
30V, 4.5mΩ n-channel logic MOSFETs (DPAK)
International Rectifier IRLR7843
10kΩ ±1% resistor (0603)
—
10Ω ±5% resistors (0603)
—
R1
R2, R15
R3
7.15kΩ ±1% resistor (0603)
—
R4, R9, R10, R17, R19, R24
2.2Ω ±5% resistors (0603)
—
1.62kΩ ±1% resistors (0603)
—
R6, R7
680Ω ±1% resistors (0603)
—
R12
22.0kΩ ±1% resistor (0603)
—
R13
4.32kΩ ±1% resistor (0603)
—
0Ω ±5% resistors (0603)
—
R16
61.9kΩ ±1% resistor (0603)
—
R5, R11, R18, R25
R14, R21
R20
7.10kΩ ±1% resistor (0603)
—
R22, R23
100Ω ±11% resistors (0603)
—
R26
160kΩ ±1% resistor (0603)
—
R27–R30
Not installed (0603)
—
10kΩ NTC thermistor
Panasonic ERTJ1VR103
U1
VRD11, VRD10, and K8 Rev F 4-phase
Maxim MAX8810A
U2
High-speed, dual-phase MOSFET driver
Maxim MAX8523
NTC
______________________________________________________________________________________
45
Table 11. Suggested Component Suppliers
PHONE
FAX
BI Technologies
COMPONENT SUPPLIER
714-447-2300
714-388-0046
www.bitechnologies.com
Falco
305-662-7276
928-752-3256
www.falco.com
International Rectifier
310-252-7105
310-252-7903
www.irf.com
Kemet
864-963-6300
408-986-1442
www.kemet.com
Murata
770-436-1300
770-436-3030
www.murata.com
Pulse
215-781-6400
215-781-6403
www.pulseeng.com
Panasonic
800-344-2112
—
www.panasonic.com
Sanyo
619-661-6835
619-661-1055
81-3-3833-5441
81-3-3835-4754
408-437-9585
408-437-9591
Taiyo Yuden
TDK
WEBSITE
www.sanyo.com
www.t-yuden.com
www.component.tdk.com
DH2 31
SEL 32
VID7 33
VID6 34
VID5 35
MAX8809A
VID3 37
DH1
LX1
BST1
DL1
PGND1
VL1
VL2
PGND2
DL2
37
24
20 VRHOT
SEL
38
23
PWM3
19 PWM3
VID7
39
22
PWM4
18 EN
VID6
40
21
EN
17 CS1+
VID5
41
20
CS1+
16 CS12-
VID4
42
19
CS12-
MAX8810A
15 CS2+
VID3
43
18
CS2+
14 CS3+
VID2
44
17
CS3+
CS34-
VID2 38
13 CS3-
VID1
45
16
VID1 39
12 NTC
VID0
46
15
CS4+
11 VRTSET
N.C.
47
14
NTC
VRREADY
48
13
VRTSET
SS/OVP
4
5
6
7
8
9
10 11 12
THIN QFN
______________________________________________________________________________________
SS/OVP
OSC
3
N.C.
RS+
2
OSC
RS-
1
RS+
VCC
THIN QFN
+
RS-
10
N.C.
9
VCC
8
GND
7
BUF
6
REF
5
COMP
4
ILIM
3
GND
2
REF
1
COMP
+
ILIM
VID0 40
46
VRHOT
N.C.
30 29 28 27 26 25 24 23 22 21
VID4 36
DH2
36 35 34 33 32 31 30 29 28 27 26 25
DH1
LX1
BST1
DL1
PGND1
VL12
PGND2
DL2
BST2
LX2
TOP VIEW
LX2
TOP VIEW
BST2
Pin Configurations
VRREADY
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
QFN THIN.EPS
______________________________________________________________________________________
47
MAX8809A/MAX8810A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
48
______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
QFN THIN.EPS
______________________________________________________________________________________
49
MAX8809A/MAX8810A
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Revision History
Pages changed at Rev 1: 1–6, 8, 13–16, 19, 20, 22,
30-37, 40, 43.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
50 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Cardenas - 80%
Freed - 20%
is a registered trademark of Maxim Integrated Products, Inc.