NCP1602 Product Preview Enhanced, High-Efficiency Power Factor Controller The 6−pin PFC controller NCP1602 is designed to drive PFC boost stages. It is based on an innovative Valley Synchronized Frequency Fold−back (VSFF) method. In this mode, the circuit classically operates in Critical conduction Mode (CrM) when Vcontrol voltage exceeds a programmable value Vctrl,FF. When Vcontrol is below this preset level Vctrl,FF, the NCP1602 (versions [B**] and [D**]) linearly decays the frequency down to about 30 kHz until Vcontrol reaches the SKIP mode threshold. VSFF maximizes the efficiency at both nominal and light load. In particular, the stand−by losses are reduced to a minimum. Like in FCCrM controllers, internal circuitry allows near−unity power factor even when the switching frequency is reduced. Housed in a TSOP6 package, the circuit also incorporates the features necessary for robust and compact PFC stages, with few external components. General Features • • • • • • • • • • • • Near−Unity Power Factor Two−Level Boost Follower Line Level Dependent (disabled by default) Critical Conduction Mode (CrM) Valley Synchronized Frequency Fold−back (VSFF): Low Frequency Operation is Forced at Low Current Levels (9 pre−programmed settings). Works With or Without a Transformer w/ ZCD Winding (simple inductor) On−time Modulation to Maintain a Proper Current Shaping in VSFF Mode Skip Mode at Very Low Load Current (versions[ B**] and [D**]) Fast Line / Load Transient Compensation (Dynamic Response Enhancer) www.onsemi.com TSOP−6 SN SUFFIX CASE 318G 1 MARKING DIAGRAM AEA AYWG G 1 AEA A Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS VCTRL 1 6 FB GND 2 5 VCC CS / ZCD 3 4 DRV Valley Turn−on High Drive Capability: −500 mA / +800 mA (Top View) VCC Range: from 9.5 V to 30 V Low Start−up Consumption for: ORDERING INFORMATION [**C] & [**D] Versions: Low Vcc Start−up level (10.5 V) See detailed ordering and shipping information in the package [**A] & [**B] Versions: High Vcc Start−up level (17.0 V) dimensions section on page 2 of this data sheet. • Line Range Detection for Reduced Crossover Frequency Spread • This is a Pb−Free Device • Low Duty−Cycle Operation if the Bypass Diode is Shorted Safety Features • Open Ground Pin Fault Monitoring • Thermal Shutdown • • • • • • Typical Applications Non−latching, Over−Voltage Protection Second Over−Voltage Protection Brown−Out Detection Soft−Start for Smooth Start−up Operation ([**C] & [**D] Versions) Over Current Limitation Disable Protection if the Feedback Pin is Not Connected • • • • PC Power Supplies Lighting Ballasts (LED, Fluorescent) Flat TV All Off Line Appliances Requiring Power Factor Correction This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2015 May, 2015 − Rev. P1 1 Publication Order Number: NCP1602/D NCP1602 DEVICE ORDERING INFORMATION Operating Part Number (OPN) Marking (L1, L2, L3) NCP1602ABASNT1G ABA NCP1602AEASNT1G AEA NCP1602AHASNT1G AHA NCP1602DEBSNT1G DEB NOTE: Package Type Tape and Reel Size TSOP−6 (Pb−Free) Other L1, L2, L3 combinations are available upon request. Product versions are coded with three letters (L1,L2,L3). Table 1. NCP1602 1st LETTER CODING OF PRODUCT VERSIONS L1 Brown−out Function Skip Mode Function A NO NO B NO YES (trim) C YES (trim) NO D YES (trim) YES (trim) Table 2. NCP1602 2nd LETTER CODING OF PRODUCT VERSIONS L2 CrM to DCM VCTRL Threshold (V) tON,max,LL (ms) tON,max,HL(ms) A 0.816 25 8.33 B 1.026 25 8.33 C 1.296 25 8.33 D 1.132 12.5 4.17 E 1.553 12.5 4.17 F 2.079 12.5 4.17 G 1.459 8.3 2.77 H 2.079 8.3 2.77 I 2.840 8.3 2.77 Table 3. NCP1602 3rd LETTER CODING OF PRODUCT VERSIONS L3 VCC Startup Level (V) 2−Level Boost Follower Feature A 17.0 NO B 17.0 YES (trim) C 10.5 NO D 10.5 YES (trim) www.onsemi.com 2 NCP1602 Vin D1 L1 IL Vbulk Rfb1 AC line VCTRL Cin EMI Filter 6 2 5 VCC GND Rcs1 CS / ZCD 3 Rz Cbulk FB 1 4 LOAD DRV Q1 Cp Rcszcd Rcs2 Cz Rfb2 Rsense Figure 1. NCP1602 Application Schematic Table 4. DETAILED PIN DESCRIPTION Pin Number Name Function 1 VCTRL The error amplifier output is available on this pin. The network connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios. VCTRL pin is internally pulled down when the circuit is off so that when it starts operation, the power increases slowly to provide a soft−start function. VCTRL pin must not be controlled or pulled down externally. 2 GND 3 CS / ZCD 4 DRV The high−current capability of the totem pole gate drive (−0.5/+0.8A) makes it suitable to effectively drive high gate charge power MOSFETs. 5 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 17.0 V ([**A] & [**B] Versions) or 10.5 V ([**C] & [**D] Versions) and turns off when VCC goes below 9.0 V (typical values). After start−up, the operating range is 9.5 V up to 30 V. 6 FB Connect this pin to the PFC stage ground. This pin monitors the MOSFET current to limit its maximum current. This pin is the output of a resistor bridge connected between the drain and the source of the power MOSFET. Internal circuitry takes care of extracting Vin , Vout , Iind and ZCD This pin receives a portion of the PFC output voltage for the regulation and the Dynamic Response Enhancer (DRE) that drastically speeds−up the loop response when the output voltage drops below 95.5% of the desired output level. FB pin voltage VFB is also the input signal for the (non−latching) Over−Voltage (OVP) and Under−Voltage (UVP) comparators. The UVP comparator prevents operation as long as FB pin voltage is lower than VUVPH internal voltage reference. A SOFTOVP comparator gradually reduces the duty−ratio when FB pin voltage exceeds 105% of VREF. If the output voltage still increases, the driver is immediately disabled if the output voltage exceeds 107% of the desired level (fast OVP). A 250−nA sink current is built−in to trigger the UVP protection and disable the part if the feedback pin is accidently open. www.onsemi.com 3 NCP1602 Table 5. MAXIMUM RATINGS TABLE Symbol Pin Rating Value Unit VCTRL 1 VCONTROL pin −0.3, Vctrl,max(*) V CS/ZCD 3 CS/ZCD Pin −0.3, +9 V DRV 4 Driver Voltage Driver Current −0.3, VDRV (*) −500, +800 V mA VCC 5 Power Supply Input −0.3, + 30 V VCC 5 Maximum (dV/dt) that can be applied to VCC TBD upon test engineer measurements V/s FB 6 Feedback Pin −0.3, +9 V PD RqJA Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ TA=70°C Thermal Resistance Junction to Air 550 145 mW °C/W TJ Operating Junction Temperature Range −40 to+125 °C TJ,max Maximum Junction Temperature 150 °C TS,max Storage Temperature Range −65 to 150 °C TL,max Lead Temperature (Soldering, 10 s) 300 °C MSL Moisture Sensitivity Level 1 − ESD Capability, HBM model (Note 1) > 2000 V ESD Capability, Machine Model (Note 1) > 200 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *“Vctrl,max” is the VCTRL pin clamp voltage. “VDRV” is the DRV clamp voltage (VDRVhigh) if VCC is higher than (VDRVhigh). “VDRV” is VCC otherwise. 1. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E Machine Model Method 200 V per JEDEC Standard JESD22−A115−A 2. This device contains latch up protection and exceeds 100 mA per JEDEC Standard JESD78. www.onsemi.com 4 NCP1602 PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE U D H ÉÉÉ ÉÉÉ 6 E1 1 NOTE 5 5 2 4 L2 GAUGE PLANE E 3 L M b SEATING PLANE DETAIL Z e 0.05 C A c A1 DETAIL Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. DIM A A1 b c D E E1 e L L2 M MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 6X 3.20 0.95 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 21 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP1602/D