NCP1602 D

NCP1602
Enhanced, High-Efficiency
Power Factor Controller
The 6−pin PFC controller NCP1602 is designed to drive PFC boost
stages. It is based on an innovative Valley Synchronized Frequency
Fold−back (VSFF) method. In this mode, the circuit classically
operates in Critical conduction Mode (CrM) when Vcontrol voltage
exceeds a programmable value Vctrl,FF. When Vcontrol is below this
preset level Vctrl,FF, the NCP1602 (versions [B**] and [D**]) linearly
decays the frequency down to about 30 kHz until Vcontrol reaches the
SKIP mode threshold. VSFF maximizes the efficiency at both
nominal and light load. In particular, the stand−by losses are reduced
to a minimum. Like in FCCrM controllers, internal circuitry allows
near−unity power factor even when the switching frequency is
reduced. Housed in a TSOP6 package, the circuit also incorporates the
features necessary for robust and compact PFC stages, with few
external components.
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MARKING DIAGRAM
AEA AYWG
G
1
General Features
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TSOP−6
SN SUFFIX
CASE 318G
Near−Unity Power Factor
Two−Level Boost Follower Line Level Dependent (disabled by default)
Critical Conduction Mode (CrM)
Valley Synchronized Frequency Fold−back (VSFF): Low Frequency
Operation is Forced at Low Current Levels
Works With or Without a Transformer w/ ZCD Winding (simple inductor)
AEA
A
Y
W
G
(Note: Microdot may be in either location)
On−time Modulation to Maintain a Proper Current Shaping in VSFF Mode
Skip Mode at Very Low Load Current (versions[ B**] and [D**])
Fast Line / Load Transient Compensation (Dynamic Response Enhancer)
Valley Turn−on
High Drive Capability: −500 mA / +800 mA
VCC Range: from 9.5 V to 30 V
Low Start−up Consumption for:
[**C] & [**D] Versions: Low Vcc Start−up level (10.5 V)
[**A] & [**B] Versions: High Vcc Start−up level (17.0 V)
Line Range Detection for Reduced Crossover Frequency Spread
This is a Pb−Free Device
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
VCTRL
1
6
FB
GND
2
5
VCC
CS / ZCD
3
4
DRV
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Safety Features
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Typical Applications
Thermal Shutdown
Non−latching, Over−Voltage Protection
Second Over−Voltage Protection
Brown−Out Detection
Soft−Start for Smooth Start−up Operation ([**C] &
[**D] Versions)
Over Current Limitation
Disable Protection if the Feedback Pin is Not Connected
Low Duty−Cycle Operation if the Bypass Diode is
Shorted
Open Ground Pin Fault Monitoring
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 2
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PC Power Supplies
Lighting Ballasts (LED, Fluorescent)
Flat TV
All Off Line Appliances Requiring Power Factor
Correction
Publication Order Number:
NCP1602/D
NCP1602
DEVICE ORDERING INFORMATION
Operating Part Number (OPN)
Marking (L1, L2, L3)
Package Type
Shipping
AEA
TSOP−6
(Pb−Free)
3000 / Tape & Reel
NCP1602AEASNT1G
NOTE:
ABA, DCC and DFC options can also be ordered, other L1, L2, L3 combinations are available upon request.
Product versions are coded with three letters (L1,L2,L3).
Table 1. NCP1602 1st LETTER CODING OF PRODUCT VERSIONS
L1
Brown−out Function
Skip Mode Function
A
NO
NO
B
NO
YES (trim)
C
YES (trim)
NO
D
YES (trim)
YES (trim)
Table 2. NCP1602 2nd LETTER CODING OF PRODUCT VERSIONS (*) UPON REQUEST
L2
CrM to DCM VCTRL Threshold (V)
tON,max,LL (ms)
tON,max,HL(ms)
B (*)
1.026
25
8.33
C (*)
1.296
25
8.33
E
1.553
12.5
4.17
F (*)
2.079
12.5
4.17
Table 3. NCP1602 3rd LETTER CODING OF PRODUCT VERSIONS
L3
VCC Startup Level (V)
2−Level Boost Follower Feature
A
17.0
NO
B
17.0
YES (trim)
C
10.5
NO
D
10.5
YES (trim)
Vin
D1
L1
IL
Vbulk
Rfb1
AC line
VCTRL
Cin
EMI
Filter
6
2
5
VCC
GND
Rcs1
CS / ZCD
3
Rz
Cbulk
FB
1
4
LOAD
DRV
Q1
Cp
Rcszcd
Cz
Rcs2
Rsense
Figure 1. NCP1602 Application Schematic
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Rfb2
NCP1602
Table 4. DETAILED PIN DESCRIPTION
Pin Number
Name
Function
1
VCTRL
The error amplifier output is available on this pin. The network connected between this pin
and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve
high Power Factor ratios.
VCTRL pin is internally pulled down when the circuit is off so that when it starts operation, the
power increases slowly to provide a soft−start function.
VCTRL pin must not be controlled or pulled down externally.
2
GND
3
CS / ZCD
4
DRV
The high−current capability of the totem pole gate drive (−0.5/+0.8A) makes it suitable to
effectively drive high gate charge power MOSFETs.
5
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds
17.0 V ([**A] & [**B] Versions) or 10.5 V ([**C] & [**D] Versions) and turns off when VCC
goes below 9.0 V (typical values). After start−up, the operating range is 9.5 V up to 30 V.
6
FB
Connect this pin to the PFC stage ground.
This pin monitors the MOSFET current to limit its maximum current.
This pin is the output of a resistor bridge connected between the drain and the source of the
power MOSFET. Internal circuitry takes care of extracting Vin , Vout , Iind and ZCD
This pin receives a portion of the PFC output voltage for the regulation and the Dynamic
Response Enhancer (DRE) that drastically speeds−up the loop response when the output
voltage drops below 95.5% of the desired output level.
FB pin voltage VFB is also the input signal for the (non−latching) Over−Voltage (OVP) and
Under−Voltage (UVP) comparators. The UVP comparator prevents operation as long as FB
pin voltage is lower than VUVPH internal voltage reference. A SOFTOVP comparator gradually reduces the duty−ratio when FB pin voltage exceeds 105% of VREF. If the output voltage
still increases, the driver is immediately disabled if the output voltage exceeds 107% of the
desired level (fast OVP).
A 250−nA sink current is built−in to trigger the UVP protection and disable the part if the feedback pin is accidently open.
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NCP1602
Table 5. MAXIMUM RATINGS TABLE
Symbol
Pin
Rating
Value
Unit
VCTRL
1
VCONTROL pin
−0.3, Vctrl,max(*)
V
CS/ZCD
3
CS/ZCD Pin
−0.3, +9
V
DRV
4
Driver Voltage
Driver Current
−0.3, VDRV (*)
−500, +800
V
mA
VCC
5
Power Supply Input
−0.3, + 30
V
VCC
5
Maximum (dV/dt) that can be applied to VCC
TBD upon test engineer
measurements
V/s
FB
6
Feedback Pin
−0.3, +9
V
PD
RqJA
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA=70°C
Thermal Resistance Junction to Air
550
145
mW
°C/W
TJ
Operating Junction Temperature Range
−40 to+125
°C
TJ,max
Maximum Junction Temperature
150
°C
TS,max
Storage Temperature Range
−65 to 150
°C
TL,max
Lead Temperature (Soldering, 10 s)
300
°C
MSL
Moisture Sensitivity Level
1
−
ESD Capability, HBM model (Note 1)
> 2000
V
ESD Capability, Charged Device Model (Note 1)
> 1500
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*“Vctrl,max” is the VCTRL pin clamp voltage. “VDRV” is the DRV clamp voltage (VDRVhigh) if VCC is higher than (VDRVhigh). “VDRV” is VCC otherwise.
1. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Charged Device Model Method 1500 V per JEDEC Standard JESD22−C101E.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1602
Table 6. TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol
Rating
Min
Typ
Max
Unit
Start−Up Threshold, VCC increasing:
[**C] & [**D] Versions
[**A] & [**B] Versions
9.75
15.80
10.50
17.00
11.25
18.20
VCC,off
Minimum Operating Voltage, VCC falling
8.50
9.00
9.50
VCC,hyst
Hysteresis (VCC ,on − VCC ,off)
[**C] & [**D] Versions
[**A] & [**B] Versions
0.75
6.00
1.50
8.00
−
−
ICC,start
Maximum Start−Up Current, for VCC lower than 9.4 V, below startup voltage
−
−
480
mA
ICC,op1
Operating Consumption, no switching.
−
0.5
1.00
mA
ICC,op2
Operating Consumption, 50−kHz switching, no load on DRV pin
−
2.00
3.00
mA
START−UP AND SUPPLY CIRCUIT
VCC,on
V
V
V
FREQUENCY FOLD−BACK DEAD TIME FOR CONFIGURATIONS L2 = B, E, H @ Km = 2.28
tDT,E,1
Dead−Time, Vctrl = 0.65V w/ E config
9.96
13.28
16.60
ms
tDT,E,2
Dead−Time, Vctrl = 0.75V w/ E config
6.70
8.93
10.80
ms
1.398
1.553
1.708
V
CrM TO DCM THRESHOLD AND HYSTERESIS
Vctrl threshold CrM to DCM mode w/ E config
Vctrl,th,E
SKIP CONTROL ([B**] & [D**] Versions)
VSKIP−H
Vctrl pin SKIP Level, Vcontrol rising
555
617
678
mV
VSKIP−L
Vctrl pin SKIP Level, Vcontrol falling
516
593
665
mV
VSKIP−Hyst
Vctrl pin SKIP Hysteresis
−
30
−
mV
tR
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
−
30
−
ns
GATE DRIVE
tF
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
−
20
−
ns
ROH
Source resistance @ 200 mV under High VCC
−
10
−
Ω
ROL
Sink resistance @200 mV above Low VCC
−
7
−
Ω
VDRV,low
DRV pin level for VCC = VCC,off +200 mV (10−kΩ resistor between DRV and GND)
8.0
−
−
V
VDRV,high
DRV pin level at VCC = 30 V (RL = 33 kΩ & CL = 1 nF)
10
12
14
V
REGULATION BLOCK
VREF
Feedback Voltage Reference
2.44
2.50
2.56
V
VREF2,HL
Feedback Voltage Reference #2 @ High Line
2.44
2.50
2.56
V
VREF2,LL
Feedback Voltage Reference #2 @ Low Line
1.56
1.60
1.64
V
IEA
Error Amplifier Current Capability, Sinking and Sourcing
15
20
26
mA
GEA
Error Amplifier Gain
110
200
290
mS
Vctrl
Vctrl,min
Vctrl,max
VCTRL pin Voltage (Vctrl ):
− @ VFB = 2 V (OTA is sourcing 20 mA)
− @ VFB = 3 V (OTA is sinking 20 mA)
−
−
4.5
0.5
−
−
V
V
Vout,L / VREF2
Ratio (Vout Low Detect Threshold / VREF ) (guaranteed by design)
−
95.5
−
%
Hout,L / VREF2
Ratio (Vout Low Detect Hysteresis / VREF ) (guaranteed by design)
−
0.35
−
%
IBOOST
VCTRL pin Source Current when (VOUT Low Detect) is activated
147
220
277
mA
CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS
VCS(th)
Current Sense Voltage Reference
450
500
550
mV
VCS,OVS(th)
Current Sense Overstress Voltage Reference
675
750
825
mV
3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
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NCP1602
Table 6. TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol
Rating
Min
Typ
Max
Unit
CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS
tLEB,OVS
“Overstress” Leading edge Blanking Time (guaranteed by design)
−
250
−
ns
tLEB,OCP
“Over−Current Protection” Leading edge Blanking Time (guaranteed by design)
−
400
−
ns
tOCP
Over−Current Protection Delay from VCS/ZCD >VCS(th) to
DRV low (dVCS/ZCD / dt = 10 V/ms)
−
40
200
ns
VZCD(th)H
Zero Current Detection, VCS/ZCD rising
8
35
62
mV
VZCD(th)L
Zero Current Detection, VCS/ZCD falling
−68
−46
−25
mV
VZCD(hyst)
Hysteresis of the Zero Current Detection Comparator
46
84
−
mV
To discuss versus what esd protection will be used
VCL(pos)
CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA (guaranteed by design)
−
9.5
−
V
tZCD
(VCS/ZCD < VZCD (th )L ) to (DRV high)
−
60
200
ns
tSYNC
Minimum ZCD Pulse Width
−
110
200
ns
tWDG
Watch Dog Timer
80
200
320
ms
tWDG(OS)
Watch Dog Timer in “OverStress” Situation
400
800
1200
ms
IZCD(gnd)
Source Current for CS/ZCD pin impedance Testing
−
50
−
mA
IZCD(Vcc)
Pull−up current source referenced to Vcc for open pin detection
−
200
−
nA
Duty Cycle, VFB = 3 V ( When low clamp of Vctrl is reached)
−
−
0
%
STATIC OVP
DMIN
ON−TIME CONTROL (Option [*E*] for maximum tON value)
ton,LL,E
Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM)
11.4
12.5
13.6
ms
ton,HL,E
Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM)
3.75
4.17
4.59
ms
tON @LL over tON @HL ratio (all tON versions)
−
3
−
w/o
Kton,LL−HL
Specifying max tON,min means tON,min can go down to zero
ton,LL,min
Minimum On Time, avg(Vcs ) = 0.9 V
(not tested, guaranteed by design)
−
300
−
ns
ton,HL,min
Minimum On Time, avg(Vcs ) = 2.8 V
(not tested, guaranteed by design)
−
200
−
ns
FEED−BACK OVER AND UNDER−VOLTAGE PROTECTIONS (OVP and UVP)
RsoftOVP
Ratio (Soft OVP Threshold, VFB rising) over VREF (or VREF2)
(guaranteed by design)
−
105
−
%
RsoftOVP(HYST)
Ratio (Soft OVP Hysteresis) over VREF (or VREF2) (guaranteed by design)
−
1.87
−
%
RfastOVP
Ratio (Fast OVP Threshold, VFB rising) over VREF (or VREF2)
(guaranteed by design)
−
107
−
%
RfastOVP(HYST)
Ratio (Fast OVP Hysteresis) over VREF (or VREF2) (guaranteed by design)
−
4.0
−
%
VUVPH
UVP Threshold, VFB increasing
555
612
670
mV
VUVPL
UVP Threshold, VFB decreasing
252
303
357
mV
VUVP(HYST)
UVP Hysteresis
273
307
342
mV
IB,FB
FB pin Bias Current @ VFB = VOV P and VFB = VUVP
50
200
450
nA
819
894
mV
BROWN−OUT PROTECTION AND FEED−FORWARD (Vsns is an internal pin that replaces Vsense)
VBOH
Brown−Out Threshold Vmains increasing, VFB based
([C**] and [D**] versions)
754
3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
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NCP1602
Table 6. TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol
Rating
Min
Typ
Max
Unit
801
mV
BROWN−OUT PROTECTION AND FEED−FORWARD (Vsns is an internal pin that replaces Vsense)
VBOL
Brown−Out Threshold, Vmains decreasing, avg(VCS) based
([C**] and [D**] versions)
659
737
VBO(HYST)
Brown−Out Comparator Hysteresis ([C**] and [D**] versions)
75
100
−
mV
tBO(blank)
Brown−Out Blanking Time ([C**] and [D**] versions)
36
50
67
ms
IVCTRL(BO)
VCTRL pin sink current during BO condition
20
30
42
mA
VHL
Comparator Threshold for Line Range Detection, avg(VCS ) rising
1.718
1.801
1.882
V
VLL
Comparator Threshold for Line Range Detection, avg(VCS ) falling
1.310
1.392
1.474
V
VHL(hyst)
Comparator Hysteresis for Line Range Detection
75
400
−
mV
tHL(blank)
Blanking Time for Line Range Detection
13
25
43
ms
TLIMIT
Thermal Shutdown Threshold
150
−
−
°C
HTEMP
Thermal Shutdown Hysteresis
−
50
−
°C
OVP2 Threshold, VCS rising, KCS = 138, @ VREF2 = 2.5 V
3.048
3.175
3.302
V
THERMAL SHUTDOWN
SECOND OVERVOLTAGE PROTECTION (OVP2)
VOVP2H,HL
VOVP2L,HL
OVP2 Threshold, VCS falling, KCS = 138, @ VREF2 = 2.5 V
2.969
3.093
3.217
V
VOVP2(HYST),HL
OVP2 Comparator Hysteresis, KCS = 138, @ VREF2 = 2.5 V
50
100
−
mV
VOVP2H,LL
OVP2 Threshold, VCS rising, KCS = 138, @ VREF2 = 1.6 V
1.951
2.032
2.113
V
VOVP2L,LL
OVP2 Threshold, VCS falling, KCS = 138, @ VREF2 = 1.6 V
1.901
1.980
2.059
V
VOVP2(HYST),LL
OVP2 Comparator Hysteresis, KCS = 138, @ VREF2 = 1.6 V
30
50
−
mV
tLEB,OVP2
OVP2 Leading Edge Blanking Time, VCS rising (guaranteed by design)
−
1000
−
ns
tRST(OVP2)
Reset Timer for OVP2 latch
400
800
1200
ms
3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP1602
Transconductance
Error Amplifier
OVLFLAG1
VREF
FB
OVP2
OFF
VREGUL
VCTRL
MANAGMENT
BONOK
PFCOK
STATICOVP
FB
MANAGMENT
DRE
VREF,DRE
VREF,UVP
UVP
VREF,OVS
SOFTOVP
VREF,SOFT_OVP
FASTOVP
VREF,FAST_OVP
OVERSTRESS
DRV
V CC
CURRENT
SENSE
VREF
VREF,XXXX
OCP
THERMAL
SHUTDOWN
VREF,OCP
VDD
TSD
UVP
BONOK
DRV
DEMAG
&
LINE SENSE
FAULT
MANAGMENT
ZCD
OFF
STATICOVP
VSNS
VREF,VCC
UVLO
OFF
SECOND
OVP
VREF,LLINE
OVP2
STATICOVP
OCP
OVERSTRESS
PFCOK
S
OFF
OVP2
LINE & BO
MANAGMENT
OVLFLAG1
STOP
FASTOVP
ZCD
DT
Q
R
VREF,BONOK
BONOK
VCC
LLINE
CLK
Internal
Timing
Ramp
DRV
S
R
CLK
DT
SKIP
tON
Processing
Circuitry
CLK & DT
MANAGMENT
SKIPDEL
Figure 2. NCP1602 Block Diagram
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Q
Output
Buffer
NCP1602
TYPICAL CHARACTERISTICS
11.15
17.8
10.95
17.3
VCC(on) (V)
VCC(on) (V)
10.75
10.55
10.35
10.15
16.8
16.3
9.95
9.75
−60 −40 −20
9.5
0
20
40
60
80
15.8
−60 −40 −20
100 120 140
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Start−Up Threshold, VCC Increasing
(VCC,on) vs. Junction Temperature
(versions [**C]&[**D])
Figure 4. Start−Up Threshold, VCC Increasing
(VCC,on) vs. Junction Temperature
(versions [**A]&[**B])
2.75
9.4
9.3
2.25
VCC(hyst) (V)
VCC(off) (V)
9.2
9.1
9.0
8.9
8.8
1.25
8.7
8.6
8.5
−60 −40 −20
0
20
40
60
80
0.75
−60 −40 −20
100 120 140
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Minimum Operating Voltage, VCC
Falling (VCC,off) vs. Junction Temperature
Figure 6. Hysteresis (VCC,on – VCC,off) vs.
Junction Temperature (versions [**C]&[**D])
12
15.96
11
14.96
10
13.96
tDT,E,1 (ms)
VCC(hyst) (V)
1.75
9
12.96
8
11.96
7
10.96
6
−60 −40 −20
0
20
40
60
80
9.96
−60 −40 −20
100 120 140
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Hysteresis (VCC,on – VCC,off) vs.
Junction Temperature (versions [**A]&[**B])
Figure 8. Dead−Time, Vctrl = 0.65 V w/
E Config (tDT,E,1) vs. Junction Temperature
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NCP1602
TYPICAL CHARACTERISTICS
10.7
1.698
10.2
1.648
9.2
Vctrl,th,E (V)
tDT,E,2 (ms)
9.7
8.7
8.2
1.598
1.548
1.498
7.7
1.448
7.2
6.7
−60 −40 −20
0
20
40
60
80
1.398
−60 −40 −20
100 120 140
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Dead−Time, Vctrl = 0.75 V w/
E Config (tDT,E,2) vs. Junction Temperature
Figure 10. Vctrl Threshold CrM to DCM Mode
w/ E Config (Vctrl,th,E) vs. Junction
Temperature
0.656
0.636
0.655
0.616
0.635
VSKIP−L (V)
VSKIP−H (V)
20
TJ, JUNCTION TEMPERATURE (°C)
0.675
0.615
0.595
0.596
0.576
0.556
0.575
0.536
0.555
−60 −40 −20
0
20
40
60
80
100 120 140
0.516
−60 −40 −20
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Vcrtl Pin SKIP Level, Vctrl Rising
(VSKIP−H) vs. Junction Temperature
Figure 12. Vcrtl pin SKIP Level, Vctrl Falling
(VSKIP−L) vs. Junction Temperature
12.0
14.0
11.5
13.5
11.0
13.0
VDRV,high (V)
VDRV,low (V)
0
10.5
10.0
9.5
12.5
12.0
11.5
9.0
11.0
8.5
10.5
8.0
−60 −40 −20
0
20
40
60
80
100 120 140
10.0
−60 −40 −20
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. DRV Pin Level for VCC = VCC,off +
200 mV (10−kW Resistor between DRV and
GND) (VDRV,low) vs. Junction Temperature
Figure 14. DRV Pin Level @ VCC = 30 V (RL =
33 kW & CL = 1 nF) (VDRV,high) vs. Junction
Temperature
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10
NCP1602
TYPICAL CHARACTERISTICS
23.6
2.56
22.6
21.6
2.52
IEA1 (mA)
VREF (Vbg Post) (V)
2.54
2.50
2.48
19.6
18.6
17.6
2.46
16.6
2.44
−60 −40 −20
0
20
40
60
80
15.6
−60 −40 −20
100 120 140
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Feedback Voltage Reference (VREF)
vs. Junction Temperature
Figure 16. Error Amplifier Current Capability,
Sourcing (IEA1) vs. Junction Temperature
−16
290
−17
270
−18
250
230
−19
GEA (mS)
IEA2 (mA)
20.6
−20
−21
210
190
170
−22
150
−23
130
−24
−60 −40 −20
0
20
40
60
80
110
−60 −40 −20
100 120 140
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Error Amplifier Current Capability,
Sinking (IEA2) vs. Junction Temperature
Figure 18. Error Amplifier Transconductance
(GEA) vs. Junction Temperature
1200
280
1100
1000
tWDG(os) (ms)
tWDG (ms)
230
180
130
900
800
700
600
500
80
−60 −40 −20
0
20
40
60
80
100 120 140
400
−60 −40 −20
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Watch Dog Timer Duration (tWDG)
vs. Junction Temperature
Figure 20. Watch Dog Timer Duration in
“OverStress” Situation (tWDG(OS)) vs. Junction
Temperature
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11
NCP1602
TYPICAL CHARACTERISTICS
13.4
4.55
4.45
4.35
ton,HL(E) (ms)
ton,LL(E) (ms)
12.9
12.4
11.9
4.25
4.15
4.05
3.95
3.85
11.4
−60 −40 −20
0
20
40
60
80
3.75
−60 −40 −20
100 120 140
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Maximum On Time, avg(VCS) = 0.9 V
& Vctrl Maximum (CrM) & Low Line for
E Version (ton,LL,E) vs. Junction Temperature
Figure 22. Maximum On Time, avg(VCS) = 2.8 V
& Vctrl Maximum (CrM) & High Line for
E Version (ton,HL,E) vs. Junction Temperature
655
400
380
635
360
VUVPL (mV)
VUVPH (mV)
340
615
595
320
300
280
260
575
240
555
−60 −40 −20
220
200
−60 −40 −20
0
20
40
60
80
100 120 140
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. UVP Threshold, VFB Increasing
(VUVPH) vs. Junction Temperature
Figure 24. UVP Threshold, VFB Decreasing
(VUVPL) vs. Junction Temperature
400
1.878
380
1.858
360
1.838
340
320
VHL (V)
VUVPL(HYST) (mV)
0
300
280
1.818
1.798
1.778
260
1.758
240
220
200
−60 −40 −20
1.738
0
20
40
60
80
100 120 140
1.718
−60 −40 −20
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. UVP Threshold Hysteresis
(VUVPL(HYST)) vs. Junction Temperature
Figure 26. Comparator Threshold for Line
Range Detection, avg(VCS) Rising, (VHL) vs.
Junction Temperature
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12
NCP1602
1.47
0.475
1.45
0.425
1.43
0.375
1.41
0.325
VHLhys (V)
VLL (V)
TYPICAL CHARACTERISTICS
1.39
1.37
0.275
0.225
1.35
0.175
1.33
0.125
1.31
−60 −40 −20
0
20
40
60
80
0.075
−60 −40 −20
100 120 140
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. Comparator Threshold for Line
Range Detection, avg(VCS) Falling, (VLL) vs.
Junction Temperature
Figure 28. Comparator Hysteresis for Line
Range Detection, (VHL(hyst)) vs. Junction
Temperature
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13
NCP1602
Detailed Operating Description
Introduction
NCP1602 is designed to optimize the efficiency of your
PFC stage throughout the load range. In addition, it
incorporates protection features for rugged operation. More
generally, NCP1602 is ideal in systems where
cost−effectiveness, reliability, low stand−by power and high
efficiency are key requirements:
• Valley Synchronized Frequency Fold−back:
NCP1602 is designed to drive PFC boost stages in
so−called Valley Synchronized Frequency Fold−back
(VSFF). In this mode, the circuit classically operates in
Critical conduction Mode (CrM) when Vctrl exceeds a
programmable value. When the Vctrl is below this
preset level, NCP1602 linearly reduces the frequency
down to about 33 kHz before reaching the SKIP
threshold voltage (SKIP Mode versions [B**] and
[D**]). VSFF maximizes the efficiency at both nominal
and light load. In particular, stand−by losses are
reduced to a minimum. Similarly to FCCrM
controllers, an internal circuitry allows near−unity
power factor even when the switching frequency is
reduced.
• SKIP Mode (Versions [B**] and [D**]):
to further optimize the efficiency, the circuit skips
cycles at low load current when Vctrl reaches the SKIP
threshold voltage. This is to avoid circuit operation
when the power transfer is particularly inefficient at the
cost of current distortion. This SKIP function is not
present on versions [A**] and [C**]).
• Low Start−up Current and large VCC range ([**A] &
[**B] versions): The start−up consumption of the
circuit is minimized to allow the use of
high−impedance start−up resistors to pre−charge the
VCC capacitor. Also, the minimum value of the UVLO
hysteresis is 6 V to avoid the need for large VCC
capacitors and help shorten the start−up time without
the need for too dissipative start−up elements. The
[**C] & [**D] version is preferred in applications
where the circuit is fed by an external power source
(from an auxiliary power supply or from a downstream
converter). Its maximum start−up level (11.25 V) is set
low enough so that the circuit can be powered from a
12−V rail. After start−up, the high VCC maximum rating
allows a large operating range from 9.5 V up to 30 V.
• Fast Line / Load Transient Compensation (Dynamic
Response Enhancer): Since PFC stages exhibit low
loop bandwidth, abrupt changes in the load or input
voltage (e.g. at start−up) may cause excessive over or
under−shoot. This circuit limits possible deviations
from the regulation level as follows:
♦ NCP1602 linearly decays the power delivery to zero
when the output voltage exceeds 105% of its desired
•
•
level (soft OVP). If this soft OVP is too smooth and
the output continues to rise, the circuit immediately
interrupts the power delivery when the output
voltage is 107% above its desired level.
♦ NCP1602, dramatically speeds−up the regulation
loop when the output voltage goes below 95.5% of
its regulation level. This function is enabled only
after the PFC stage has started−up to allow normal
soft−start operation to occur.
Safety Protections: Permanently monitoring the input
and output voltages, the MOSFET current and the die
temperature to protect the system from possible
over−stress making the PFC stage extremely robust and
reliable. In addition to the OVP protection, the
following methods of protection are provided:
♦ Maximum Current Limit: The circuit senses the
MOSFET current and turns off the power switch if
the set current limit is exceeded. In addition, the
circuit enters a low duty−cycle operation mode when
the current reaches 150% of the current limit as a
result of the inductor saturation or a short of the
bypass diode.
♦ Under−Voltage Protection: This circuit turns off
when it detects that the output voltage is below 12%
of the voltage reference (typically). This feature
protects the PFC stage if the ac line is too low or if
there is a failure in the feedback network (e.g., bad
connection).
♦ Brown−Out Detection: The circuit detects low ac
line conditions and stops operation thus protecting
the PFC stage from excessive stress.
♦ Thermal Shutdown: An internal thermal circuitry
disables the gate drive when the junction
temperature exceeds 150°C (typically). The circuit
resumes operation once the temperature drops below
approximately 100°C (50°C hysteresis).
Output Stage Totem Pole: NCP1602 incorporates a
−0.5 A / +0.8 A gate driver to efficiently drive most
TO220 or TO247 power MOSFETs.
NCP1602 Operation Modes
As mentioned, NCP1602 PFC controller implements a
Valley Synchronized Frequency Fold−back (VSFF) where:
♦ The circuit operates in classical Critical conduction
Mode (CrM) when Vctrl exceeds a programmable
value Vctrl,th,* .
♦ When Vctrl is below this Vctrl,th,* , the NCP1602
linearly reduces the operating frequency down to
about 33 kHz
♦ When Vctrl reaches Vcrtl minimum value or the Vctrl
SKIP mode threshold, the system works in low
frequency burst mode.
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14
NCP1602
High Current
No delay è CrM
Low Current
The next cycle is
delayed
Timer delay
Lower Current
Longer dead−time
Timer delay
Figure 29. Valley Switching Operation in CrM and DCM Modes
As illustrated in Figure 29, under high load conditions, the
boost stage is operating in CrM but as the load is reduced, the
controller enters controlled frequency discontinuous
operation.
To further reduce the losses, the MOSFET turns on is
stretched until its drain−source voltage is at its valley. The
end of the dead time is synchronized with the drain−source
ringing.
Valley Synchronized Frequency Foldback (VSFF)
a/ Valley Synchronized (VS)
Dead−Time (DT)
Zero Current Detection
DRV
DRV
Ramp for DT Control
DT
200−us
WATCHDOG
Vctrl
VCTRL
DEAD TIME
GENERATOR
END OF DEMAG
SENSING
DRV
DEMAG
SENSING
DRV
Clock Generation
ZCD
ZCD TIMER
CS/ZCD
Vcs int
DRV
CSZCD
BUFFER
CLK
END OF DEAD TIME
SYNCHRONIZATION
DRV
Figure 30. Valley Synchronized Turn−on Block Diagram
by the simulation results of Figure 31. When the Line
voltage and inductor current are very low, or when the
amplitude of the drain voltage gets too low (in the case of
long dead times), the turn−on of the power MOSFET is no
longer synchronized with the drain valley but will start
exactly at the end of a programmed dead time looks to the
ZCD TIMER block.
If no demagnetization is sensed the power MOSFET will
be turned−on after a watchdog timing of 200−ms.
Valley Synchronized is the first half of the VSFF system.
Synchronizing the Turn−on with the drain voltage valley
maximizes the efficiency at both nominal and light load
conditions. In particular, the stand−by losses are reduced to
a minimum. The synchronization of Power MOSFET
Turn−on (rising edge of CLK signal) with drain voltage
valley is depicted on Figure 30. This method avoids system
stalls between valleys. Instead, the circuit acts so that the
PFC controller transitions from the n valley to (n+1) valley
or vice versa from the n valley to (n−1) cleanly as illustrated
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15
NCP1602
350
300
250
200
3rd Valley
Drain Source Voltage
(50 V/div)
4th Valley
150
100
50
−0
2. 54
VREF,DT
2. 52
2. 5
Ramp + Vffctl
(20mV/div)
2. 48
2. 46
2. 44
2. 42
10
8
6
DRV
(2 V/div)
4
2
2
1. 8
1. 6
1. 4
1. 2
1
0. 8
0. 6
0. 4
0. 2
0
−0. 2
Inductor Current
(100 mA/div)
385. 69
385. 695
385. 7
385. 705
385. 71
Time (5 uSecs /div)
/
Figure 31. Clean Transition Without Hesitation Between Valleys
b/ Frequency Foldback (FF)
Frequency Foldback is the second half of the VSFF system.
When Vctrl falls below an option−programmable Vctrl,th,*
threshold, the NCP1602 enters DCM and linearly reduces
the operating frequency down to about 33 kHz by adding a
dead−time after the end of inductor demagnetization. The
end of the dead−time is synchronized with the valley in the
tON
Iind
t DEMAG
drain voltage, hence the name Valley Synchronized (VS).
The lower the Vctrl value, the longer the dead−time.
The Frequency Foldback (FF) system adjusts the on−time
versus tDT (see Figure 32) and the output power in order to
ensure that the instantaneous mains current is in phase with
the mains instantaneous voltage (creating a PF=1).
Ipeak ,max
0
Tsw
CLK
DT
t DT
DRV
time
Figure 32. NCP1602 Clock, Dead Time and tON Waveforms
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16
NCP1602
from CrM to DCM mode is named Vctrl,th, * (see Table 6) and
the Vctrl threshold for transitioning from DCM to CrM mode
is Vctrl,th ,* + 40 mV.
When the load is at its maximum (the maximum Vctrl
value and inductor peak current limitation is not triggering),
the controller runs in CrM mode and the frequency
(@Vin =Vin,max ) has its minimum value. As we start
decreasing the output power, the Vctrl voltage decreases, the
switching frequency (@Vin =Vin,max ) increases and the
controller stays in CrM mode until Vctrl reaches a threshold
voltage named Vctrl,th,* . From this point, continuing to
reduce the output power makes the controller to continue
increase the dead time (TDT ) after the end of
demagnetization resulting in a DCM conduction mode and
a switching frequency decrease (Frequency Foldback).
When the output power is reduced and we enter DCM
mode, the switching frequency decreases down to a value
given by the following equation, which is valid down to
before entering SKIP mode. This minimum DCM frequency
value is dominated by the dead time value, tON plus tDEMAG
being negligible versus tDT that has reached is maximum
value tDT,max .
FSW, DCM, min +
NCP1602 Skip Mode (Active on Versions [B**] and
[D**], Disabled on Versions [A**] and [C**])
The circuit also skips cycles when Vctrl decreases towards
VSKIP−L threshold. A comparator monitors the Vctrl voltage
and inhibits the drive when Vctrl is lower than the SKIP
Mode threshold VSKIP−L. Switching resumes when Vctrl
exceeds VSKIP−H threshold. The skip mode capability is
disabled whenever the PFC stage is not in nominal operation
(as dictated by the PFCOK signal − see PFCOK Operation
section).
NCP1602 On−time Modulation and VTON Processing
Circuit
Let’s analyze the ac line current absorbed by the PFC
boost stage. The initial inductor current at the beginning of
each switching cycle is always zero. The coil current ramps
up when the MOSFET is on. The slope is (Vin/L) where L is
the coil inductance. At the end of the on−time (t1 ), the
inductor starts to demagnetize. The inductor current ramps
down until it reaches zero. The duration of this phase is (t2 ).
In some cases, the system enters then the dead−time (t3 ) that
lasts until the next clock is generated.
One can show that the ac line current is given by:
1
1
[
(eq. 1)
t DT,max ) t ON ) t DEMAG
t DT,max
In order to have, depending on customer application, a
different limitation of the maximum switching frequency
(@Vin=Vin,max), as well as different Vctrl thresholds for
CrM to DCM boundary, different product versions are made
available (see Table 2).
I in + V in
CrM−DCM and DCM−CrM Transition Hysteresis
Hesitation of the system to transition between the modes
CrM and DCM may have a consequences on inductor
current shape and distort the mains current, resulting in a bad
PF value when the operating point is at the CrM−DCM
boundary.
To avoid such undesired behavior, a 40−mV hysteresis is
added on Vctrl threshold. The Vctrl threshold for transitioning
2T L
T + t1 ) t2 ) t3
Iind
L1
D1
Vout
Cbulk
Q1
DRV
Rsense
time
Iind
t1
(eq. 3)
is the switching period and Vin is the ac line rectified voltage.
In light of this equation, we immediately note that Iin is
proportional to Vin if [t1.(t1+t2)/T] is a constant.
Cin
Ipeak,max
(eq. 2)
Where
Vin
Vin
t 1ǒt 1 ) t 2Ǔ
t2
t3
time
0
T
Figure 33. PFC Boost Converter and Inductor Current in DCM
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17
NCP1602
The input current is then proportional to the input voltage.
Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CrM
case. This condition is just a particular case of this
functioning where (t3=0), which leads to (t1+t2=T) and
(Vton=Vregul). That is why the NCP1602 automatically
adapts to the conditions and transitions from DCM and CrM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
The NCP1602 operates in voltage mode. As portrayed by
Figure 33 & Figure 34, the MOSFET on−time t1 is set by a
dedicated circuitry monitoring Vctrl and dead−time tDT
ensuring [t1.(t1+t2)/T] is constant and as a result making Iin
proportional to Vin (PF=1)
On−time t1 is also called ton and its maximum value ton,max
is obtained when Vctrl is at maximum level. The internal
circuitry makes ton,max at High Line condition (HLINE) to
be 3 times the ton,max at Low Line condition (LLINE)
(low−pass filtered internal CS−pin voltage is compared to
VHL and VLL for deciding whether we are in HLINE or in
LLINE). Two other values of ton,max are offered as options.
Ich
PWM
Comparator
Turns off
MOSFET
Closed when
output low
Cramp
Vton
Vton
Ramp Voltage
PWM output
Figure 34. PWM Circuit and Timing Diagram
NCP1602 Regulation Block and Output Voltage Control
The VF value is 0.5 V typically.
The regulated output voltage Vout uses a reference voltage
that has two possible values based on mains voltage level.
For LLINE = 0 VREF = 2.5 V and for LLINE = 1
VREF = VREF2 = 1.6 V so the output voltage will have for
example a 390 V value for Highline (LLINE = 0) and a
250 V value for Lowline (LLINE = 1).
This feature that can be named “two level boost follower”
is not active by default but can be enabled by OTP
programming.
Given the low bandwidth of the regulation loop, abrupt
variations of the load, may result in excessive over or
under−shoot. Over−shoot is limited by the Over−Voltage
Protection connected to FB pin ( Feedback).
NCP1602 embeds a “Dynamic Response Enhancer”
circuitry (DRE) that contains under−shoots. An internal
comparator monitors the FB pin voltage (VFB ) and when
VFB is lower than 95.5% of its nominal value, it connects a
200−mA current source to speed−up the charge of the
A trans−conductance error amplifier (OTA) with access to
the inverting input and output is provided. It features a
typical trans−conductance gain of 200 mS and a maximum
current capability of ±20 mA. The output voltage of the PFC
stage is typically scaled down by a resistors divider and
monitored by the inverting input (pin FB). Bias current is
minimized (less than 500 nA) to allow the use of a high
impedance feed−back network. However, it is high enough
so that the pin remains in low state if the pin is not connected.
The output of the error amplifier is brought to pin VCTRL
for external loop compensation. Typically a type−2 network
is applied between pin VCTRL and ground, to set the
regulation bandwidth below about 20 Hz and to provide a
decent phase boost.
The swing of the error amplifier output is limited within
an accurate range:
• It is forced above a voltage drop (VF ) by some circuitry.
• It is clamped not to exceed 4.0 V + the same VF voltage
drop.
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18
NCP1602
• Output DRE Level: Vout,dre = 95.5% x Vout,nom
• Output Soft OVP Level: Vout,sovp = 105% x Vout,nom
• Output Fast OVP level: Vout,fovp = 107% x Vout,nom
compensation network. Effectively this appears as a 10x
increase in the loop gain.
The circuit also detects overshoot and immediately
reduces the power delivery when the output voltage exceeds
105% of its desired level.
The error amplifier OTA and the OVP, UVP and DRE
comparators share the same input information. Based on the
typical value of their parameters and if (Vout,nom) is the
output voltage nominal value (e.g., 390 V), we can deduce:
• Output Regulation Level: Vout,nom
Current Sense and Zero Current Detection
NCP1602 is designed to monitor the current flowing
through the power switch during On−time for detecting over
current and overstress and to monitor the power MOSFET
drain voltage during demagnetization time and dead time in
order to generate the ZCD signal.
DRAIN
DRV
ZCD
Vcc
DEMAG
& LINE SENSE
VSNS
R cs1
CS/ZCD pin
Vcsint
C cs
CSZCD
BUFFER
R cs2
OVERSTRESS
OVS
BLANKING
OVERSTRESS
TIMER
VOVS,REF
DRV
DRV
SOURCE
OCP
OCP
BLANKING
VOCP,REF
DRV
Figure 35. Current Sense, Zero Current Detection Blocks and Vin Sense
Current Sense
Current sense, zero current detection and Vin sense are
using the CS/ZCD pin voltage as depicted in the electrical
schematic of Figure 35.
The power MOSFET current I is sensed during the TON
phase by the resistor Rsense inserted between the MOSFET
source and ground (see Figure 36). During TON phase Rcs1
and Rcs2 are almost in parallel and the signal Rsense .I is equal
to the voltage on pin CS.
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19
NCP1602
D
R cs1
Rcs1
CS
R dson
CS
D,S
C cs
I
C cs
R cs2
Rcs2
S
I
R sense
R sense
Figure 36. Current Sensing during the TON Phase
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20
NCP1602
By default, the Brown−out flag is set High (BONOK=1),
meaning that Vin ,sensed thru CSZCD pin and Vsns (Vsns is
a low−pass filtered scaled down Vin) internal signal (see
Figure 1), when higher than internal reference voltage
VBOH will set the brown−out flag to zero (BONOK=0) and
allow the controller to start. After BONOK is set to zero, and
switching activity starts, the Vin continues to be sensed thru
CSZCD pin and when Vsns falls under Brown−out internal
reference voltage VBOL for 50 ms, BONOK flag will be set
to 1. After BONOK flag will be set to 1, drive is not disabled,
instead, a 30−mA current source is applied to VCTRL pin to
gradually reduce Vctrl . As a result, the circuit only stops
pulsing when the STATICOVP function is activated (that is
when Vctrl reaches the SKIP detection threshold). At that
moment, the circuit stops switching. This method limits any
risk of false triggering.
For an application w/ Vaux (not using the Drain),
Brown−out options ([C**] and [D**]) are not be allowed
and the UVP will act like a brown−in. The reason is that
before controller starts switching, the Vout voltage is equal
to Vmains,rms and sensed by FB pin and compared to UVP
high internal reference voltage VUVPH.
The input of the PFC stage has some impedance that leads
to some sag of the input voltage when the input current is
large. If the PFC stage suddenly stops while a high current
is drawn from the mains, the abrupt decay of the current may
make the input voltage rise and the circuit detect a correct
line level. Instead, the gradual decrease of Vcontrol avoids a
line current discontinuity and limits the risk of false
triggering.
Vsns internal voltage is also used to sense the line for
feed−forward. A similar method is used:
• The Vsns internal pin voltage is compared to a 1.801−V
reference.
• If Vsns exceeds 1.801V, the circuit detects a high−line
condition and the loop gain is divided by three (the
internal PWM ramp slope is three times steeper)
• Once this occurs, if Vsns remains below 1.392 V for
25 ms, the circuit detects a low−line situation (500−mV
hysteresis).
During the On−time and after a 200−ns blanking time, an
OCP (Over Current Protection) signal is generated by an
OCP comparator, comparing (VCS = VCS2 ) to a 500−mV
internal reference.
When RsenseIds_max = VCS = VCS2 = 500 mV we get:
I ds_max +
V ocp
R sense
(eq. 4)
When VCS exceeds the 500−mV internal reference
threshold, the OCP signal turns high to reset the PWM latch
and forces the driver low. The 200−ns blanking time
prevents the OCP comparator from tripping because of the
switching spikes that occur when the MOSFET turns on.
Zero Current Detection
The CS pin is also designed to receive, during tDEMAG and
tDT, a scaled down (divided by 138) power MOSFET drain
voltage that will be used for Zero Current Detection. It may
happen that the MOSFET turns on while a huge current
flows through the inductor. As an example such a situation
can occur at start−up when large in−rush currents charge the
bulk capacitor to the line peak voltage. Traditionally, a
bypass diode is generally placed between the input and
output high−voltage rails to divert this inrush current. If this
diode is accidently shorted, the demagnetization will be
impossible and cycle after cycle the inductor current will
increase so the MOSFET will also see a high current when
it turns on. In both cases, the current can be large enough to
trigger the OverStress (OVS) comparator. In this case, the
“OverStress” signal goes high and disables the driver for an
800−ms delay. This long delay leads to a very low duty−ratio
operation in case of “OverStress” fault in order to limit the
risk of overheating.
When no signal is received that triggers the ZCD
comparator to indicate the end of inductor demagnetization,
an internal 200−ms watchdog timer initiates the next drive
pulse. At the end of this delay, the circuit senses the CS/ZCD
pin impedance to detect a possible grounding of this pin and
prevent operation.
Brown−Out Detection (Versions [C**] and [D**])
For an application w/o Vaux (using the Drain) and using
Brown−out options ([C**] and [D**]) the Brown−out
feature will use the High and Low Brown−out levels.
Brown−out options ([C**] and [D**]) must not be used on
an application using Vaux as these options are not designed
to work in this case.
At startup, the circuit is in High−line state (“LLINE” Low”)
and then Vsns will be used to determine the High−Line or
Low−Line state.
The line range detection circuit allows more optimal loop
gain control for universal (wide input mains) applications.
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21
NCP1602
CSint
VSNS
VREF,LLINE
DEMAG
&
LINE SENSE
CSZCD
BUFFER
1.801 V if LLINE=1
1.392 V otherwise
DRV
VREF,BONOK
0.819 V if BONOK=1
0.737 V otherwise
Figure 37. Input Line Sense Monitoring
Two−Level Boost Follower Line Level Dependent
tDEMAG the value of Vout , thru the RCS1 , RCS2 divider bridge
connected to the pin CS and compares it to an OVP2 voltage
reference VREF,OVP2 . Because it is not possible to adjust the
VREF,OVP2 reference to Rfb1 & Rfb2 that programs the Vout
value, it has been decided to set VREF,OVP2 and RCS1 , RCS2
in order to get OVP2 triggering for Vout voltages much
higher than for OVP condition (e.g. OVP2 goes high when
Vout goes higher than 438 V)
For Vout = 438 V for OVP2 and given a KCS value equal
to 1/138 (KCS = RCS2 / (RCS1 + RCS2), this gives
VREF,OVP2 = 3.175 V for the threshold voltage to which is
compared to the CS voltage during toff . When VCS goes
above VREF,OVP2 threshold of the OVP2 comparator
(100 mV hysteresis), and after a 1−ms leading edge blanking
time, the OVP2 flag is latched and will stop the switching by
resetting the main PWM latch. The OVP2 latch is reset each
800 ms.
The Two−Level Boost Follower feature is disabled by
default, but it is available on product versions [**B] &
[**D].
When the feature is enabled, the controller will regulate its
output voltage Vout to a value dependent on the sensed line
level. The regulated ouput voltage Vout uses a reference
voltage that has two possible values based on mains voltage.
For LLINE = 0 VREF = 2.5 V and for LLINE = 1
VREF = VREF2 = 1.6 V so the output voltage will have for
example a 390 V value for Highline (LLINE = 0) and a
250 V value for Lowline (LLINE = 1).
In order for the Two−Level Boost Follower Line Level
Dependent feature to work OK with the the Brown−in
feature at startup, the controller will always start with
VREF = 2.5 V and then, once Brown−in validated and
switching started, the sensed line level will determine the
VREF value to be used and hence the Vout value.
Two−level Boost Follower
Thermal Shut−Down (TSD)
An internal thermal circuitry disables the circuit gate drive
and keeps the power switch off when the junction
temperature exceeds 150°C. The output stage is then
enabled once the temperature drops below about 100°C
(50°C hysteresis).
The temperature shutdown remains active as long as the
circuit is not reset, that is, as long as VCC is higher than a reset
threshold.
In order to minimize the voltage between Vin and Vout for
avoiding the degradation of power efficiency, the internal
voltage references can be managed versus the line voltage
level condition (LLINE = 0 for High Line or LLINE = 1 for
Low Line).
If the “Two−level Boost Follower” feature is activated (by
default it is not activated), this will result in a regulated Vout
voltage for Low Line condition being 0.64 times the
regulated Vout voltage for High Line condition.
Output Drive Section
OFF Mode
The output stage contains a totem pole optimized to
minimize the cross conduction current during high
frequency operation. Its high current capability (−500 mA /
+800 mA) allows it to effectively drive high gate charge
power MOSFET.
As previously mentioned, the circuit turns off when one
of the following faults is detected:
• Incorrect feeding of the circuit (“UVLO” high when
VCC <VCC(off), VCC(off) equating 9 V typically).
• Excessive die temperature detected by the thermal
shutdown
• Under−Voltage Protection
• Brown−Out Fault and STATICOVP (see Figure 2)
Second Over−Voltage Protection
On top of the existing overvoltage protection, a second
and redundant overvoltage protection named OVP2 has
been added. This overvoltage protection, senses, during
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22
NCP1602
shorted; a pin can be grounded or badly connected. Such
open/short situations are generally required not to cause fire,
smoke nor big noise. NCP1602 integrate functions that ease
meet this requirement. Among them, we can list:
• Floating feedback pin
A special internal circuitry detects the floating feedback
pin and stops the operation of the IC.
• Fault of the GND connection
If the GND pin is not connected, internal circuitry
detects it and if such a fault is detected for 200 ms, the
circuit stops operating.
• Detection the CS/ZCD pin improper connection
If the CS/ZCD pin is floating or shorted to GND it is
detected by internal circuitry and the circuit stops
operating.
• Boost or bypass diode short
The controller addresses the short situations of the
boost and bypass diodes (a bypass diode is generally
placed between the input and output high−voltage rails
to divert this inrush current). Practically, the overstress
protection is implemented to detect such conditions and
forces a low duty−cycle operation until the fault is gone.
Generally speaking, the circuit turns off when the
conditions are not proper for desired operation. In this mode,
the controller stops operating. The major part of the circuit
sleeps and its consumption is minimized.
More specifically, when the circuit is in OFF state:
• The drive output is kept low
• All the blocks are off except:
♦ The UVLO circuitry that keeps monitoring the VCC
voltage and controlling the start−up current source
accordingly.
♦ The TSD (thermal shutdown)
♦ The Under−Voltage Protection (“UVP”)
♦ The brown−out circuitry
• Vctrl is grounded so that when the fault is removed, the
device starts−up under the soft start mode (version XB).
• The internal “PFCOK” signal is grounded.
• The output of the “Vton processing block” is grounded
Failure Detection
When manufacturing a power supply, elements can be
accidentally shorted or improperly soldered. Such failures
can also happen to occur later on because of the components
fatigue or excessive stress, soldering defaults or external
interactions. In particular, adjacent pins of controllers can be
Refer to application note ANDxxxx for more details.
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23
NCP1602
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE U
D
H
ÉÉÉ
ÉÉÉ
6
E1
1
NOTE 5
5
2
4
L2
GAUGE
PLANE
E
3
L
M
b
SEATING
PLANE
DETAIL Z
e
0.05
C
A
c
A1
DETAIL Z
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
3.20
0.95
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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NCP1602/D