eorex SDRAM Timing Mode Register Set Cycle CLK tIS tIH /CS tIS tIH tIS tIH tIS tIH tIS tIH /RAS /CAS /WE A0 to A11 BA0,1 Register set data Rev.01 eorex SDRAM Timing Interleaved Bank Read ( BL=4, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK /CS tRC tRC tRC tRC /RAS tRP tRAS tRAS tRAS tRP tRP tRAS /CAS /WE BA0 ‘ Low ‘ BA1 tRCD A10 RAa A0 toA9 ,A11 RAa tRCD tRCD RBb CAw RBb tRCD RAc CBx RBd RAc CAy RAe RBd CBz RAe ‘ Low ‘ DQM ‘ High ‘ CKE tAC DQ tAC aw0 aw1 aw2 aw3 Bank #1 Active bx0 tRRD tRRD Bank #0 tAC Read Active Precharge Read bx1 bx2 bx3 cy0 tRRD Active Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 Read Precharge tAC cy1 cy2 cy3 tRRD Active Precharge Read Active eorex SDRAM Timing Interleaved Bank Read ( BL=4, CL=3, Auto Precharge ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK /CS tRC tRC tRC tRC /RAS tRAS tRP tRAS tRAS tRP tRP tRAS /CAS /WE BA0 ‘ Low ‘ BA1 tRCD tRCD A10 RAa RBb A0 to A9 ,A11 RAa CAw RBb DQM tRCD tRCD RAc CBx RBd RAc CAy RAe RBd CBz RAe ‘ Low ‘ ‘ High ‘ CKE tAC DQ Bank #1 Active tAC bx0 aw0 aw1 aw2 aw3 tRRD Bank #0 tAC bx1 bx2 tRRD Read cy0 cy1 tRRD Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 cy3 AP AP Read cy2 tRRD Active AP Active bx3 tAC Read Active Active Read 23 eorex SDRAM Timing Interleaved Bank Read ( BL=8, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK /CS tRC tRC tRC /RAS tRAS tRP tRP tRAS tRAS tRP /CAS /WE BA0 ‘ Low ‘ BA1 tRCD tRCD A10 RAa A0 to A9 ,A11 RAa tRCD RAc RBb CAx RBb CBy RAc CA z DQM CKE tAC tAC aX0 aX1 aX2 aX3 aX4 aX5 aX6 by0 by1 DQ tRRD Bank #0 tAC Active Bank #1 tRRD Read Precharge by4 by5 by6 by7 Precharge Active Read Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 Active Read Precharge cz0 23 eorex SDRAM Timing Interleaved Bank Read ( BL=8, CL=3, Auto Precharge ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK tRC /CS tRC /RAS tRAS tRP tRAS tRAS tRP /CAS /WE BA0 ‘ Low ‘ BA1 tRCD A10 tRCD RBb RAa A0 to A9 ,A11 RAa tRCD CAx RBb RAc CBy RAc CAz DQM CKE tAC tAC aX0 aX1 aX2 aX3 aX4 aX5 aX6 aX7 by0 by1 DQ tRRD Bank #0 tAC Active Bank #1 by4 by5 by6 tRRD Read AP Active Read Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 Active Read AP cz0 23 eorex SDRAM Timing Interleaved Bank Write ( BL=8 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK /CS tRC /RAS tRAS tRP tRAS tRP /CAS tRCD tRCD tRCD /WE BA0 BA1 ‘ Low ‘ A10 RAa A0 to A9 ,A11 RAa RBb CAx RBb RAc CBy RAc CAz DQM CKE aX0 aX1 DQ aX4 aX5 aX6 aX7 by0 by1 by2 by3 tRRD Bank #0 Active Bank #1 by4 by5 by6 by7 cz0 cz1 cz2 tRRD Write Precharge Active Write Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 Active Write Precharge eorex SDRAM Timing Interleaved Bank Write ( BL=8, Auto Precharge ) CLK /CS tRC /RAS tRAS tRP tRAS tRAS tRP /CAS /WE BA0 ‘ Low ‘ BA1 tRCD A10 tRCD RAa A0 to A9 ,A11 RAa tRCD RBb CAa RBb RAb RAc CBy CAz DQM CKE aX0 aX1 DQ aX4 aX5 aX6 aX7 by0 by1 by2 by3 tRRD tRRD Bank #0 Active Bank #1 by4 by5 by6 by7 cz0 cz1 cz2 AP Write Active Write Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 Active AP Write eorex SDRAM Timing Page Mode Read /Write ( BL=8, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK /CS tRAS tRP /RAS /CAS /WE BA0 ‘ Low ‘ BA1 tRCD A10 RAa A0 to A9 ,A11 RAa CAy CAx DQM ‘ High ‘ CKE tDPL tAC aX0 aX1 aX2 aX3 aX4 aX5 DQ Q Bank #0 Active Q Q Q Q Q Read ay0 ay1 ay2 ay3 ay4 D D Write Bank #1 Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 D D D Precharge 23 eorex SDRAM Timing Page Mode Read ( BL = 4, CL = 3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK tCCD tCCD tCCD /CS tRAS tRP tRP tRAS /RAS /CAS /WE BA0 ‘ Low ‘ BA1 tRCD tRCD A10 RAa RBb A0 to A9 ,A11 RAa CAl RBb DQM CBx CAy CAn CBz ‘ Low ‘ ‘High ‘ CKE tAC tAC al0 DQ al1 al2 tAC tAC tAC al3 bx0 bx1 av0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 tRRD Rev.01 22 23 eorex SDRAM Timing Auto Precharge Read ( BL=4, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK /CS tRC tRC /RAS tRAS tRP tRAS tRP /CAS /WE BA0 BA1 ‘ Low ‘ tRCD A10 RAa A0 to A9 ,A11 RAa DQM tRCD RAb RAb CAw CAx ‘ Low ‘ ‘ High ‘ CKE tAC DQ Bank #0 tAC aw0 Active Read bx0 aw1 aw2 aw3 AP Active Bank #1 Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 Read bx1 AP bx2 bx3 23 eorex SDRAM Timing Auto Precharge Write ( BL=4 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK /CS tRC tRC /RAS tRAS tRP tRAS tRP /CAS /WE BA0 BA1 ‘ Low ‘ tRCD tRCD A10 RAa RAb A0 to A9 ,A11 RAa RAb DQM RAc RAc CAx ‘ Low ‘ CKE DQ Bank #0 aw0 Active Write bx0 aw1 aw2 aw3 AP Active Bank #1 Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 Write bx1 bx2 bx3 AP Active 23 eorex SDRAM Timing Burst Read and Single Write ( BL=4, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK /CS /RAS /CAS tRCD /WE BA0 ‘ Low ‘ BA1 A10 RBa A0 to A9 ,A11 RBa CBv CBw CBx CBy CBz DQM ‘ High ‘ CKE tAC DQ tAC av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 Q Q Q Q D D D Q Q Q Q Bank #0 Bank #1 Active Read Read Single Write Bank #2 ( Idle ) Bank #3 ( Idle ) Rev.01 22 23 eorex SDRAM Timing Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK /CS /RAS /CAS /WE BA A10 RAa A0 to A9 ,A11 RAa DQM RAa CAa RAa ‘ Low ‘ CKE tIS tIS tIS aX0 aX1 DQ aX2 tIS aX3 Pre-charge Standby Power Down Mode Active Standby Power Down Mode Rev.01 CAx 23 eorex SDRAM Timing Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK tRP tRC tRC /CS /RAS /CAS /WE BA0 BA1 A10 A0 to A9 ,A11 DQM ‘ High ‘ CKE DQ All Banks Precharge Auto Refresh (Arbitary Cycle) Auto Refresh Rev.01 22 23 eorex SDRAM Timing Self Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ CLK /CS tRP /RAS /CAS /WE BA0 BA1 A10 A0 to A9 ,A11 DQM tIS tIS ~ ~ CKE tIS ~ ~ DQ tRC All Banks Precharge Self Refresh Cycle Self Refresh Entry No Operation Cycle Arbitrary Cycle Rev.01