MOSEL MSS1506

MOSEL VITELIC
MOSEL
MSS1506
VOICE ROM
DECEMBER
Features
Single power can operate at 2.4 V through 6V.
Current output could drive 8 ohm speaker with a
transistor, Vout could drive buzzer directly.
The voice content is stored up to 15 seconds and
can be separated to 64 sections.
Duration of each section can be different.
Mute is available for each section up to 48
seconds totally.
A Forever Play function is available.
Four addressing interface modes are provided for
versatile applications: CPU, Stand alone, Ring
Trigger and Table Trigger.
Stand alone mode:
8 sections can be accessed by 8 trigger input
pins individually.
Table trigger mode:
a. A phrase is accessed by TG0, low active.
b. This phrase is composed of 16 elements
contiguously as the table content.
c. These 16 elements are chosen from 8 sections.
d. Section is located and numbered by 0 through 7.
Ring trigger mode:
a. A section-by-section phrase is accessed by TG0,
low active.
b. This phrase is composed of 16 element (section)s
contiguously as the table content.
c. Each single trigger plays next one element (section)
following above sequence.
d. These 16 elements are chosen from 8 sections.
e. Section is located and numbered by 0 through 7.
CPU addressing mode:
a. 64 sections can be accessed by 6 address bits
with enable strobe trigger.
b. Section is located and numbered by 0 through 63.
c. The address bit is high true.
Mask option for either retriggerable output or not.
Mask option for either Level or Edge trigger type.
For all four modes, retrigger action restarts playing
from the beginning.
One BUSY output signal is available.
Automatic power down function(selected by external
input, pwr).
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General Description
The MSS1506 is a single-chip CMOS LSI ROM that can memorize voice up to 15 seconds using MOSEL
qualified coding method (MPCM).
Four addressing interfaces are provided: CPU mode, Stand Alone mode, Ring Trigger mode and Table Trigger
mode for versatile applications. The voice content can be stored separatly into 64 or 8 or 16 sections or 1
phrase with arbitary length. With minimum external components, this chip can be applied to various
application. Customer voice is edited and programmed into ROM by changing one mask during fabrication.
Block Diagram
9
OSC
CLOCK
2
VOICE
GENERATOR
MPCM
8
BUFFERS
DECODER
DATA ROM
7
ADDRESS GENERATOR and
4
VOUT2
VOUT1
COUT
BUSY
KEY SWITCH INTERFACE
1
VDD
18
TG0
17
TG1
16
TG2
15
TG3
14
13
TG4
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1
TG5
12
TG6/E1
11
TG7/E2
3
PWR
10
VSS
PID216C 12/93
MOSEL VITELIC
MSS1506
Absolute Maximum Rating
Rating
Symbol
VDD ~ VSS
Unit
-0.5 ~ +7.0
VIN (TG)
all input pins
VOUT (STS)
all output pins
V
VSS -0.3 < V IN < VDD+0.3
V
VSS <VOUT < VDD
V
T (Operating)
-10 ~ +60
C
T (Storage)
-55 ~ +125
C
Pad Description
Pad No.
Signal Name
I/O
Function
1
V DD
Power
2
OSC
I
Oscillator input
Positive power supply
3
PWR
I
Active high for non-power down, Internal pull low
4
BUSY
O
Busy signal output, active high
5
NC
6
NC
7
8
C OUT
O
O
Audio signal current output (for speaker)
Audio signal voltage output (for buzzer)
9
Audio signal voltage output (for buzzer)
VOUT1
V OUT2
O
10
VSS
Power
11
E2, TG7
NC/I
No connection (RT,TT);Trigger 7, active low( SA);
Enable 2, active low (CPU)
12
E1, TG6
NC/I
No connection (RT,TT);Trigger 6, active low (SA);
Enable 1, active high (CPU)
13
TG5
NC/I
14
15
16
17
TG4
TG3
TG2
TG1
NC/I
NC/I
NC/I
NC/I
18
TG0
I
Negative power supply
No connection (RT, TT); Trigger 1 ~ 5, active low
(SA); address 1 ~ 5, high true (CPU)
Trigger 0, active low (RT TT, SA);
address 0 high true (CPU)
AC Characteristics
Parameter
Trigger pulse width
Min.
10
TW
TH
Write Enable pulse width
300
80
TP
TR
Power rise up time
Power Ripple width
Timing
TT
Trigger address hold time
Typ.
Max.
ns
ns
1
1
2
Unit.
ms
ms
ms
PID216C 12/93
MSS1506
MOSEL VITELIC
DC Characteristics
Symbol
ISB
Parameter
Stand by
Supply
Current
V IH
V IL
Input Voltage
(T0~T7, E1,E2, PWR)
I IL
IOH
I OL
IOH
IOL
ICO
∆F/F
4
-0.3
O/P Current
VOUT1 ,VOUT2
5
0.3
4.5
0
0
-15
20
Input Current
for PWR
Drive
Sink
-8
8
Output Current
(BUSY)
Output Current (C OUT )
∆F/F
Max.
200
Input Current
(T0~T7)
IIH
Typ.
1
Operating
IOP
IIH
I IL
Min.
0
-13
-18
18
13
2
4
Unit
µA
VDD = 4.5V, I/O Open
V
VDD = 4.5V
µA
VDD = 4.5V
µA
VDD = 4.5V
V DD = 4.5V, VO/P = 0V
V DD = 4.5V, VO/P = 4.5V
mA
VDD = 4.5V, VO/P = 0V
mA
Frequency Stability
3.6
5
mA
%
Frequency Variation
10
%
2.4
Condition
3
V DD = 4.5V, V O/P = 4.5V
VDD = 4.5V
[F OSC (4.5V) - F OSC (4V)]/Fosc(4.5V)
VDD = 4.5V, ROSC = 1.2MΩ
Timing Diagram
I.1. Acceptable Power On Signal & Ripple
TP
TR
90% V DD
VDD
90% V DD
10% V DD
VSS = 0.0 V
II.1. Stand Alone mode, No Retrigger function, Edge Trigger Mask, low active, single trigger input
TGn
AUDIO
Sn
Sn
BUSY
II.2. Stand Alone mode, No Retrigger function, Level Trigger Mask, low active, single trigger input
TGn
AUDIO
Sn
Sn
Sn
BUSY
III.1. Stand Alone mode, Retrigger function, Edge Trigger Mask, low active, single trigger input
TGn
AUDIO
Sn
Sn
Sn
BUSY
3
PID216C 12/93
MSS1506
MOSEL VITELIC
III.1. Stand Alone mode, Retrigger function, Level Trigger Mask, low active, single trigger input
TGn
AUDIO
Sn
Sn
Sn
Sn
BUSY
IV. 1. Stand Alone mode, No Retrigger function, Edge Trigger Mask, low active, two non - overlap trigger inputs
TG1
TG2
S2
AUDIO
S1
BUSY
IV. 2. Stand Alone mode, No Retrigger function, Level Trigger Mask, low active, two non - overlap trigger inputs
TG1
TG2
AUDIO
S1
S2
S1
BUSY
IV. 3. Stand Alone mode, Retrigger function, low active, two non - overlap trigger inputs
TG1
TG2
AUDIO
S2
S2
S1
BUSY
V. 4. Retrigger function , Trigger Mask = Edge or Level, Overlap trigger inputs
TG1
TG2
AUDIO
S2
S1
BUSY
V. Table Trigger Mask
TG
AUDIO
T0
T1
T(LAST)
T2
BUSY
NOTE: Tn = nth element of Table content.
4
PID216C 12/93
MSS1506
MOSEL VITELIC
VII. Ring Trigger mode, Edge Trigger Mask
TG
AUDIO
T0
T1
T(LAST)
T2
T0
BUSY
VIII. Ring Trigger mode, Level Trigger Mask
a. When trigger is shorter than a whole section output
b. When trigger is longer than a whole section output
TG
AUDIO
T1
T0
T2
T3
T4
BUSY
IX. Power keep function
PWR
Address
n
m
l
E2
Sn
AUDIO
Sm
Sl
X. Mask as Retrigger / CPU mode ( 6 - bit address )
TG7 / E2
TG6
TW
High
TG5
Low
TG4
Low
TG3
TH
TG2
TG1
TG0
AUDIO
S09
S06
BUSY
XI. Debounce Time
TG
TT
AUDIO
Note: 1. AUDIO means cout, vout1, vout2.
2. TG0 ~ TG5, E1/TG6, E2/TG7 are all internal pull high.
3. For standalone mode, TG0 ~ TG7 are used as section trigger input (active low).
4. Every retrigger action will reload address and play the audio output from the beginning.
5. In CPU mode to avoid unwanted noise caused by abrupt change between different sections
of messages, it is recommended to program PWR pin to high (VDD) during voice processing.
5
PID216C 12/93
MSS1506
MOSEL VITELIC
Application Circuit
1.Typical Application
a.Standalone
R1
b.CPU Mode
VCC
OSC
TG0
TG1
TG2
TG3
TG4
TG5
TG6
TG7
R1
S
COUT
S
TG0 COUT
T
µP
T
Address
Bus
TG5
R2
R2
E1
E2
BUSY
VSS
VSS
R1
VCC
OSC
R1
VCC
VCC
OSC
OSC
VOUT1
TG0
TG1
TG2
TG3
TG4
TG5
TG6
TG7
TG0 VOUT1
VOUT2
µP
PIEZO
BUZZER
Address
Bus
VOUT2
PIEZO
BUZZER
TG5
E1
E2
BUSY
VSS
VSS
2.Parallel Application
(Could extend depth to desired section number in parallel arrangement)
R1
R1
VCC
OSC
VCC
OSC
TG0 COUT
TG1
TG2
TG3
TG4
TG5
TG6
TG7
TG0 COUT
TG1
TG2
TG3
TG4
TG5
TG6
TG7
VSS
VSS
6
S
T
R2
PID216C 12/93
MSS1506
MOSEL VITELIC
R1
R1
VCC
OSC
TG0
TG1
TG2
TG3
TG4
TG5
TG6
TG7
VOUT1
VCC
OSC
VOUT1
TG0
TG1
TG2 VOUT2
TG3
TG4
TG5
TG6
TG7
VOUT2
VSS
PIEZO
BUZZER
VSS
3.Cascade Application
(Could extend length to desired length in serial arrangement)
R1
R1
VCC
OSC
VCC
OSC
TG
BUSY
COUT
S
TG
C1
COUT
VSS
T
VSS
R2
R2 = open is better.
R1
R1
VCC
OSC
VCC
OSC
TG
BUSY
VOUT1
TG
VOUT1
C1
VOUT2
VOUT2
VSS
VSS
PIEZO
BUZZER
Note: 1. R1 = 1.2 M Ω, C1 = 0.1 µf, T(transistor) = ß > 150, R2 =open, S(speaker) = 1/4 w, 8 Ω; all typical.
2. Piezo buzzer resonant frequency being around 1K Hz in recommended.
3. Input switch could be replaced by CDS.
4. Cout,Vout1,Vout2 are tristate during stand by state.
5. Both cascade and parallel application are applied in CPU mode.
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PID216C 12/93
MSS1506
MOSEL VITELIC
Bonding Diagram
Pad No. Designation
1
VDD
2
OSC
3
PWR
4
BUSY
5
NC
6
NC
7
C OUT
8
V OUT1
9
V OUT2
10
VSS
11
TG7
12
TG 6
13
TG 5
14
TG4
15
TG3
16
TG 2
17
TG 1
18
TG 0
18
17
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Note: Substrate is VDD
MOSEL
No. 1, R&D I Rd., Hsinchu Science-Based Industrial Park, Hsinchu,
Taiwan, R.O.C.
TEL:886-35-77-0055
FAX:886-35-77-2788
3910 North First street, San Jose, CA 95134-1501 U.S.A.
TEL:1-408-433-6000
FAX:1-408-433-0952
Reserves the right to make changes to above content and product without notice .
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