WINBOND W986416CH

W986416CH
1M x 16 bit x 4 Banks SDRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V±0.3V power supply
Up to 166 MHz clock frequency
1,048,576 words x 4 banks x 16 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8 , and full page
Burst read, Single Writes Mode
Byte data controlled by UDQM and LDQM
Power-Down Mode
Auto-Precharge and controlled precharge
4k refresh cycles / 64ms
Interface: LVTTL
Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W986416CH is a high speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x
16 bits. Using pipelined architecture and 0.20um process technology, W986416CH delivers a data bandwidth of up to 332M
bytes per second (-6). For different application, W986416CH is sorted into four speed grades: -6, -7, -75 and -8H. The -6 parts
can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3 specification. The -75 parts can run up to PC133/CL3
specification. The -8H parts can run up to 125Mhz/CL3 or PC100/CL2 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated
by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock
cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst
to maximize its performance. W986416CH is ideal for main memory in high performance applications.
Key Parameters
Symbol
tCK
tAC
tRP
tRCD
ICC1
ICC4
ICC6
Description
Clock Cycle Time
Access Time from CLK
Precharge to Active Command
Active to Read/Write Command
Operation Current ( Single bank )
Burst Operation Current
Self-Refresh Current
min/max
min
max
min
min
max
max
max
Revision 1.2
-6
6ns
5ns
18ns
18ns
80mA
130mA
1mA
-7
7ns
5.4ns
20ns
20ns
65mA
115mA
1mA
-75(PC133)
7.5ns
5.4ns
20ns
20ns
65mA
115mA
1mA
-8H(PC100)
8ns
6ns
20ns
20ns
60mA
110mA
1mA
Publication Release Date: June, 1999
-1-
W986416CH
1M x 16 bit x 4 Banks SDRAM
BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
RAS
CONTROL
SIGNAL
GENERATOR
COMMAND
CAS
DECODER
COLUMN DECODER
COLUMN DECODER
A10
MODE
REGISTER
A0
CELL ARRAY
BANK #0
ROW DECODER
ROW DECODER
WE
CELL ARRAY
BANK #1
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
A9
A11
BS0
BS1
DMn
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ15
REFRESH
COUNTER
COLUMN
COUNTER
UDQM
LDQM
CELL ARRAY
BANK #2
COLUMN DECODER
ROW DECODER
ROW DECODER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE:
The cell array configuration is 4096 * 256 * 16.
Revision 1.2
Publication Release Date: June, 1999
-2-
W986416CH
1M x 16 bit x 4 Banks SDRAM
Pin Assignment
Pin Number
23 ~ 26, 22,
29 ~35
20, 21
Pin Name
A0~ A11
Function
Address
BS0, BS1
Bank Select
2, 4, 5, 7, 8,
10, 11, 13,
42, 44, 45,
47, 48, 50,
51, 53
19
DQ0 ~
DQ15
Data Input/
Output
CS#
Chip Select
18
RAS#
17
CAS#
16
39, 15
WE#
UDQM/
LDQM
Row Address
Strobe
Column
Address Strobe
Write Enable
input/output
mask
38
37
CLK
CKE
Clock Inputs
Clock Enable
1, 14, 27
28, 41, 54
3, 9, 43, 49
VCC
VSS
VCCQ
6, 12, 46, 52
VSSQ
36, 40
NC
Power ( +3.3 V )
Ground
Power ( + 3.3 V
) for I/O buffer
Ground for I/O
buffer
No Connection
Description
Multiplexed pins for row and column address.
Row address: A0 ~ A11. Column address: A0 ~ A7.
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the clock,
RAS#, CAS# and WE# define the operation to be executed.
Referred to RAS#
Referred to RAS#
The output buffer is placed at Hi-Z (with latency of 2) when DQM
is sampled high in read cycle. In write cycle, sampling DQM
high will block the write operation with zero latency.
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE
is low, Power Down mode, Suspend mode, or Self Refresh
mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from VCC, used for output buffers to improve
noise.
Separated ground from VSS, used for output buffers to improve
noise.
No connection
Revision 1.2
Publication Release Date: June, 1999
-3-
W986416CH
1M x 16 bit x 4 Banks SDRAM
Pin Assignment (Top View)
VCC
1
54
VSS
DQ0
2
53
DQ15
VCCQ
3
52
VSSQ
DQ1
4
51
DQ14
DQ2
5
50
DQ13
VSSQ
6
49
V CC Q
DQ3
7
48
DQ12
DQ4
8
47
DQ11
VCCQ
9
46
VSSQ
DQ5
10
45
DQ10
DQ6
11
44
DQ9
VSSQ
12
43
VCCQ
DQ7
13
42
DQ8
VCC
14
41
VSS
LDQM
15
40
NC
UDQM
WE
16
39
CAS
17
38
CLK
RAS
18
37
CKE
CS
19
36
NC
BS0
20
35
A11
BS1
21
34
A9
A10/AP
22
33
A8
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VCC
27
28
VSS
Revision 1.2
Publication Release Date: June, 1999
-4-
W986416CH
1M x 16 bit x 4 Banks SDRAM
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
NOTES
Input, Output Voltage
-0.3~VCC+0.3
V
1
VCC,VCCQ
Power Supply Voltage
-0.3~4.6
V
1
TOPR
Operating Temperature
0~70
°C
1
TSTG
Storage Temperature
-55~150
°C
1
VIN,VOUT
TSOLDER
ITEM
260
°C
1
PD
Soldering Temperature(10s)
Power Dissipation
1
W
1
IOUT
Short Circuit Output Current
50
mA
1
RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70°C )
SYMBOL
VCC
VCCQ
PARAMETER
MIN
TYP
MAX
UNIT
NOTES
Power Supply Voltage
3.0
3.3
3.6
V
2
Power Supply Voltage (for I/O Buffer)
3.0
3.3
3.6
V
2
VIH
Input High Voltage
2.0
-
VCC+0.3
V
2
VIL
Input Low Voltage
-0.3
-
0.8
V
2
Note: VIH(max) = VCC/VCCQ+1.2V for pulse width < 5ns
VIL(min) = VSS/VSSQ-1.2V for pulse width < 5ns
CAPACITANCE (VCC=3.3V, Af = 1MHz, Ta=25°C)
SYMBOL
CI
CO
PARAMETER
MIN
MAX
UNIT
Input Capacitance (A0 to A11, BS0 ,BS1, CS, RAS, CAS, WE, DQM, CKE)
-
4
pf
Input Capacitance (CLK)
-
4
pf
Input/Output capacitance
-
6.5
pf
Note: These parameters are periodically sampled and not 100% tested.
Revision 1.2
Publication Release Date: June, 1999
-5-
W986416CH
1M x 16 bit x 4 Banks SDRAM
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc=3.3V±0.3V, Ta=0° to 70°C Notes:5, 6, 7, 8)
SYMBOL
PARAMETER
tRC
tRAS
tRCD
tCCD
tRP
tRRD
tWR
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a)
to
Read/Write(b)Command
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
CL*=2
CL*=3
CLK Cycle Time
CL*=2
CL*=3
CLK High Level width
CLK Low Level width
Access Time from CLK
CL*=2
CL*=3
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
tCK
tCH
tCL
tAC
tOH
tHZ
tLZ
tSB
tT
tDS
tDH
tAS
tAH
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
-6
MIN
60
42
18
1
18
12
10
6
10
6
2.5
2.5
-7
MAX
10000
1000
1000
MIN
63
42
20
1
20
14
10
7
10
7
2.5
2.5
6
5
2
2
0
0
0.3
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
6
6
10
10000
1000
1000
6
5.4
2.5
2.5
0
0
0.3
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
12
MAX
7
7
10
64
14
-75(PC133)
MIN
MAX
65
45
10000
20
1
20
15
10
7.5
10
1000
7.5
1000
2.5
2.5
6
5.4
2.7
2.7
7.5
0
0
7.5
0.3
10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
15
-8H(PC100)
MIN
MAX
68
48
10000
20
1
20
20
10
8
10
1000
8
1000
3
3
6
6
3
3
8
0
0
8
0.5
10
2
1
2
1
2
1
2
1
64
16
* CL=CAS Latency
Revision 1.2
Publication Release Date: June, 1999
-6-
UNIT
Ns
Cycle
ns
ms
ns
W986416CH
1M x 16 bit x 4 Banks SDRAM
DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, Ta=0°~70°C)
SYMBOL
-6
MAX.
1 bank operation
ICC1
80
65
60
3
CKE = VIH
ICC2
60
45
40
3
CKE = VIL (Power Down mode)
ICC2P
1
1
1
3
CKE = VIH
ICC2S
7
6
6
CKE = VIL (Power Down mode)
ICC2PS
1
1
1
CKE = VIH
ICC3
65
50
45
CKE= VIL (Power Down mode)
ICC3P
3
3
3
ICC4
130
115
110
3.4
ICC5
155
110
100
3
ICC6
1
1
1
ITEMS
OPERATING CURRENT
tCK=min , tRC=min
Active Precharge command cycling
without Burst operation
STANDBY CURRENT
tCK=min , CS#=VIH
VIH/L=VIH(min)/VIL(max)
Bank : inactive state
STANDBY CURRENT
CLK=VIL , CS#=VIH
VIH/L=VIH(min)/VIL(max)
BANK : inactive state
NO OPERATING CURRENT
tCK=min
CS#=VIH(min)
BANK : active state (4 banks)
-7/-75(PC133) -8H(PC100)
MAX.
MAX.
UNIT
NOTES
mA
BURST OPERATING CURRENT
tCK = min
Read / Write command cycling
AUTO REFRESH CURRENT
tCK = min
Auto Refresh command cycling
SELF REFRESH CURRENT
Self Refresh mode
CKE = 0.2V
ITEM
INPUT LEAKAGE CURRENT
( 0V ≤ VIN ≤ VCC , all other pins not under test = 0V )
OUTPUT LEAKAGE CURRENT
( Output disable , 0V ≤ VOUT ≤ VCCQ )
LVTTL OUTPUT ″H″ LEVEL VOLTAGE
( IOUT = -2mA )
LVTTL OUTPUT ″L″ LEVEL VOLTAGE
( IOUT = 2mA )
SYMBOL
MIN.
MAX.
UNIT
II(L)
-5
5
µA
IO(L)
-5
5
µA
VOH
2.4
-
V
VOL
-
0.4
V
Revision 1.2
NOTES
Publication Release Date: June, 1999
-7-
W986416CH
1M x 16 bit x 4 Banks SDRAM
NOTES:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of
tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open. The
W986416CH-6/-7/-75/-8H is tested with 50pF output load.
5. Power up sequence is further described in the "Functional Description" section.
6. AC TESTING CONDITIONS
Output Reference Level
Output Load
1.4V/1.4V
The W986416CH-6/-7/-75/-8H is tested with
50pF output load. (See diagram below)
2.4V/0.4V
2ns
1.4V
Input Signal Levels
Transition Time (Rise and Fall) of Input Signal
Input Reference Level
1.4 V
50 ohms
output
Z = 50 ohms
50pF
AC TEST LOAD
7 Transition times are measured between VIH and VIL.
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
Revision 1.2
Publication Release Date: June, 1999
-8-
W986416CH
1M x 16 bit x 4 Banks SDRAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth
table for the operation commands.
Table 1 Truth Table
( note (1) , (2) )
command
Device state
CKEn-1
CKEn
DQM
BS0,1
A10
A11,
A9-0
CS
RAS
Bank Active
Idle
Bank Precharge
Any
Precharge All
Any
Write
Active (3)
Write with Autoprecharge
Active (3)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
L
H
H
x
x
x
x
x
x
x
x
x
x
x
H
L
H
H
L
L
L
H
H
H
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
L
H
v
v
x
v
v
v
v
v
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
v
L
H
L
H
L
H
v
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
v
x
x
v
v
v
v
v
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
x
H
L
x
H
L
x
x
L
L
L
H
H
H
H
L
H
H
x
L
L
x
H
x
x
H
x
x
H
x
x
Read
Active (3)
Read with Autoprecharge
Active (3)
Mode Register Set
Idle
No - Operation
Any
Burst Stop
Active (4)
Device Deselect
Any
Auto - Refresh
Idle
Self - Refresh Entry
Idle
Self Refresh Exit
idle
(S.R.)
Clock suspend Mode Entry
Active
Power Down Mode Entry
Idle
Active (5)
Clock Suspend Mode Exit
Active
Power Down Mode Exit
Any
(power down)
Data write/Output Enable
Active
Data Write/Output Disable
Active
CAS
WE
H
H
H
L
L
L
L
L
H
H
x
L
L
x
H
x
x
H
x
x
H
x
x
H
L
L
L
L
H
H
L
H
L
x
H
H
x
x
x
x
x
x
x
x
x
x
Notes: (1) v= valid x = Don't care L= Low Level H= High Level
(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
Revision 1.2
Publication Release Date: June, 1999
-9-
W986416CH
1M x 16 bit x 4 Banks SDRAM
Functional Description
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be
followed to guarantee the device being preconditioned to each user specific needs.
During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held
in the "NOP" state. The power up voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. After power up,
an initial pause of 200us is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause
period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register.
An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure
proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a
precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode
Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address
input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command
may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for
Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to
RAS# activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write
operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be
precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between
successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum
time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time
(tRRD). The maximum time that each bank can be held active is specified as tRAS(max).
Read and Write Access Modes
After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low
at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation
(WE high), or a write operation (WE low). The address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate
command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using
the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access
operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or
between active banks on every clock cycle.
Revision 1.2
Publication Release Date: June, 1999
- 10 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst
(sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the
next page explain the address sequence of interleave mode and sequence mode.
Burst Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied
on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each
subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses
are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on
the outputs until the CAS latency from the interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance
state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the
write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the
DQ bus and DQM masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is
interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the
programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs
must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention.
When the Read Command is activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write
Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other
burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the
rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst
read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any
residual data from the burst write cycle will be ignored.
Revision 1.2
Publication Release Date: June, 1999
- 11 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Table 2 Address Sequence of Sequential Mode
DATA
Access Address
Burst Length
Data 0
n
BL= 2 (disturb address is A0)
Data 1
n+1
No address carry from A0 to A1
Data 2
n+2
BL= 4 (disturb addresses are A0 and A1)
Data 3
n+3
No address carry from A1 to A2
Data 4
n+4
Data 5
n+5
Data 6
n+6
Data 7
n+7
BL= 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
. Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the
device. The disturb address is varied by the Burst Length as shown in Table 2.
. Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in the
sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Access
Address
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
Revision 1.2
Burst Length
BL = 2
BL = 4
BL = 8
Publication Release Date: June, 1999
- 12 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Auto-Precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During autoprecharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically
before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the
end of the scheduled burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore,
use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge
operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge
command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with AutoPrecharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst
write cycle. This delay is referred to as Write tDPL. The bank undergoing auto-precharge can not be reactivated until tDPL and tRP are
satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge Command, the
interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when
CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge
each bank separately or all banks simultaneously. Three address bits, A10, A12, and A13, are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated
before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must
be greater than or equal to the Precharge time (tRP).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.
All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to
keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except
CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation
and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of
4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the
power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down
mode longer than the Refresh period (tREF) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next
rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCES(min) +
tCK(min).
Revision 1.2
Publication Release Date: June, 1999
- 13 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from
registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS,
CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is
still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought
high, the RAS, CAS, and WE signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the
banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any
clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the
time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high
to when Clock Suspend mode is exited.
Revision 1.2
Publication Release Date: June, 1999
- 14 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Timing Waveform
Command Input Timing
tCL
tCK
tCH
VIH
CLK
VIL
tT
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
tT
tCMH
CS
RAS
CAS
WE
A0-A11
BS0, 1
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
CKE
Revision 1.2
Publication Release Date: June, 1999
- 15 -
tCMS
W986416CH
1M x 16 bit x 4 Banks SDRAM
Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A11
BS0, 1
tAC
tAC
tLZ
tHZ
tOH
tOH
Valid
Data-Out
Valid
Data-Out
DQ
Read Command
Burst Length
Revision 1.2
Publication Release Date: June, 1999
- 16 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Control Timing of Input Data
(Word Mask)
CLK
tCMS
tCMH
tCMH
tCMS
DQM
tDS
tDH
tDS
tDH
Valid
Data-in
DQ0 -15
tDS
Valid
Data-in
tDH
tDS
Valid
Data-in
tDH
Valid
Data-in
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tDH
tDS
tDH
tCKS
CKE
tDS
DQ0 -15
Valid
Data-in
tDS
Valid
Data-in
tDH
tDS
Valid
Data-in
tDH
Valid
Data-in
Control Timing of Output Data
(Output Enable)
CLK
tCMS
tCMH
tCMH
tCMS
DQM
tAC
tLZ
tOH
Valid
Data-Out
DQ0 -15
tAC
tHZ
tAC
tOH
tOH
Valid
Data-Out
tAC
tOH
Valid
Data-Out
OPEN
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tAC
tOH
DQ0 -15
tAC
tAC
tOH
tOH
Valid
Data-Out
Valid
Data-Out
Revision 1.2
tAC
tOH
Valid
Data-Out
Publication Release Date: June, 1999
- 17 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Mode Register Set Cycle
tRSC
CLK
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
CS
RAS
CAS
WE
tAS
A0-A10
BS
tAH
Register
set data
A0
A1
Burst Length
A2
A3
Addressing Mode
A4
A5
CAS Latency
A2
0
0
0
0
1
1
1
1
A6
A7
A0
"0"
(Test Mode)
A8
"0"
Reserved
WriteA0
Mode
A9
A0
A10
"0"
A0
A11
"0"
BS0
"0"
BS1
A0
"0"
A0
Reserved
A0
A0
A1
A0
0
A0
0
A0
1
A0
1
A0
0
A0
0
A0
1
A0
1
A0
0
1
0
1
0
1
0
1
A0
A3
A0
0
A0
1
A6
0
0
0
0
1
A0
A5
A0
0
A0
0
A0
1
A0
1
A0
0
A0
A9
A0
0
A0
1
Revision 1.2
next
command
BurstA0
Length
Sequential
A0
Interleave
A0
1
A0
1
A0
2
A0
2
A0
A0
4
4
A0
A0
8
8
Reserved
A0
A0
Reserved
FullA0
Page
Addressing
A0 Mode
A0
Sequential
Interleave
A0
A4
0
1
0
1
0
CAS A0
Latency
Reserved
A0
Reserved
A0
2
A0
3
Reserved
Single Write Mode
Burst read and
A0 Burst write
Burst read and
A0 single write
Publication Release Date: June, 1999
- 18 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Operating Timing Example
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
1
0
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRAS
tRP
tRP
tRAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
tRCD
RBb
CBx
RBb
CAw
tRCD
RAc
RBd
RAc
CAy
RAe
RBd
RAe
CBz
DQM
CKE
aw0
DQ
tRRD
Bank #0 Active
Bank #1
tAC
tAC
tAC
aw1
aw2
aw3
bx0
Precharge
Active
bx2
bx3
cy0
tRRD
tRRD
Read
bx1
Active
cy1
cy2
cy3
tRRD
Precharge
Read
Precharge
Read
tAC
Active
Read
Bank #2
Idle
Bank #3
Revision 1.2
Publication Release Date: June, 1999
- 19 -
Active
W986416CH
1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRAS
tRP
tRP
tRAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
tRCD
RBb
CAw
tRCD
CBx
RBb
RAe
RBd
RAc
CAy
RAc
CBz
RBd
RAe
DQM
CKE
tAC
DQ
tRRD
Active
Bank #0
Bank #1
aw1
aw2
aw3
bx0
Active
AP*
Active
bx1
bx2
bx3
tAC
cy0
tRRD
tRRD
Read
tAC
tAC
aw0
Read
cy2
cy3
dz0
tRRD
Read
AP*
cy1
AP*
Active
Active
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2
Publication Release Date: June, 1999
- 20 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length=8, CAS Latency=3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9
A11
RAa
tRCD
tRCD
RAc
RBb
CAx
RBb
CBy
RAc
CAz
DQM
CKE
tAC
DQ
tAC
ax0
ax1
tRRD
Bank #0
Active
ax3
ax4
ax5
ax6
by0
by1
by4
by5
by6
by7
CZ0
tRRD
Read
Precharge
Bank #1
ax2
tAC
Precharge
Active
Read
Active
Read
Precharge
Bank #2
Idle
Bank #3
Revision 1.2
Publication Release Date: June, 1999
- 21 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Read (Burst Length=8, CAS Latency=3, Autoprecharge)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
t RC
CS
tRC
RAS
tRAS
tRP
tRAS
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
tRCD
tRCD
A10
A0-A9
RBb
RAa
RAa
CAx
RAc
RBb
RAc
CBy
CAz
DQM
CKE
tCAC
tCAC
ax0
DQ
ax1
ax2
tRRD
Bank #0
Active
ax4
ax5
ax6
ax7
by0
by1
by4
by5
by6
CZ0
tRRD
AP*
Read
Active
Bank #1
ax3
tCAC
Read
Active
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2
Publication Release Date: June, 1999
- 22 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Write (Burst Length=8)
(CLK = 100 MHz)
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRAS
tRAS
tRP
tRP
tRAS
CAS
tRCD
tRCD
tRCD
WE
BS0
BS1
RBb
A10
RAa
A0-A9,
A11
RAa
CAx
RAc
RBb
CBy
RAc
CAz
DQM
CKE
ax0
DQ
ax1
ax4
ax5
ax6
ax7
by0
by1
tRRD
Bank #0
Active
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
Precharge
Write
Active
Bank #1
by2
Write
Active
Write
Precharge
Bank #2
Bank #3
Idle
Revision 1.2
Publication Release Date: June, 1999
- 23 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Interleaved Bank Write (Burst Length=8, Autoprecharge)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
RAS
tRP
tRAS
tRAS
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
tRCD
RBb
CAx
RAb
CBy
RBb
CAz
RAc
DQM
CKE
ax0
DQ
ax1
ax4
ax5
ax6
ax7
by0
by1
tRRD
Bank #0 Active
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
AP*
Write
Active
Bank #1
by2
Write
Active
Write
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2
Publication Release Date: June, 1999
- 24 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Page Mode Read (Burst Length=4, CAS Latency=3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tCCD
tCCD
tCCD
CS
tRAS
tRP
tRAS
tRP
RAS
CAS
WE
BS0
BS1
tRCD
A10
A0-A9,
A11
tRCD
RAa
RBb
RAa
RBb
CAI
CBx
CAy
CAm
CBz
DQM
CKE
tAC
a0
DQ
tAC
tAC
a1
a2
a3
bx0
bx1
Ay0
tAC
Ay1
Ay2
tAC
am0
am1
am2
bz0
bz1
bz2
bz3
tRRD
Bank #0 Active
Read
Active
Bank #1
Read
Read
Read
Precharge
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2
Publication Release Date: June, 1999
- 25 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Page Mode Read / Write (Burst Length=8, CAS Latency=3)
(CLK = 100 MHz)
0
1
2
3
5
4
6
7
8
9
11
10
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRAS
tRP
RAS
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
CAx
CAy
DQM
CKE
tAC
tWR
ax0
DQ
Q Q
Bank #0
Active
ax1
ax3
ax2
Q
Q
ax5
ax4
Q
Q
Read
ay1
ay0
D
D
Write
ay2
D
ay4
ay3
D
D
Precharge
Bank #1
Bank #2
Bank #3
Idle
Revision 1.2
Publication Release Date: June, 1999
- 26 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
AutoPrecharge Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
6
5
7
8
9
11
10
12
13
14
16
15
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
A10
RAa
A0-A9,
A11
RAa
tRCD
RAb
CAw
RAb
CAx
DQM
CKE
tAC
DQ
Bank #0
tAC
aw0
Active
Read
aw1
AP*
aw2
aw3
bx0
Active
Read
bx1
bx2
bx3
AP*
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2
Publication Release Date: June, 1999
- 27 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
AutoPrecharge Write (Burst Length = 4)
(CLK = 100 MHz)
CLK
0
1
2
3
5
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CS
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
3CK
A10
RAa
A0-A9,
A11
RAa
RAc
RAb
CAw
RAb
CAx
RAc
DQM
CKE
aw0
DQ
Bank #0
Active
Write
aw1
aw2
bx0
aw3
AP*
Active
Write
bx1
bx2
bx3
AP*
Active
Bank #1
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Revision 1.2
Publication Release Date: June, 1999
- 28 -
23
W986416CH
1M x 16 bit x 4 Banks SDRAM
AutoRefresh cycle
0
1
2
(CLK = 100 MHz)
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
tRP
tRC
t RC
CS
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
Revision 1.2
Publication Release Date: June, 1999
- 29 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
SelfRefresh Cycle
(CLK = 100 MHz)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
tCKS
tCKS
tSB
CKE
tCKS
DQ
tRC
Self Refresh Cycle
All Banks
Precharge
No Operation Cycle
Self Refresh
Entry
Arbitrary Cycle
Revision 1.2
Publication Release Date: June, 1999
- 30 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Burst Read and Single Write (Burst Lenght = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
6
5
7
8
9
11
10
12
13
14
15
16
17
18
19
21
20
22
CLK
CS
RAS
CAS
tRCD
WE
BS0
BS1
A10
RBa
A0-A9,
A11
RBa
CBv
CBw
CBx
CBy
CBz
DQM
CKE
tAC
tAC
DQ
av0
Q
Bank #0 Active
Bank #1
Bank #2
Bank #3
av1
Q
av2
av3
aw0
ax0
ay0
az0
az1
az2
az3
Q
Q
D
D
D
Q
Q
Q
Q
Read
Single Write Read
Idle
Revision 1.2
Publication Release Date: June, 1999
- 31 -
23
W986416CH
1M x 16 bit x 4 Banks SDRAM
PowerDown Mode
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS
A10
RAa
A0-A9
RAa
RAa
CAa
RAa
CAx
DQM
tSB
tSB
CKE
tCKS
tCKS
tCKS
DQ
ax0
Active
ax1
ax2
NOP Wrate
tCKS
ax3
Precharge
NOPActive
Precharge Standby
Power Down mode
Active Standby
Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Revision 1.2
Publication Release Date: June, 1999
- 32 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Autoprecharge Timing ( Read Cycle )
0
1
Read
AP
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
DQ
Act
t RP
Q0
( b ) burst length = 2
Command
Read
AP
Act
tRP
DQ
Q0
Q1
( c ) burst length = 4
Command
Read
AP
Act
tRP
DQ
Q0
Q1
Q2
Q3
( d ) burst length = 8
Command
Read
AP
Q0
DQ
Q1
Q2
Q3
Q4
Q5
Q6
Act
tRP
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read
AP
Act
tRP
Q0
DQ
( b ) burst length = 2
Command
Read
AP
Act
tRP
Q0
DQ
( c ) burst length = 4
Command
Read
Q1
AP
Act
t RP
Q0
DQ
Q1
Q2
Q3
( d ) burst length = 8
Command
Read
AP
Act
tRP
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Note )
Read
represents the Read with Auto precharge command.
AP
represents the start of internal precharging.
Act
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t RAS (min).
Revision 1.2
Publication Release Date: June, 1999
- 33 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Autoprecharge timing ( Write Cycle )
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Write
AP
Act
tWR
DQ
tRP
D0
( b ) burst length = 2
Command
Write
AP
Act
tWR
DQ
D0
tRP
D1
( c ) burst length = 4
Command
Write
AP
tWR
DQ
D0
D1
D2
Act
tRP
D3
( d ) burst length = 8
Command
Write
AP
tWR
DQ
(2) CAS Latency=3
( a ) burst length = 1
Command
D0
D1
Write
D2
( b ) burst length = 2
Command
D5
D6
D7
Act
tRP
D0
Write
AP
Act
tWR
DQ
D4
AP
tWR
DQ
D3
Act
tRP
D0
tRP
D1
( c ) burst length = 4
Command
Write
AP
Act
tWR
DQ
( d ) burst length = 8
Command
D0
D1
D2
tRP
D3
Write
AP
tWR
DQ
D0
D1
D2
D3
D4
D5
D6
Act
tRP
D7
Note )
Write
represents the Write with Auto precharge command.
AP
represents the start of internal precharging.
Act
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS(min) .
Revision 1.2
Publication Release Date: June, 1999
- 34 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Timing Chart of Read to Write cycle
In the case of Burst Length=4
0
1
2
3
4
5
D1
D2
D3
D0
D1
D2
D1
D2
D3
D1
D2
6
7
8
9
10
11
(1) CAS Latency=2
Read Write
( a ) Command
DQM
DQ
D0
( b ) Command
Read
Write
DQM
DQ
(2) CAS Latency=3
D3
Read Write
( a ) Command
DQM
D0
DQ
Read
( b ) Command
Write
DQM
D0
DQ
Note )
D3
The Output data must be masked by DQM to avoid I/O conflict
Revision 1.2
Publication Release Date: June, 1999
- 35 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Timing Chart of Write-to-Read cycle
In the case of Burst Length=4
0
1
2
3
4
5
6
7
8
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
9
10
(1) CAS Latency=2
( a ) Command
Write Read
DQM
DQ
( b ) Command
D0
Read
Write
DQM
DQ
D0
D1
(2) CAS Latency=3
( a ) Command
Write Read
DQM
DQ
( b ) Command
D0
Write
Read
DQM
DQ
D0
D1
Revision 1.2
Q3
Publication Release Date: June, 1999
- 36 -
11
W986416CH
1M x 16 bit x 4 Banks SDRAM
Timing chart of Burst Stop cycle ( Burst stop Command )
0
1
2
3
4
5
6
7
8
9
10
11
(3) Read cycle
( a ) CAS latency =2
Command
Read
BST
Q0
DQ
Q1
Q2
Q3
Q4
( b )CAS latency = 3
Command
Read
BST
Q0
DQ
(2) Write cycle
Command
DQ
Q1
Q2
Note )
Q4
BST
Write
D0
Q3
D1
BST
D2
D3
D4
represents the Burst stop command
Revision 1.2
Publication Release Date: June, 1999
- 37 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Timing chart of Burst Stop cycle ( Precharge Command )
In the case of Burst Lenght = 8
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a )CAS latency =2
Commad
Read
PRCG
Q0
DQ
Q1
Q2
Q3
Q4
( b )CAS latency = 3
Commad
Read
PRCG
Q0
DQ
Q1
Q2
Q3
Q4
(2) Write cycle
( a ) CAS latency =2
Commad
Write
PRCG
tWR
DQM
DQ
D0
D1
D2
D3
D4
( b )CAS latency = 3
Commad
PRCG
Write
tWR
DQM
DQ
D0
Note )
D1
PRCG
D2
D3
D4
represents the Precharge command
Revision 1.2
Publication Release Date: June, 1999
- 38 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
CKE/DQM Input timing ( Write cycle )
CLK cycle No.
1
2
3
D1
D2
D3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
D5
DQM MASK
D6
CKE MASK
(1)
CLK cycle No.
1
2
3
D1
D2
D3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
DQM MASK
D5
D6
5
6
7
D4
D5
D6
CKE MASK
(2)
CLK cycle No.
1
2
3
D1
D2
D3
4
External
CLK
Internal
CKE
DQM
DQ
CKE MASK
(3)
Revision 1.2
Publication Release Date: June, 1999
- 39 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
CKE/DQM Input timing ( Read cycle )
CLK cycle No.
1
2
3
4
Q1
Q2
Q3
Q4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Open
Open
(1)
CLK cycle No.
1
2
3
Q1
Q2
Q3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q4
Open
(2)
CLK cycle No.
1
2
Q1
Q2
3
4
5
6
7
Q4
Q5
Q6
External
CLK
Internal
CKE
DQM
DQ
Q3
(3)
Revision 1.2
Publication Release Date: June, 1999
- 40 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time ( Power down mode exit time ) is specified by t CKS(min) + t CK(min)
A ) tCK < tCKS(min)+t CK(min)
tCK
CLK
CKE
tCKS(min)+tCK(min)
NOP
Command
Command
Input Buffer Enable
B) tCK >= t CKS(min) + t CK (min)
tCK
CLK
tCKS(min)+tCK(min)
CKE
Command
Command
Input Buffer Enable
Note )
All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
NOP
Command
Represents the No-Operation command
Represents one command
Revision 1.2
Publication Release Date: June, 1999
- 41 -
W986416CH
1M x 16 bit x 4 Banks SDRAM
Package Dimension
54L TSOP (II)-400 mil
54
28
HE
E
1
27
e
b
C
D
L
A2
A
L1
A1
ZD
Y
SEATING PLANE
Controlling Dimension : Millimeters
DIMENSION
(MM)
DIMENSION
(INCH)
SYMBOL
MIN.
NOM.
0.05
NOM.
0.10
0.15
0.002
0.004
0.24
c
0.32
MAX.
0.047
1.00
A2
b
MIN.
1.20
A
A1
MAX.
0.006
0.039
0.40
0.009
0.15
0.012
0.006
0.016
D
22.12
22.22
22.62
0.871
0.875
0.905
E
10.06
10.16
10.26
0.396
0.400
0.404
HE
11.56
11.76
11.96
0.455
0.463
0.471
e
L
L1
0.80
0.40
0.50
0.60
0.016
0.80
Y
ZD
0.0315
0.020
0.024
0.032
0.004
0.10
0.028
0.71
Revision 1.2
Publication Release Date: June, 1999
- 42 -