9BIT 0.5MSPS DAC AL1213H FEATURES GENERAL DESCRIPTION The AL1213H is a CMOS 9Bit D/A converter for · Resolution : 9Bits general application. · Differential Linearity Error : ±0.16 LSB(TYP) This digital to analog converter consists of a R-2R · Maximum Conversion Rate : 0.5MSPS ladder block & an Op amp block. · Supply Voltage : 5V Its maximum conversion rate is 0.5MSPS. · Single Voltage Output : 0V~5V · Operation Temperature Range : 0°C~70°C TYPICAL APPLICATIONS · DVD · CDP · General purpose Digital to Analog Conversion FUNCTIONAL BLOCK DIAGRAM RSTRING LADDER SIGNAL SELECT D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] VREF DACCTL Rev 2.1 (Apr. 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD OP AMP AOUT AL1213H 9BIT 0.5MSPS DAC CORE PIN DESCRIPTION NAME I/O TYPE I/O TYPE ABBR I/O PAD PIN DESCRIPTION * AI : Analog Input * DI : Digital Input VDDA AP vdda Analog Power VSSA AG vssa Analog Ground * AO : Analog Output * DO : Digital Output * AP : Analog Power VDD DP vddd Digital Power VSS DG vssd Digital Ground * AB : Analog Bidirection port D[0] ~ D[8] DI picc_bb Digital Input Data * DB : Digital Bidirection port DACCTL DI picc_bb Signal Select signal VREF AI pia_bb Voltage Reference Top (5V) AOUT AO poa_bb Analog Voltage Output VBB AG vbb Analog Ground * AG : Anlalog Ground * DP : Digital Power * DG : Digital Ground * DB : Digital Sub Bias CORE CONFIGURATION VSS VDD VDDA VSSA VBB al1213h D[8:0] DACCTL SEC ASIC AOUT VREF 2 / 11 ANALOG AL1213H 9BIT 0.5MSPS DAC ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Typ Unit 5 V VRT 5.0 V VRB 0.0 V Digital Input Voltage HIGH Vinh 5.0 V LOW Vinl 0.0 V Top 0 to 70 °C VDD Supply Voltage VDDA Reference Input Voltage Operating Temperature NOTES : 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATINGS conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions not implied. 2. All voltages are measured with respect to VSSA,VDDD unless otherwise specified. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit 4.75 5.0 5.25 V VRT - 5.0 - V VRB - 0.0 - V Digital Input Voltage HIGH Vinh 0.7 VDDD - - V LOW Vinl - - 0.3 VDDD V Top 0 - 70 °C VDD Supply Voltage VDDA Reference Input Voltage Operating Temperature NOTE : It is strongly recommended that to avoid power latch-up all the supply pins(VDDA,VDDD) be driven from the same source. SEC ASIC 3 / 11 ANALOG AL1213H 9BIT 0.5MSPS DAC DC ELECTRICAL CHARACTERISTICS (Converter Specifications : VDD=VDDA=5V, VSS=VSSA=VBB=0V, Top=25°C, VREF=2.5V, DACCTL=0.0V unless otherwise specified.) Characteristics Symbol Min Typ Max Unit Resolution - - 9 - Bits Differential Linearity Error DLE - 0.16 ±1 LSB Integral Linearity Error ILE - 1.1 ±1.5 LSB Maximum Output Voltage - 4.75 5 5.25 V LSB Size - 9.4 9.8 10.1 mV AC ELECTRICAL CHARACTERISTICS (Converter Specifications : VDD=VDDA=5V, VSS=VSSA=VBB=0V, Top=25°C, VREF=2.5V, DACCTL=0.0V unless otherwise specified.) Characteristics Symbol Min Typ Max Unit Test Conditions Conversion Rate fc - - 0.5 MSPS data = 0.5MHz Ivdd 2.0 3.0 7.0 mA Analog Output Delay Td - 190 300 ns Analog Output Rise Time Tr - 230 320 ns Analog Output Fall Time Tf - 230 320 ns Center Code Rising Time Trd - 0.3 0.4 µs Slew Rate SR - 10 12 V/µs tvr - 350 - ns tar - 350 - ns Dynamic Supply Current fc=0.5MHz (load cap=25pF) fc=0.5MHz Data : All High fc=0.5MHz Data : All Low→All High fc=0.5MHz *Reference Voltage Output Responce Time *Analog Output Recovery Time Data : All High→All Low fc=0.5MHz Data : 111111111 → 000000000 fc=0.5MHz Data : All High→All Low VREF(arbitary) DACCTL=High DACCTL=Low Data(arbitary) * Note These above items are verified in simulation SEC ASIC 4 / 11 ANALOG AL1213H 9BIT 0.5MSPS DAC TIMING DIAGRAM D[0]-D[8] DATA VREF DACCTL tvr Td tar 1LSB 90% VREF 50% 1LSB AOUT 10% Tr Ts 1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition. 2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB. 3. Output rise/fall time measured between the 10% and 90% points of full scale transition. FUNCTION DESCRIPTION 1. The AL1213H has a 1-of-512 decoder, a R-String Block for 9bit and an Opamp Block for driving Output. 2. The decoder has 512 digital outputs and only one of them is valid. The R-string block consists of R-array with 512 resistors and 512 CMOS switches and decides to output voltage according to 512 digital inputs generated by 1-of-512 decoder. 3. VRstring = VRT − VRB 8 n ∑ 2 * Dn 29 n= 0 χ η 4. Output of the R-string Block is driven by OPamp. SEC ASIC 5 / 11 ANALOG AL1213H 9BIT 0.5MSPS DAC CORE EVALUATION GUIDE 5V Cc Ct VDD D[8:0] Cc + + Ct VSS MAIN PATH 5V VDDA VSSA VBB al1213h AO UT VREF Cc + DACCTL Ct Ct + Cc SELECT 2.5V 0V TEST PATH LOCATION DESCRIPTION Ct 10µF TANTALUM CAPACITOR Cc 0.1µF CERAMIC CAPACITOR TESTABILITY Whether you use MUX or the internal logic for testability, it is required to be able to select the values of digital inputs ( D[0] ~ D[8] ). See above figure. Only if it is, you can check the main functon ( Linearity ) SEC ASIC 6/ 11 ANALOG AL1213H 9BIT 0.5MSPS DAC PHANTOM CELL INFORMATION VDD VSS VDDA VBB VSSA VSSA VBB VDDA VSS VDD AOUT AL1213H DI Internal / External VREF AB Internal / External AOUT AO Internal / External VDDA AP External VSSA AG External VDD DP External VSS DG External VBB AG External D[6] DACCTL D[5] Internal / External D[8] DI D[0] D[8:0] D[4] Pin Usage D[3] Property D[2] D[1] DACCTL VREF Pin Name D[7] Pin Layout Guide 1. Digital Input Signal lines must have same length to reduce propagation delay. 1. Voltage reference lines (VRT / VRB) must be wide metal to reduce voltage drop of metal lines. 2. VOUT signal should not be crossed by any signals and should not run next to digital signals to minimize capacitive coupling between the two signals. 1. It is recommended that you use thick analog power metal. When connected to PAD, the path should be kept as short as possible. 2. Digital power and analog power are separately used. 1. When the core block is connected to other blocks, it must be double guard-ring using N-well and P+ active to remove the substrate and coupling noise. In that case, the power metal should be connected to PAD directly. 2. The Bulk power is used to reduce the influence of substrate noise. SEC ASIC 7 / 11 ANALOG AL1213H 9BIT 0.5MSPS DAC PACKAGE CONFIGURATION L1 Cc Ct L2 Cc + 5V Ct + 1 VDDA NC 28 2 NC NC 27 3 VBB NC 26 4 VDDA NC 25 5 VSSA AOUT 24 6 NC VREF 23 D[8> 7 D[8] NC 22 D[7] 8 D[7] NC 21 D[6] 9 D[6] VSS 20 D[5] 10 D[5] VDD 19 D[4] 11 D[4] NC 18 D[3] 12 D[3] DACCTL 17 D[2] 13 D[2] NC 16 D[1] 14 D[1] D[0] 15 0V AL1213H LOCATION DESCRIPTION Ct 10µF TANTALUM CAPACITOR Cc 0.1µF CERAMIC CAPACITOR L1,L2 FERRITE BEAD ( 0.1mh ) SEC ASIC 8 / 11 AOUT VREF(5V) Cc Ct + DACCTL(0V) D[0] ANALOG AL1213H 9BIT 0.5MSPS DAC PACKAGE PIN DESCRIPTION NAME PIN NO I/O TYPE PIN DESCRIPTION VDDA 1,4 AP Analog Power VBB 3 AG Analog Ground VSSA 5 AG Analog Ground D[0] ~ D[8] 7~15 DI Digital Input Data DACCTL 17 DI Digital Input Data VDD 19 DP Digital Power VSS 20 DG Digital Ground VREF 23 AI Voltage Reference Voltage (2.5V) AOUT 24 AO Analog Voltage Output DO No Connection NC SEC ASIC 2,6,7,16,18,21 22,25,26,27,28 9 / 11 ANALOG AL1213H 9BIT 0.5MSPS DAC PC BOARD LAYOUT CONSIDERATIONS PC Board Considerations To minimize noise on the power lines and the ground lines, the digital inputs need to be shielded and decoupled. This trace length between groups of VDD (VDDA,VDD) and VSS (VSSA,VSS) pins should be as short as possible so as to minimize inductive ringing. Supply Decoupling and Planes For the decoupling capacitor between the power line and the ground line, 0.1µF ceramic capacitor is used in parallel with a 10µF tantalum capacitor. The digital power plane(VDD) and analog power plane(VDDA) are connected through a ferrite bead, and also the digital ground plane(VSS) and the analog ground plane(VSSA). This ferrite bead should be located within 3inches of the AL1213H. The analog power plane supplies power to the AL1213H of the analog output pin and related devices. SEC ASIC 10 / 11 ANALOG AL1213H 9BIT 0.5MSPS DAC FEEDBACK REQUEST We appreciate your interest in out products. If you have further questions, please specify in the attached form. Thank you very much. DC / AC ELECTRICAL CHARACTERISTIC Characteristics Min Typ Max Unit Supply Voltage V Power dissipation mW Resolution Bits Analog Output Voltage V Operating Temperature °C Output Load Capacitor µF Output Load Resistor Ω Integral Non-Linearity Error LSB Differential Non-Linearity Error LSB Maximum Conversion Rate MHz Remarks VOLTAGE OUTPUT DAC Reference Voltage TOP V BOTTOM Analog Output Voltage Range Digital Input Format V Binary Code or 2's Complement Code CURRENT OUTPUT DAC - Analog Output Maximum Current mA Analog Output Maximum Signal Frequency MHz Reference Voltage V External Resistor for Current Setting(RSET) Ω Pipeline Delay sec Do you want to Power down mode? Do you want to Interal Reference Voltage(BGR)? Which do you want to Serial Input TYPE or parallel Input TYPE? Do you need 3.3v and 5v power supply in your system? SEC ASIC 11 / 11 ANALOG AL1213H 9BIT 0.5MSPS DAC HISTORY CARD Version Date Modified Items Ver 1.0 Jun.'98 Original version published Ver 2.0 Feb.'00 Core layout Guide update Ver 2.1 Apr.'02 Phantom Cell information update SEC ASIC Comments ANALOG